Showing papers on "Clock synchronization published in 1976"

Automatic data synchronizer

Abstract: Disclosed is a device for automatically synchronizing incoming digital data with a local clock. Incoming clock pulses are compared with the local clock pulses after being delayed by a sufficient amount to produce synchronization between the incoming and local clock pulses. The incoming data pulses are delayed by the same amount as the incoming clock pulses so that they too are synchronized with the local clock. Both digital delays are variable and may be used to provide both fractional clock period delays or multiple clock period delays for accurate synchronization over a relatively long communications cycle.

Clock synchronization system

Abstract: In a fail soft synchronization clock system having a plurality of central processing units and a plurality of input-output units operably connected to one or more remotely located volatile cache memories there is provided a free-running, non-synchronized clock in each central processing unit. The clock outputs are connected to sets of synchronizing clock system logic circuits, one for each central processing unit, which disable the clocks of all other central processing units and selects their own associated clock as the input for producing a plurality of synchronized outputs employed in turn to time the operation of the processing system which is operably connected to the cache memories.

Satellite controlled digital clock system

Abstract: A method and apparatus are provided for maintaining and correcting a time ference in a satellite controlled digital clock system A time code message including time-of-year information and satellite position information is transmitted in a data stream from a transmitter on earth to a satellite orbiting the earth to be relayed back to receivers located around the world The data is transmitted at a precise data rate According to the invention, a local clock oscillator is phase locked with the precise data rate, thereby providing the clock system with time-of-year information by counting the pulses produced by the local oscillator At the same time, the digital clock system assembles the time code message from the received data stream and compares the message with the time accumulated by counting the pulses produced by the oscillator After a predetermined number of errors are detected by such comparisons, the clock system resets itself to coincide with the received time code message If transmission of the time code message is interrupted, the clock continues counting pulses produced by the local oscillator and thereby continues keeping time undisturbed In a preferred embodiment, the digital clock system is implemented with a firmware programmed micro-computer and the time-of-year and satellite position information is displayed on light emitting diode digital displays

Time division system for synchronizing functions controlled by different clocks

Abstract: Synchronization control circuit for a time divisional data transmitting and receiving system. Data is received at an exchange at a clock rate determined by the transmitting station and is stored in memory at that rate. Read-out of data from the memory is based on the internal clock rate of the exchange. Since only one operation -- read or write -- can occur on a memory at any one time and the operations are controlled at rates which may be out of synchronism with one another, conflicts may occur. To prevent such conflicts, a time shift of predetermined duration is inserted between operations when the out-of-synchronism interval is less than a predetermined time interval.

Master/slave clock arrangement for providing reliable clock signal

Abstract: The outputs of two like frequency oscillators are combined to form a single reliable clock signal, with one oscillator functioning as a slave under the control of the other to achieve phase coincidence when the master is operative and in a free-running mode when the master is inoperative so that failure of either oscillator produces no effect on the clock signal.

Discrete-control correction A technique for the synchronization of digital communication networks

Abstract: Discrete-control correction is a method of synchronizing the clocks of a digital communication network by means of periodic corrections to their frequencies, the correction to each clock being derived from the change in the buffer level at that node. This paper presents a comprehensive treatment of this method and extends the results of earlier papers to more general situations. It is shown that there is a set of conditions, one for each node, which is sufficient to establish network synchronism. Explicit formulae are derived for the frequency of synchronism and the steady-state buffer levels. It is shown also that the master—slave scheme of synchronization, in which the clocks of the network are synchronized to a designated master clock, is obtained as the special case of discrete-control correction in which corrections are made to all the clocks except the master clock. It is pointed out that in the event of disruption of a part of the network, the surviving part or parts of the network are assured of r...

Comparison of Bit Synchronization Schemes Using AM and Summed Clocks

Abstract: This paper considers bit synchronization through the use of a separate clock signal which is either amplitude modulated onto or summed with the data signal. For continuous data transmission, such schemes are known to be inferior, in the sense of efficient use of power, to schemes which derive synchronization directly from the data signal. However, these techniques have application in burst systems such as spacecraft command systems, and in systems where receiver simplicity is more important than power conservation. For systems in which the composite data-clock signal subsequently modulates an RF carrier, it is shown that the summed clock signal performs slightly better than the AM clock signal, and that for both signal types, the optimum allocation of power between data and clock is approximately 9:1.