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Showing papers on "Clock synchronization published in 1984"


Proceedings ArticleDOI
27 Aug 1984
TL;DR: A new fault-tolerant algorithm for solving a variant of Lamport's clock synchronization problem for a system of distributed processes that communicate by sending messages, which solves the problem of maintaining closely synchronized local times, assuming that processes' local times are closely synchronized initially.
Abstract: We describe a new fault-tolerant algorithm for solving a variant of Lamport's clock synchronization problem. The algorithm is designed for a system of distributed processes that communicate by sending messages. Each process has its own read-only physical clock whose drift rate from real time is very small. By adding a value to its physical clock time, the process obtains its local time. The algorithm solves the problem of maintaining closely synchronized local times, assuming that processes' local times are closely synchronized initially. The algorithm is able to tolerate the failure of just under a third of the participating processes. It maintains synchronization to within a small constant, whose magnitude depends upon the rate of clock drift, the message delivery time, and the inital closeness of synchronization. We also give a characterization of how far the clocks drift from real time. Reintegration of a repaired process can be accomplished using a slight modification of the basic algorithm. A similar style algorithm can also be used to achieve synchronization initially.

331 citations


Journal ArticleDOI
TL;DR: It is proved that, even if the clocks all run at the same rate as real time and there are no failures, an uncertainty of e in the message delivery time makes it impossible to synchronize the clocks of n processes any more closely than e(1−1/ n ).
Abstract: The problem of synchronizing clocks of processes in a fully connected network is considered. It is proved that, even if the clocks all run at the same rate as real time and there are no failures, an uncertainty of e in the message delivery time makes it impossible to synchronize the clocks of n processes any more closely than e(1−1/ n ). A simple algorithm is given that achieves this bound.

266 citations


Proceedings ArticleDOI
27 Aug 1984
TL;DR: Two simple efficient distributed algorithms are given: one for keeping clocks in a network synchronized and one for allowing new processors to join the network with their clocks synchronized.
Abstract: This paper gives two simple efficient distributed algorithms: one for keeping clocks in a network synchronized and one for allowing new processors to join the network with their clocks synchronized. The algorithms tolerate both link and node failures of any type. The algorithm for maintaining synchronization will work for arbitrary networks (rather than just completely connected networks) and tolerates any number of processor or communication link faults as long as the correct processors remain connected by fault-free paths. It thus represents an improvement over other clock synchronization algorithms such as [LM1,LM2,LL1]. Our algorithm for allowing new processors to join requires that more than half the processors be correct, a requirement which is provably necessary.

189 citations


Proceedings ArticleDOI
01 Dec 1984
TL;DR: This work shows that clock synchronization is achievable, without authentication, as long as the faults do not disconnect the network, and provides a lower bound on the closeness to which simultaneity can be achieved in the network as a function of the transmission and processing delay properties of the network.
Abstract: It is known that clock synchronization can be achieved in the presence of faulty clocks numbering more than one-third of the total number of participating clocks provided that some authentication technique is used. Without authentication the number of faults that can be tolerated has been an open question. Here we show that if we restrict logical clocks to running within some linear function of real time, then clock synchronization is impossible, without authentication, when one-third or more of the processors are faulty. However, if there is a bound on the rate at which a processor can generate messages, then we show that clock synchronization is achievable, without authentication, as long as the faults do not disconnect the network. Finally, we provide a lower bound on the closeness to which simultaneity can be achieved in the network as a function of the transmission and processing delay properties of the network.

140 citations


Proceedings ArticleDOI
27 Aug 1984
TL;DR: An informal description is given of three fault-tolerant clock-synchronization algorithms that work in the presence of arbitrary kinds of failure, including “two-faced” clocks.
Abstract: An informal description is given of three fault-tolerant clock-synchronization algorithms. These algorithms work in the presence of arbitrary kinds of failure, including “two-faced” clocks. Two of the algorithms are derived from Byzantine Generals solutions.

111 citations


Patent
03 Aug 1984
TL;DR: In this article, a decoder suitable for use in a paging receiver of the type responsive to a transmission which includes a preamble sequence followed by batches each containing a synchronization word followed by a plurality of address and/or message words is operative to detect a single synchronization word.
Abstract: In a decoder suitable for use in a paging receiver of the type responsive to a transmission which includes a preamble sequence followed by batches each containing a synchronization word followed by a plurality of address and/or message words, the decoder is operative to detect a single synchronization word. Thereafter, the decoder is powered up to search in its specific frame in each batch by means of a clock which has been synchronized with the transmission and which provides the timing for searching in the specific frame of all subsequent batches. The clock may have coarse and fine modes of timing control, the coarse mode being applicable when initial bit synchronization is being attained, and the fine mode being applied subsequently to reduce the risk of the clock drifting out of synchronization.

51 citations


Patent
John William Ballance1
20 Sep 1984
TL;DR: In this article, the authors propose to synchronize the receive clock with the master send clock when there is no reception in a point to multipoint (P2P) system.
Abstract: @ The node of a point to multipoint data telecommunications system needs a receive clock to regenerate the data. The conventional method of regenerating the clock from received signals is difficult because there are gaps when no outstation is active. The invention reduces these problems by synchronising the receive clock with the master send clock when there is no reception.

40 citations


Patent
02 Mar 1984
TL;DR: In this article, the disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system, which eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.
Abstract: The disclosed clock adjustment method and apparatus utilizes a periodically transmitted positive or negative predetermined fixed increment clock phase adjustment signal to phase adjust the clocks of the system. The transmitter clock is periodically compared with a common reference clock and a fixed increment clock adjustment signal is transmitted to the receiver which adjusts its clock by applying the fixed increment clock adjustment signal to the common reference clock. The utilization of a predetermined fixed increment clock phase adjustment signal eliminates the need to send the resolution of the clock adjustment and hence reduces the number of data bits required to send clock information over the communication channel.

35 citations


Patent
26 Jun 1984
TL;DR: In this article, a color reference signal produced by a color oscillator is coupled to a frequency converter that generates a signal having a frequency that is a multiple of that of the colour reference signal.
Abstract: A color reference signal produced by a color oscillator is coupled to a frequency converter that generates a signal having a frequency that is a multiple of that of the color reference signal. The phase of the frequency converter output signal is adjusted in accordance with the phase of the clock synchronization sequence pulses of a teletext data line signal to produce a regenerated clock. Edges of the regenerated clock define the times in which corresponding bits of the teletext data line contain valid digital information.

22 citations


Patent
01 Feb 1984
TL;DR: In this article, the error between the remote software clock and the accurate clock is determined and a correction factor is also downloaded which attempts to correct the error, in addition to periodically downloading the correct time to the software clock.
Abstract: Apparatus and methods for correcting a software clock remote from an accurate clock, which include determining the error between the remote software clock and accurate clock, and in addition to periodically downloading the correct time to the software clock, a correction factor is also downloaded which attempts to correct the error.

14 citations


Patent
06 Jun 1984
TL;DR: In this article, the first data bit is detected at a detection circuit in reference to the plurality of clock pulses, and according to the detected timing, a selector circuit selects one of the clock pulses with a predetermined constant phase difference from the received data signal.
Abstract: A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal. The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.

Patent
Darrell Boots Irvin1
28 Mar 1984
TL;DR: In this article, a method and apparatus for generating two phase-locked digital clocks of different word rates was presented for a graphic and alphanumeric computer display terminal, where the master and slave clock generators were used to generate output pulses at every N-th and M-th clocks of a common clock.
Abstract: @ A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.

01 Aug 1984
TL;DR: A general formal model to describe a system of distributed processes, each of which has its own clock is presented, and it is proved that even if the clocks run at a perfect rate, an uncertainty of in the known message delivery time makes it impossible to synchronize the clocks of n processes any more closely than 2.
Abstract: Keeping the local times of processes in distributed system synchronized in the presence of arbitrary faults is important in many applications and is an interesting theoretical problem in its own right. In order to be practical, any algorithm to synchronize clocks must be able to deal with process failures and repairs, clock drift, and varying message delivery times, but these conditions complicate the design and analysis of algorithms. In this thesis, a general formal model to describe a system of distributed processes, each of which has its own clock is presented. The processes communicate by sending messages to each other, and they can set timers to cause themselves to take steps at some future times. It is proved that even if the clocks run at a perfect rate and there are no failures, an uncertainty of in the known message delivery time makes it impossible to synchronize the clocks of n processes any more closely than 2 (1 -1/n). A simple algorithm that achieves this bound is given to show that the lower bound is tight. Two fault-tolerant algorithms are presented and analyzed, one to maintain synchronization among processes whose clocks initially are close together, and another to establish synchronization in the first place. Both handle drift in the clock rates, uncertainty in the message delivery time, and arbitrary failure of just under one third of the processes. The maintenance algorithm can be modified to allow a failed process that has been repaired to be reintegrated into the system. A variant of the maintenance algorithm is used to establish the initial synchronization. It was also necessary to design an interface between the two algorithms since we envision the processes running the start-up algorithm until the desired degree of synchronization is obtained, and then switching to the maintenance algorithm.

Journal ArticleDOI
TL;DR: The slip mechanism and the alternative methods of its minimization, i.e. the use of high accuracy clocks working in a plesiochronous mode or the phase locking of nodal clocks to a reference clock are discussed.
Abstract: The timing of signals and processes within integrated digital networks requires careful control in order to minimize signal degradation through the occurrence of slip. The paper discusses the slip mechanism and the alternative methods of its minimization, i.e. the use of high accuracy clocks working in a plesiochronous mode or the phase locking of nodal clocks to a reference clock.The progress of relevant international standardization activities in CCITT is discussed, particularly in relation to the specification of reference clocks, limits for tolerable slip performance and equipment design limits to cater for wander and jitter in the network.The approach taken to timing control within the international network and to synchronization techniques adopted by certain administrations with respect to synchronization methodology and network topology, clock configurations and interconnecting timing links are also given.

01 Sep 1984
TL;DR: A validation method for the synchronization subsystem of a fault tolerant computer system is investigated, and an asymptotic approach to estimation in the tail of a distribution is employed.
Abstract: A validation method for the synchronization subsystem of a fault tolerant computer system is investigated. The method combines formal design verification with experimental testing. The design proof reduces the correctness of the clock synchronization system to the correctness of a set of axioms which are experimentally validated. Since the reliability requirements are often extreme, requiring the estimation of extremely large quantiles, an asymptotic approach to estimation in the tail of a distribution is employed.

Journal ArticleDOI
TL;DR: In this paper, the authors compare the behavior required for clocks to maintain synchrony in the group of coordinate frames that leaves Maxwell's equations invariant, and show that the need for adjustment is due to the well known invariance of the equations under a group of transformations larger than the Lorentz group, and not due to imperfections in clocks.

Patent
24 Apr 1984
TL;DR: In this article, a correction part was proposed to prevent the adverse influence caused by troubles in a triplex system by providing a correction, which reproduces a clock waveform having a certain width with the aid of an edge of an output waveform obtained by majority decision and outputs it, on an output of a clock synchronizing circuit of each system.
Abstract: PURPOSE:To prevent the adverse influence caused by troubles in a triplex system by providing a correction part, which reproduces a clock waveform having a certain width with the aid of an edge of an output waveform obtained by majority decision and outputs it, on an output of a clock synchronizing circuit of each system. CONSTITUTION:Respective systems A-C comprising a triplex system have clock synchronizing parts Sa-Sc with the same constitution, which are impressed by original clocks ocp1-ocp3 from a clock generator circuit provided on respective systems, synchronize clocks and output majority decision clocks mjcp1-mjcp3 of the same frequency. The clock synchronizing part Sa divides original clocks of its own system by a frequency dividing counter 1 and decides its output dcp1 and inputs dcp2 and dcp3 from other systems by majority in a majority decision circuit 2. Said part Sa compares the order of its output mjcp1 with that of the output of the counter 1 and judges whichever that its own system is any one of an advancing system, intermediate one and delay one. According to the result, the counter 1 is controlled by a control circuit 3, and a correction part Ca generates an output ccp with a certain width from the output mjcp1.

02 Apr 1984
TL;DR: In this article, the MKIII VBLI system was compared with traveling cesium clocks and GPS for clock synchronization at sub-nanosecond levels, and the results showed that the system appeared to be very good benchmark system against which future time synchronization systems can be evaluated.
Abstract: It is well known that Very Long Baseline Interferometry (VLBI) is capable of precise time synchronization at subnanosecond levels. This paper deals with a demonstration of clock synchronization using the MKIII VBLI system. The results are compared with clock synchronization by traveling cesium clocks and GPS. The comparison agrees within the errors of the portable clocks (+ 5 ns) and GPS(+ or - 30 ns) systems. The MKIII technology appears to be capable of clock synchronization at subnanosecond levels and appears to be very good benchmark system against which future time synchronization systems can be evaluated.

Patent
10 Jan 1984
TL;DR: In this paper, the authors propose a scheme to simplify a phase adjustment and facilitate synchronization by providing each processor with a clock generating circuit and putting the clock generating circuits in phase under the control of a master processor.
Abstract: PURPOSE:To simplify a phase adjustment and to facilitate synchronization, by providing each processor with a clock generating circuit and putting the clock generating circuits in phase under the control of a master processor. CONSTITUTION:The master processor 2 controls an AND circuit 7, 8, or 9 while placing a clock generating circuit 4 in operation. Consequently, the output of the clock generating circuit 4 is synchronized with the output of the clock generating circiit 5-1 of a slave processor 3-1 while the clock generating cirduit 5-1 is in operation. Other slave processors 3-2, 3-3... are synchronized on the basis of the output of the clock generating circuit 4 of the master processor 2.

Journal ArticleDOI
H W. Barz1
TL;DR: It is shown that some synchronization mechanisms cannot implement programs based on another mechanism without some loss in parallelism, i.e., a reduced measure.
Abstract: A common question in parallel programming is How to implement a program efficiently for a particular synchronization problem? Here we pose a more general question: Is a certain synchronization mechanism capable of implementing efficiently a particular synchronization problem represented by a program using another synchronization mechanism? We give a definition of “implementing efficiently” which measures efficiency by the amount of parallelism of the parallel programs. If this measure is reduced by the implementation the efficiency of the implementation is inferior. It is shown that some synchronization mechanisms cannot implement programs based on another mechanism without some loss in parallelism, i.e., a reduced measure. These results imply a power hierarchy (or efficiency hierarchy) of synchronization mechanisms. A further outcome of this paper is that simple synchronization mechanisms, with only a few variables, are capable of implementing any synchronization problem implementable by more powerful me...

Proceedings ArticleDOI
01 Jan 1984
TL;DR: A validation method for the synchronization subsystem of a fault-tolerant computer system is presented and utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof.
Abstract: A validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating an experimental implementation of the Software Implemented Fault Tolerance (SIFT) clock synchronization algorithm. The design proof of the algorithm defines the maximum skew between any two nonfaulty clocks in the system in terms of theoretical upper bounds on certain system parameters. The quantile to which each parameter must be estimated is determined by a combinatorial analysis of the system reliability. The parameters are measured by direct and indirect means, and upper bounds are estimated. A nonparametric method based on an asymptotic property of the tail of a distribution is used to estimate the upper bound of a critical system parameter. Although the proof process is very costly, it is extremely valuable when validating the crucial synchronization subsystem.