Showing papers on "Clock synchronization published in 1986"

Easy impossibility proofs for distributed consensus problems

Abstract: Easy proofs are given, of the impossibility of solving several consensus problems (Byzantine agreement, weak agreement, Byzantine firing squad, approximate agreement and clock synchronization) in certain communication graphs. It is shown that, in the presence ofm faults, no solution to these problems exists for communication graphs with fewer than 3m+1 nodes or less than 2m+1 connectivity. While some of these results had previously been proved, the new proofs are much simpler, provide considerably more insight, apply to more general models of computation, and (particularly in the case of clock synchronization) significantly strengthen the results.

Method and apparatus for clock management

Abstract: Disclosed is a method, and apparatus implementing that method, for synchronizing and managing the "system clocks" maintained by each of a number of processor units forming a multiprocessor system. Based on an averaging technique, the method includes creating a synchronization message by an originator processor unit and routing that message to other of the processor units to obtain clock values representative of each of the system clocks of each processor unit. The average clock value is then determined and that average clock value then rerouted to each of the processor units to permit them to update, if necessary, their individual system clocks to the average of all. The method further includes determining the transit times encountered by the various messages so that each processor unit can adjust the average clock value it will use to update or synchronize its system clock to account for such transit times.

A Paradigm for Reliable Clock Synchronization

Abstract: Existing fault-tolerant clock synchronization protocols are shown to result from refining a single clock synchronization paradigm. In that paradigm, a reliable time source periodically issues messages that cause processors to resynchronize their clocks. The reliable time source is approximated by reading all clocks in the system and using a convergence function to compute a fault-tolerant average of the values read. The performance of a clock synchronization algorithm based on the paradigm can be quantified in terms of the two parameters that characterize the behavior of the convergence function used: accuracy and precision.

Slot Synchronization in Optical PPM Communications

Abstract: Maintaining slot clock synchronization in a baseband pulse position modulated (PPM) communication link is vital to its performance. This paper examines the slot clocking design associated with a direct detection, photodetecting optical PPM system. Although theoretical PPM synchronizers for optical links have been derived in the past, there is still interest in finding more practical, simpler, and easier-to-implement clocking subsystems. In this paper several types of practical slot synchronizers are considered. A basic design involving analog correlators and slot gating is presented, along with an indication of its performance. Several alternative designs are also presented, including digital synchronizers in which time samples are used for loop control. The advantage in digital systems is that more extensive processing can be handled in software, allowing the loop to perform closer to the ideal. Design procedures for digital clocking are presented, and optimal laser pulse shaping and filtering are discussed. Performance in terms of loop models and tracking error variance is included.

Almost) No Cost Clock Synchronization

Abstract: We show how synchronized clocks can be realized in a distributed system as a byproduct of a common communication paradigm where processors periodically perform broadcasts. Our approach decouples the precision concern-limiting how much correct clocks can differ from each other-and the accuracy concern-limiting how much any correct clock can differ from real time-of clock synchronization. Given a system that guarantees only precision, we develop a protocol whereby high accuracy can be achieved on demand. In this manner, the ``lazy'''' protocol we obtain incurs the cost of high accuracy only when needed while keeping the basic synchronization procedure extremely simple and cheap.

Byzantine clock synchronization

Abstract: An informal description is given of three fault-tolerant clock-synchronization algorithms. These algorithms work in the presence of arbitrary kinds of failure, including "two-faced" clocks. Two of the algorithms are derived from Byzantine Generals solutions.

A Performance Evaluation of the Software-Implemented Fault-Tolerance Computer

Abstract: The results of a performance evaluation of the Software-Implemented Fault-Tolerance (SIFT) computer system conducted in the NASA Avionics Integration Research Laboratory are presented. The essential system functions are described and compared to both earlier design proposals and subsequent design improvements. Using SIFT's specimen task load, the executive tasks, such as reconfiguration, clock synchronization, and interactive consistency, are found to consume significant computing resources. Together with other system overhead (e.g., voting and scheduling), the operating system overhead is in excess of 60%. The authors propose specific design changes that reduce this overhead burden significantly.

A Virtual Time CSMA Protocol for Hard Real Time Communication.

Abstract: We study a virtual time CSMA protocol for hard real time communication systems where messages have explicit deadlines. In this protocol, each node maintains two clocks: a real time clock and a virtual time clock. Whenever a node finds the channel to be idle, it resets its virtual clock to be equal to the real clock. The virtual clock then runs at a higher rate than the real clock. A node transmits a waiting message when the time on the virtual clock is equal to the latest time to send the message. This protocol implements the minimum-laxity-first transmission policy. We compare the performance of our protocol with two baseline protocols both of which transmit messages according to the minimum-laxity-first policy. While both use perfect state information about the nodes and channel, the first is an idealized protocol which obtains this information without paying any cost and the second one pays a reasonable price for it. The simulation study shows that in most cases, our protocol performs close to the first one and better than the second one.

Phase synchronization system

Abstract: Basic operation clock generators for effecting frequency division of the system clock are provided for respective ones of a plurality of processors, and the basic operation clock generators associated with respective processors are connected in cascade. The basic operation clock generator of the preceding stage produces a synchronization signal in response to each particular state of the basic operation clock signal and supplies the synchronization signal to a basic operation clock generator of a succeeding stage, and the basic operation clock generator of the succeeding stage establishes the initial state in the basic operation clock signal by using the synchronization signal supplied from the basic operation clock generator as a control signal, whereby the phases of basic operation clock signals of respective processors are matched to each other.

Triplicated clock distribution device for use when each clock signal comprises a synchonization signal

Abstract: A triplicated clock distribution device, for use where each clock signal comprises a synchronization signal, comprises three slave clocks connected to receivers. Each slave clock comprises a clock generator and a synchronization generator and delivers a clock signal incorporating a synchronization signal the frequency of which is half that of the clock signal. Each receiver comprises a clock regenerator and a synchronization regenerator which respectively deliver a clock signal and a synchronization signal to user circuits to which the receiver is connected.

Digital signal transmission system having frame synchronization operation

Abstract: A digital signal transmission system includes a synchronization pattern detection circuit for detecting a synchronization pattern in response to a received transmitted digital signal, a pseudo synchronization detection circuit for detecting a pseudo synchronization pattern in the form of cyclic redundancy code in response to a received transmitted digital signal, and a synchronization protection circuit for counting the synchronization pattern detection signals produced when synchronization patterns are detected in response to a synchronization pattern detection signal from the synchronization pattern detection circuit. The synchronization protection circuit includes a main synchronization counter circuit and an auxiliary synchronization counter circuit. The count of protection steps for the confirmation of synchronization recovery of the auxiliary synchronization counter circuit in accordance with synchronization or asynchronization of the main synchronization counter circuit is variable.

Method for clock-synchronization of a signal receiver

Abstract: In a method for clock synchronization of a signal receiver, the demodulated received signal is sampled in each of the subintervals over N time windows having in each case K subintervals (1A . . . 4C). In each case, the dispersion is calculated for the sampled values of N corresponding subintervals and the K dispersion values obtained are compared with each other. The optimum sampling time is derived from the position in time of the minimum dispersion value.

Impact of Communciation Networks on Fault-Tolerant Distributed Computing

Abstract: When the desired reliability of a computing system exceeds that of its individual hardware components the need for fault-tolerant systems arise. While distributed systems have the potential to achieve highly reliable computing, programming them is a challenging task. Several paradigms have been identified that can simplify the conceptual design of fault-tolerant distributed systems. Properties of a distributed system have profound implications on the solvability and efficiency of implementations of these paradigms. In this thesis we study the effect that different communication models have on the efficiency of fault-tolerant computing. As an instance of a fundamental operation we examine protocols for reliable broadcast in distributed systems. Our main contribution is the characterization of the time complexity of reliable broadcast with respect to communication models. A practical consequence of our results is the development of efficient reliable broadcast protocols with respect to communication models. A variety of common networks are shown to support this style of communication. In fact, by parameterizing the minimum multicast size and diameter of these networks, we are able to characterize all known network architectures. Distributed systems where processors perceive the same approximate time makes programming them much easier. Clock synchronization protocols implement this abstraction given only clocks that have bounded drift rates with respect to real time. We show how a primitive which is normally used only for communication in a distributed system can also be used for synchronizing clocks. If this primitive occurs naturally with a sufficient frequency, clock synchronization can be achieved at no additional message cost. Our results reveal hardware/software tradeoffs between performance, resiliency and network cost. Thus, they offer many new alternatives previously not considered in designing fault-tolerant systems.

Clock control system for network synchronization

Abstract: PURPOSE: To attian the synchronizing control of an equipment connected always to a communication system by detecting the absence of a network synchronization clock so as to apply a prescribed fixed voltage to a clock source, thereby generating the clock internally. CONSTITUTION: The network synchronizing clock and a feedback clock from a clock source 101 are subjected to phase comparison by a phase comparing means 102, a control voltage from the means 102 is supplied to output a clock synchronously with the network synchronizing clock from the clock source 101. On the other hand, when the absence of the network synchronizing clock is detected by an input interruption detection circuit 103, a changeover means 104 selects a fixed voltage similar to the control voltage from the means 102 generated from the clock source 101 to supply the clock synchronously with the network synchronizing clock to the clock source 101. Thus, even when the network synchronizing clock is absent, the synchronizing clock is generated synchronously with the network synchronizing clock in the inside of the equipment and the equipment connected to the communication system is subjected to excellent synchronization control at all times. COPYRIGHT: (C)1988,JPO&Japio

A Telephone-Based Time Dissemination System

Abstract: : Telephone time dissemination can serve a broad spectrum of users who require time accuracy in the millisecond range and who are reluctant to use radio time dissemination services. A system which uses a simple protocol for telephone loop-delay correction is presented. The protocol uses ASCII characters transmitted by the frequency shift keying techniques of standard 300 baud modems. The protocol is designed for the transfer of the correct time from a master clock to a slave clock. The slave clock places the telephone call, puts the master clock into a prompt echo mode, measures the loop delay time, and applies half the loop delay time as a correction to the time it receives from the master clock. The precision and accuracy of this protocol are discussed and measurements are presented on the precision of time transfer using Leitch CSD-5300 units as master and slave clocks. The capabilities of the full system, and the Leitch CSD 5300 units which are used at each distribution node, are discussed as possible solutions to questions that are often addressed (or misaddressed) to "Precise Time" research groups.

Clock synchronizing circuit

Abstract: PURPOSE:To quicken the reception leading time and to prevent deterioration of reception characteristics by changing the operating count number of an up-down counter of a digital PLL used for synchronous detection depending on the presence of establishment of clock synchronization. CONSTITUTION:A base band signal received from an input terminal 12 is inputted to a differentiation circuit 13 and a reception clock is reproduced from the extracted reception clock component by using a digital PLL comprising a phase comparator circuit 14, an up-down counter 16, a variable frequency division circuit 17, a frequency division circuit 18, an oscillation circuit 19 and a crystal oscillator 20.An up-down counter 23 outputs an establishment of clock synchronization to a count control circuit 15 and the operation count number of the up-down counter 16 is changed.

Designing fault-tolerant algorithms for distributed systems using communication primitives

Abstract: Fault-tolerance is an important requirement in distributed computing systems. However, designing applications for distributed systems is a difficult task, particularly when components of the system can fail. The difficulty of this task increases with the severity of failures encountered. Arbitrary process failures are generally much harder to overcome than failures that are restricted, e.g., where processes only fail by halting. Thus, techniques that restrict the disruptive behavior of faulty processes can greatly simplify the design of fault-tolerant algorithms. Such techniques effectively provide reduction mechanisms from one class of failures to a more benign class. Message authentication is an example of a technique that imposes restrictions on the externally visible behavior of faulty processes. This technique has been used to derive simple solutions to many problems of fault-tolerance for systems with arbitary faults. To exploit the simplicity provided by authentication, we present communication primitives that provide properties of authentication without using digital signatures. These primitives can also be extended to provide properties beyond those of authentication, thereby further restricting the types of faults that have to be overcome. These communication primitives lead to a general methodology for designing fault-tolerant algorithms. We first design an algorithm assuming that messages are signed. Then, replacing signed communication in this algorithm with our broadcast primitive automatically results in an equivalent non-authenticated algorithm. We illustrate this methodology by deriving new solutions to the problems of distributed agreement and clock synchronization in the presence of faults. Our solutions to the problems of Byzantine Agreement, early-stopping Byzantine Agreement, Byzantine Elections, and clock synchronization are simpler and more efficient than those previously known. Furthermore, the clock synchronization algorithm that we propose is the first one that achieves optimal accuracy with respect to real time.

Two-screen television receiver

Abstract: PURPOSE:To realize a two-screen television receiver with high resolution and high picture quality using a low-cost method by mounting two line-memory at least and screen change-over means and controlling not only a selective fetching means but also clock synchronization of fetch/read clocks against line memories. CONSTITUTION:Left half of the two-screen television receiver displays the image inputted from a video signal input terminal 61, while right half displays the image inputted from a external signal input terminal 62. When two screens are displayed, the control signal c of the switching circuit 65 must not be fixed at either 'high' or 'low' speed, but is set to switch 'high' and 'low' at high speed and select reciprocally the input signals a and b in the switching circuit 65. At this time, the frequency fc of the control signal c must be one half of the sampling clock frequency fck of the A/D converters 661 to 663. Thus high- quality picture images can be obtained by mounting only line memories and converting a scanning method to 1:1 non-interlacing method.

Transmission and reception of synchronous data and timing signals using a steady bit stream

Abstract: In an telecommunications switching system, user clock data is "massively sampled" at the source node with reference to a global clock signal, and reconstructed with no more than allowable error at the destination. Massive sampling and reconstruction of the clock signal allows users of the transmission system to send data at arbitrary data rates and to perform their own clock synchronization at a different protocol level from the hardware switching system. Direct use of the global system clock rate of approximately 192 kilobits per second (kbps) is provided for by synchronizing the user data with the global clock signal.

Clock synchronization circuit for a timer

Abstract: A timing system (Fig. 1) ordinarily includes: a timer circuit (24), a source (11, 14) of first clock pulses for advancing the timer circuit, and a circuit (16, 18) for reading out the timer circeit in delayed synchronizism with the clock pulses. In order to allow the timer circuit to be advanced by second clock pulses from a second source (29), where the second clock pulses are asynchronous with respect to the first clock pulses, there is provided a synchronizing or storage circuit (32) for storing an indication of the occurrence of each second clock source pulse. The timer circuit is advanced only when there are present the stored indication and the next-occurring first clock pulse. The stored indication thereafter is erased, in anticipation of receipt of the next-occurring second clock pulse.

Measuring time in Cm

Abstract: A system clock is often used as a time-keeping device for measuring software performance. Obtaining accurate clock reading in a distributed system with only one system clock may be difficult due to communication delays and clock contention. This paper investigates the problems associated with a single time base in multiprocesso r systems and uses the Cm* multiprocessor as a research vehicle. First, the accuracy of the reported time was found to be greatly affected by the number of simultaneous clock reads and overall system workload. Second, methods were developed to compensate the clock readings by monitoring the system load during the time measurements. These methods correct readings so that they are within 7/xS. of the actual time that the clock read request is issued. Finally, to demonstrate the utility of the methods, an experiment was performed to measure die latency of messages and message-based remote procedure calls.

Clock path phase errors

Abstract: This paper aims at the total design of synchronizing clock phase quality in a master-slave synchronization network and studies the clock path phase errors. In master-slave synchronization, reference clock distribution paths are a major source of phase errors. It is useful to examine the phase errors using Time Interval Error (TIE), specified in units of time. In this paper, the TIE of clock paths containing multiplexers, digital transmission lines and digital synchronous terminals is analyzed. Then measurements taken for multiplexers are presented by varying a stuffing ratio. Field data taken for a 7-link clock path, the longest effective link path in Japan, shows that in practice a TIE of less than 100 ns over a 102 – 103 s measurement period is measured, which agrees well with theoretical data.