Showing papers on "Clock synchronization published in 1987"

Clock Synchronization in Distributed Real-Time Systems

Abstract: The generation of a fault-tolerant global time base with known accuracy of synchronization is one of the important operating system functions in a distributed real-time system. Depending on the types and number of tolerated faults, this paper presents upper bounds on the achievable synchronization accuracy for external and internal synchronization in a distributed real-time system. The concept of continuous versus instantaneous synchronization is introduced in order to generate a uniform common time base for local, global, and external time measurements. In the last section, the functions of a VLSI clock synchronization unit, which improves the synchronization accuracy and reduces the CPU load, are described. With this unit, the CPU overhead and the network traffic for clock synchronization in state-of-the-art distributed real-time systems can be reduced to less than 1 percent.

Optimal clock synchronization

Abstract: We present a simple, efficient, and unified solution to the problems of synchronizing, initializing, and integrating clocks for systems with different types of failures: crash, omission, and arbitrary failures with and without message authentication. This is the first known solution that achieves optimal accuracy—the accuracy of synchronized clocks (with respect to real time) is as good as that specified for the underlying hardware clocks. The solution is also optimal with respect to the number of faulty processes that can be tolerated to achieve this accuracy.

Understanding Protocols for Byzantine Clock Synchronization

Abstract: All published fault-tolerant clock synchronization protocols are shown to result from refining a single paradigm. This allows the different clock synchronization protocols to be compared and permits presentation of a single correctness analysis that holds for all. The paradigm is based on a reliable time source that periodically causes events; detection of such an event causes a processor to reset its clock. In a distributed system, the reliable time source can be approximated by combining the values of processor clocks using a generalization of a ``fault-tolerant average'''', called a convergence function. The performance of a clock synchronization protocol based on our paradigm can be quantified in terms of the two parameters that characterize the behavior of the convergence function used: accuracy and precision.

Virtual Time CSMA Protocols for Hard Real-Time Communication

Abstract: We study virtual time CSMA protocols for hard real time communication systems, i, e., systems where messages have explicit deadlines. In this class of CSMA protocols, each node maintains two clocks; a real time clock and a virtual time clock. Whenever a node finds the channel to be idle, it resets its virtual clock. The virtual clock then runs at a higher rate than the real clock. A node transmits a waiting message when the time on the virtual clock is equal to some parameter of the message. Using different message parameters in conjunction with the virtual clock, different transmission policies can be implemented. In particular, use of message arrival time, message length, message laxity, and message deadline implements FCFS, Minimum-Length-First, Minimum-Laxity-First, and Minimum-Deadline-First transmission policies, respectively.

A synchronization service for a distributed operating system or the like

Abstract: A synchronization service which can be incorporated into a distributed operating system as a shared service. It allows the realization of different custom-built synchronization strategies for different applications. This approach is based on defining a general set of application-independent synchronization primitives. These are provided by the distributed operating system in the form of a synchronization service. By themselves the individual primities are insuffient to provide synchronization. However, they can be combined in different ways to realize customized synchronization strategies. This leaves the ultimate responsibility for synchronization with the application, but in a much simplified form. Application programs can combine these primitives to construct the most suitable form of synchronization.

Loosely coupled distributed computer system with node synchronization for precision in real time applications

Abstract: A loosely coupled distributed computer system provided with node synchronization for precision in real time applications includes a number of loosely coupled node computers. Each computer includes a local real time clock, I/O subsystems, and a communication unit. The computers are connected to each other by a transmission medium for serial communication. Each computer contains a synchronization unit for synchronization of the local real time clocks in each of the computer nodes with the real time clocks of other nodes. Each synchronization unit is connected with a digital output line of its associated local real time clock for supply of unsynchronized time signals from the digital output line to a digital input of the synchronization unit. The latter also has a digital output supplying global synchronized time signals to digital inputs of other I/O subsystems and is operatively connected with the communication unit for obtaining therefrom information as to the point of time of sending a message. The synchronization unit generates global synchronized time signals on its digital output line as a function of the time of an information from a sender and the arrival time information of other computer systems.

Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults

Abstract: Clock synchronization in the presence of malicious faults is one of the main problems associated with the design of a multiprocessor system. Although over the past few years many different algorithms have been proposed for overcoming this problem, they are not suitable for a large real-time multiprocessor system due to their excessive time overhead, asymmetric structure, and/or large number of interconnections. To remedy this problem, we propose a new method in this paper that i) requires little time overhead by using phase-locked clock synchronization, ii) needs a clock network very similar to the processor network, and iii) uses only 20-30 percent of the total number of interconnections required by a fully connected network for almost no loss in the synchronizing capabilities. Both ii) and iii) are made possible by grouping the various clocks in the system into many different clusters and then treating the clusters themselves as single clock units as far as the network is concerned. The method is significant in that regardless of their size multiprocessor systems can be built at an inexpensive cost without sacrificing both the synchronization and fault tolerance capabilities. To show the feasibility of our method, an example hardware implementation is presented. This implementation turns out to be much simpler than the other existing methods and also retains the symmetry and synchronizing capabilities of the network.

A method and a system for synchronizing clocks in a bus type local network

Abstract: The invention relates to a method of synchronizing clocks contained in a local network of bus type, such as Ethernet and a system of synchronizing clocks. In local networks of this kind a number of nodes (1-3) are connected to a common data channel (4). The object of the invention is to obtain a method and a system of synchronizing the clocks which is more accurate than previous methods and systems, in which the synchronizing information is transmitted as common data packages in which the receiver of the synchronizing information does not know the instant of the data package generation. According to the invention a synchronizing message is transmitted from one node which has been chosen to be the master to all nodes, the master node inclusive. When receiving a synchronizing message the nodes read the clock state. Then the master node transmits a clock time message containing the master node clock state when it received the synchronizing message. The clock state indicated by the received clock time message is compared in the slave nodes with the clock states which have been read in the slave nodes. The clock states of the read clocks are compared with the received master clock state and the clock stats of the slave nodes are corrected in dependence on the outcome of the comparison. The clock synchronizing according to the above is suitable for, e.g., military applications.

The Accuracy of the Clock Synchronization Achieved by TEMPO in

Abstract: This paper discusses the upper and lower bounds on the accuracy of the time synchronization achieved by the algorithms implemented in TEMPO, a distributed clock synchronizer running on Berkeley UNIX 4.3BSD systems. We show that the accuracy is a function of the network transmission latency, and depends linearly upon the drift rate of the clocks and the interval between synchronizations. Comparisons with other clock synchronization algorithms reveals that This paper discusses the upper and lower bounds on the accuracy of the time synchronization achieved by the algorithms implemented in TEMPO, a distributed clock synchronizer running on Berkeley UNIX 4.3BSD systems. We show that the accuracy is a function of the network transmission latency, and depends linearly upon the drift rate of the clocks and the interval between synchronizations. Comparisons with other clock synchronization algorithms reveals that TEMPO may achieve better synchronization accuracy at a lower cost.

Hierarchic synchronization method and circuit arrangement for exchanges of a mesh telecommunication network

Abstract: In a mesh telecommunication network in which a hierarchic synchronization method is used for synchronizing the clock pulses of exchanges in such network, a class identification is assigned to the clock pulses of each echange corresponding to a hierarchical order of all the exchanges in the network. To maintain synchronization regardless of changes in the network configuration or failure of interconnecting lines, a synchronization identification is additionally assigned to each exchange. Each exchange transmits its class and synchronization identifications to the exchanges connected thereto, and all the identification received at any exchange are compared to determine the exchange connected thereto having the highest class identification and the highest synchronization identification in such class. The sychronizing clock pulses of such highest order exchange are then used for synchronization. Each exchange may also add to its identifications a mark to distinguish different operating conditions of the network. The reception at each exchange of the class and synchronization identifications transmitted by exchanges connected thereto is effected within presettable time intervals.

TDM transmission system

Abstract: A time division multiplex transmission system includes: a time division multiplex encoder for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect clock synchronization and generating a time-divisionally multiplexed data signal based on a data word not D/A converted and sampled from each digital signal source; a transmission line for transmitting the multiplexed data signal from the time division multiplex encoder; and a time division demultiplex decoder for selecting a desired transmitted, multiplexed data signal and demultiplexing the selected data signal in accordance with a transmission rate before the time division multiplexing.

Introduction to the Special Issue on Real-Time Systems

Abstract: A high-level real-time programming system called RNet is proposed. The main goal of RNet is to develop and use programing concepts and tools for modeling the behavior of real-time tasks, measuring the real-time characteristics of system resources, validating the specifications, and so on. Part of RNet has already been implemented and the remaining parts are currently under development. It is shown that use of a common time base in distributed systems can simplify various design problems, e.g., process communications and checkpointing. The design simplification in turn reduces time overhead associated with the usual design algorithms, thus making them suitable for real-time applications. Upper bounds on the achievable synchronization accuracy and the functions of a VLSI clock synchronization unit to improve the synchronization accuracy and reduce the CPU load.

Clock synchronization system

Abstract: An apparatus and method of synchronizing data systems having different clock frequencies at a particular address. A first device receives first and second parallel data and outputs first serial data at a first particular clock frequency. A second device outputs second parallel data at a second particular clock frequency that is a submultiple at an integer "n" of the first particular clock frequency. The second parallel data is outputted in groups of "n" pieces of data. The address is combined with the integer "n" until the combination passes through a particular numerical value. This produces a first signal representative of the combination passing through the particular numerical value and a second signal representing an offset position less than "n" relative to the first serial data. The first and second signals control second parallel data to initiate the outputting of the second parallel data in accordance with the first signal and to offset the outputted second parallel data in accordance with the second signal. The offset second parallel data may then be merged with the first serial data beginning at the proper address.

Resynchronization of serial data blocks

Abstract: A method and apparatus for re-synchronization of serial data blocks (13,17) utilizing recorded re-synchronizing signals (15a,15b,...,19a,19b,....) separating sub-blocks (13a,­13b,...,17a,17b,....) of data is provided. Use of the re-­synchronization signals (15a,15b,...,19a,19b,....) in combination with error correction codes allows the recovery of data lost due to a signal drop-out even when clock synchronization is also lost. The optimum re-synchronization mark comprises a unique key (40) having a header (44) of two b bits preceding the key and a trailer (42) of b bits appended to the key where b is the maximum correctable number of bits slipped that the clock can be out of synchronization with the beginning of a data sub-block.

Present and Future of Synchronization in the US Telephone Network

Abstract: The need for phase (timing) control in a digital network is described. Because of unknown and unstable path delays, phase con- trol is done on a local basis, whereas only frequency control is feasible on a global basis. The means to provide frequency control is potentially built into the network as a hierarchical masterislave system. The char- acteristics of the four levels of quality of the frequency sources (clocks) in this system are described. Each clock must be phase-locked to a clock of equal or better quality (e.g., S-3 locked to S-2). The pull-in range of the phase-lock loop associated with a clock must allow for inaccuracies of the clock to which it locks-even under startup condi- tions. The pull-in range for an S-3 clock expressed on a fractional fre- quency basis is about 9 X The importance of this number is placed in perspective by realizing two things: 1) the goal for frequency accu- racy of a signal controlling an S-3 clock is a minimum of 3.5 X 2) it is the current intention to equip about 98 percent of the 10 000 digital switches with S-3 clocks. This means that almost all S-3 clocks will be directly connected to an S-3, not an S-2, clock. Furthermore, many other types of equipment, such as digital cross connects and dig- ital channel banks (based on S-3 or S-4 clocks), will intentionally or inadvertently become sources of timing signals. The magnitude of the potential problem therefore becomes apparent. Experience in the field indicates that the number of instances of synchronization problems to- day is troublesomely large. The three major causes of these problems- equipment and line failures, design errors, and operational errors- are discussed. Means of limiting these problems, including the greater use of high-quality equipment and better system monitoring, are also discussed.

Communication System Design using M'ary Full and Partial Response Continuous Phase Modulation

Abstract: Continuous Phase Modulation (CPM), a constant envelope digital signaling technique, provides power efficient and/or bandwidth efficient performance Practical signal designs are selected by applying a trade-off between error probability performance and receiver complexity for a given occupied bandwidth An overall system architecture is presented incorporating the maximum likelihood sequence estimation demodulator coupled with phase and clock synchronization The size and cost of a digital receiver implementation is affected by the sampling rate and number of quantization levels When applied to CPM waveforms, these implementation parameters lead to reasonable design values with minimal performance degradation Finally, a hardware architecture is suggested for data rates on the order of megabits per second

Fault-Tolerant Distributed Real-Time System: MARS

Abstract: MARS (MAintainable Real Time System) is designed from point of view of fault-tolerance and real-time. It is built of self-checking components running in active redundancy. To gain a very high self-checking coverage special error-detection mechanisms are used at the level of the operating system kernel. Error-detection is performed in both, the value and the time domain. A fault-tolerant global time-base is provided cooperatively by the kernel and the clock synchronization unit. Error-detection in the time domain and the design to handle peak load on the components deterministically, require an exact analysis of the time behavior and the communication structure of the tasks executed. Minimum and maximum frequencies for receiving and sending messages have to be specified. All messages are sent with a validity time to prevent the use of outdated information. Error-propagation is limited by reducing the interaction between components.

Real time clocks versus virtual clocks

Abstract: Symmetric distributed termination algorithms are systematically developed. Solution are first presented in an abstract setting of Dijkstra, Feijen and Van Gasteren [DFG] and then gradually transformed into solutions to the distributed termination problem of Francez [F]. The initially used global real time clock is eventually replaced by local virtual clocks. A dependence between the degree of clock synchronization and the efficiency of the solutions is indicated.

Fault-Tolerant Clock Synchronization Validation Methodology

Abstract: A validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight-crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating the clock synchronization system of the Software Implemented Fault Tolerance computer. The design proof of the algorithm includes a theorem that defines the maximum skew between any two nonfaulty clocks in the system in terms of specific system parameters. Most of these parameters are deterministic. One crucial parameter is the upper bound on the clock read error, which is stochastic. The probability that this upper bound is exceeded is calculated from data obtained by the measurement of system parameters. This probability is then included in a detailed reliability analysis of the system.

High reliability system for network system

Abstract: PURPOSE:To prevent out-of-synchronism when plural clock sources exist by supplying a general common clock usually and supplying a private station clock when the clock is at fault, to the interface of respective lines. CONSTITUTION:Usually, one side of clocks 117 and 118 extracted from receiving data 106 and 111 by clock extracting devices 33 and 43 in NTT interfaces 31 and 41 is selected as a master clock 119 with a clock selecting part 52 in a clock deciding device 5. The clock 119 is supplied through PLLs 25, 35 and 45 to transmitting receiving LSI 22, 32 and 42, and transmitting data 102, 107 and 112 are transmitted by using the clock. On the other hand, when the losing of the clocks 117 and 118 is detected by a clock deciding part 53, a main/sub- switching part 6 is switched, and a clock 116 extracted from receiving data 101 with a clock extracting device 23 in a private station interface 21 is selected as the master clock 119 by a selecting part 52.

A virtual time CSMA protocols for hard real-time communication

Abstract: We study virtual time CSMA protocols for hard real time communication systems where messages have explicit deadlines. In this protocol, each node maintains two clocks; a real time clock and a virtual time clock. Whenever a node finds the channel to be idle, it resets its virtual clock to be equal to the real clock. The virtual clock then runs at a higher rate than the real clock. A node transmits a waiting message when the time on the virtual clock is equal to the latest time to send the message. This protocol implements the minimum-laxity-first transmission policy. We compare the performance of our protocol with two baseline protocols both of which transmit messages according to the minimum-laxity-first policy. While both use perfect state information about the nodes and channel, the first is an idealized protocol which obtains this information without paying any cost and the second one pays a reasonable price for it. The simulation study shows that in most cases, our protocol performs close to the first one and better than the second one.

Clock synchronization system

Abstract: This invention relates to a clock synchronization system capable of recording data and the time of initiation of data which is transferred from one location to another.

Self-stabilization of fault-tolerant clock synchronization

Abstract: A study of the self-stabilization of fault-tolerant clock synchronization algorithms is carried out for distributed fault-tolerant system designs. A distributed system with any desired degree of fault-tolerance can be implemented if fault-tolerant clock synchronization is assumed. A self-stabilizing fault-tolerant clock synchronization design proposed in this dissertation can not only periodically resynchronize all the correct clocks but also maintain the required number of correct clocks in the system. This design appears to be the first design with both synchronization and detection functions. A general design approach for a self-stabilizing fault-tolerant clock synchronization algorithm is presented. The approach is based on a statistical testing method and a self-diagnosis technique. The major advantages of the approach are better self-stability control in the design-analysis cycle and lower overhead in achieving self-stabilization. Two self-stability evaluation methods are also discussed. The first method involves differential equations. It can provide an exact self-stability measurement for a fault-tolerant clock synchronization design which satisfies certain sets of system conditions. The second method is a new application of stochastic Petri nets, and can be applied in the self-stability estimation of a more general class of distributed fault-tolerant system designs.

Ais signal detection circuit

Abstract: PURPOSE:To preclude the possibility of mis-information of the detection of an AIS signal even when a circuit detecting the uniformity of an input data string by adding the speciality of a spectrum of the AIS signal to the condition so as to apply detection in detecting the AIS signal. CONSTITUTION:A clock synchronization detection means 101 detects that a circuit extracting a clock from an input bipolar signal is synchronized and operated normally and generates an output, and a uniformity detection means 102 detects that a data string obtained by identifying an input bipolar signal is all '1' or all '0' and generates an output. A spectrum detection means 103 detects that no f0/4 (f0 is a clock frequency) components exists from the spectrum of the input bipolar signal and generates an output. Then an AND means 104 ANDs outputs of the clock synchronization detection means 101, the uniformity detection means 102 and the spectrum detection means 103 and generates an output.

Master/slave type flip-flop circuit

Abstract: PURPOSE:To obtain a master/slave type flip-flop provide with a clock synchronization reset without adding an external circuit, by inserting and connecting a transfer gate to an input side of an inverter, and connecting a control signal of the transfer gate to a control signal of a transfer gate being in an output side of the inverter. CONSTITUTION:When a two-input NOR gate 19 and a transfer gate 20 are inserted and connected, a master/slave type flip-flop provided with a clock synchronization reset is obtained. An R-S flip-flop is constituted of an inverter 16 and the two-input NOR gate 19, and since a control signal of the transfer gate 20 is the same clock signal CK as a control signal of a transfer gate 13, an input reset signal R is held in said R-S flip-flop until an input data D is read. Accordingly, a pulse width of the reset signal R comes to have no relation to a pulse width of the clock signal CK, therefore, the sensitive capacity of a reset operation is improved.