Showing papers on "Clock synchronization published in 1989"

Probabilistic clock synchronization

Abstract: A probabilistic method is proposed for reading remote clocks in distributed systems subject to unbounded random communication delays. The method can achieve clock synchronization precisions superior to those attainable by previously published clock synchronization algorithms. Its use is illustrated by presenting a time service which maintains externally (and hence, internally) synchronized clocks in the presence of process, communication and clock failures.

Time Warp on a Shared Memory Multiprocessor.

Abstract: : A variation of the Time Warp parallel discrete event simulation mechanism is presented that is optimized for execution on a shared memory multiprocessor. In particular, the direct cancellation mechanism is proposed that eliminates the need for anti-messages and provides an efficient mechanism for canceling erroneous computations. The mechanism thereby eliminates many of the overheads associated with conventional, message-based implementations of Time Warp. More importantly, this mechanism effects rapid repairs of the parallel computation when an error is discovered. Initial performance measurements of an implementation of the mechanism executing on a BBN Butterfly multiprocessor are presented. These measurements indicate that the mechanism achieves good performance, particularly for many workloads where conservative clock synchronization algorithms perform poorly. Speedups as high as 56.8 using 64 processors were obtained. However, our studies also indicate that state saving overheads represent a significant stumbling block for many parallel simulations using Time Warp.

The accuracy of the clock synchronization achieved by TEMPO in Berkeley UNIX 4.3BSD

Abstract: The authors discuss the upper and lower bounds on the accuracy of the time synchronization achieved by the algorithm implemented in TEMPO, the distributed service that synchronizes the clocks of the University of California, Berkeley, UNIX 4.3BSD systems. The accuracy is shown to be a function of the network transmission latency; it depends linearly upon the drift rate of the clocks and the interval between synchronizations. TEMPO keeps the clocks of the VAX computers in a local area network synchronized with an accuracy comparable to the resolution of single-machine clocks. Comparison with other clock synchronization algorithms shows that TEMPO, in an environment with no Byzantine faults, can achieve better synchronization at a lower cost. >

Method and apparatus for clock distribution and for distributed clock synchronization

Abstract: A method and apparatus of phase synchronizing a plurality of spatially distributed application modules having synchronizing clocks requiring synchronization, each application module being connected, at a predetermined site nearest the module, to an outgoing path and, at a corresponding site nearest the module, a return path of a pulse reference path, the method comprising the steps of injecting reference pulses at a predetermined frequency into an injection site of the reference path such that the pulses travel along the outgoing path to a remote site and return to the injection site along the return path; determining, for each application module, the time interval for each pulse to travel from the predetermined site to the corresponding site associated with the application module; monitoring, for each application module, the elapsed time interval for each pulse to travel between the predetermined and corresponding sites associated with the application module; producing, for each application module, a local phase reference signal when the elapsed time interval is one-half a last determined one of the time intervals; and synchronizing the clock of each application module with the local phase reference signal.

Synchronized fault tolerant clocks for multiprocessor systems

Abstract: A system for providing fault-tolerant synchronized operation of the Time of Day (TOD) clocks of the respective data processors in a multiprocessor complex. Basically, the system is comprised of a duplex implementation having redundant TOD clock sources, and a plurality of TOD slaves which provide the TOD clocks in the associated processors. A register/counter in each TOD clock source is incremented by a high frequency signal to achieve the required TOD value resolution, and the latter signal is divided down to provide a lower reference frequency signal for synchronization of the clock sources. Each TOD slave includes means for receiving a pair of reference frequency signals and for trouble-free switching between the signals, as required. Alternately, a quad implementation of clock sources which is substantially free of single points of failure of the synchronization mechanism is described. Frequency steering of the clock sources provides increased accuracy and conformity to real time when desired.

An all digital receiver architecture for bandwidth efficient transmission at high data rates

Abstract: Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions. >

A probabilistic approach to distributed clock synchronization

Abstract: A probabilistic method is proposed for reading remote clocks in distributed systems subject to unbounded random communication delays. The method can achieve clock synchronization precisions superior to those attainable by previously published clock synchronization algorithms. The method can be used to improve the precision of both internal and external synchronization algorithms. The approach is probabilistic because it does not guarantee that a processor can always read a remote clock with an a priori specified precision; however, by retrying a sufficient number of times, a process can read the clock of another process with a given precision with a probability as close to one as desired. An important characteristic of the method is that, when a process succeeds in reading a remote clock, it knows the actual reading precision achieved. The use of the remote clock reading methods is illustrated by presenting a time service which maintains externally (and, hence, internally) synchronized clocks in the presence of process, communication, and clock failures. >

Enhanced data formats and machine operations for enabling error correction

Abstract: A record medium, such as a magnetic tape, optical disk, magnetic disk, and the like stores data signals and error redundancy signals Resynchronization signals are interleaved between the recorded signals such that the error redundancy signals are usable to correct signals recorded between such interposed resynchronization signals wherein no error redundancy signals are recorded Error pointing redundancy signals are recorded between all of the resynchronization signals for pointing to signals in error for enhancing the error correction Such error pointing signals can be cyclic redundancy check (CRC) signals Controls for taking advantage of the above-described arrangement are also described Reframing and clock synchronization controls are also disclosed

Bit synchronization circuit

Abstract: A telephone exchange system has a plurality of bit synchronization circuit each provided for an individual subscriber's line A single clock generating circuit which generates a plurality of clocks is provided in common to the plurality of bit synchronization circuits The bit synchronization circuit selects one clock of a phase suitable for regenerating an input data signal among the plurality of clocks applied thereto by the clock generating circuit, and regenerates and phases the input data signal by using the selected clock

AT&T's new approach to the synchronization of telecommunication networks

Abstract: A description is given of AT&T's nationwide synchronization network along with a tutorial on the importance of and need of synchronization. The primary reference clock (PRC) is described along with its verification methodology, capabilities, and performance. The clock and transmission models are discussed along with methods of specifying and testing clock performance. Planning tools and methodology for the synchronization of private digital networks are presented. An expert system that uses the clock models to prepare the optimum performance synchronization plan for a private network is introduced. >

Network synchronization system

Abstract: A network synchronization system for synchronizing a master clock in a distributed communication system composed of a plurality of communication devices interconnected by one or more transmission lines, with a reference clock supplied from outside. A phase difference obtaining circuit for obtaining a phase difference between the reference clock and a master clock in the distributed communication system, is provided in a first communication device of the plurality of communication devices, and the phase difference is transmitted from the first communication device to a second communication device through the transmission line. The second communication device comprises a controlled oscillator circuit for receiving the phase difference, and outputting a master clock having a phase which is controlled according to the output of the phase difference obtaining circuit, so that the phase of the master clock is synchronized with the phase of the reference clock.

Formal Verification of a Fault Tolerant Clock Synchronization Algorithm

Abstract: A formal specification and mechanically assisted verification of the interactive convergence clock synchronization algorithm of Lamport and Melliar-Smith is described Several technical flaws in the analysis given by Lamport and Melliar-Smith were discovered, even though their presentation is unusally precise and detailed It seems that these flaws were not detected by informal peer scrutiny The flaws are discussed and a revised presentation of the analysis is given that not only corrects the flaws but is also more precise and easier to follow Some of the corrections to the flaws require slight modifications to the original assumptions underlying the algorithm and to the constraints on its parameters, and thus change the external specifications of the algorithm

A clock distribution scheme for nonsymmetric VLSI circuits

Abstract: The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit. The scheme uses the hierarchy created by the clock buffers to parallelize the distribution of the clock signal. At each hierarchical level, an exhaustive search of paths with intelligent pruning is used to determine the optimal layout of clock lines at that level. Unlike other related work in this area, both delay and skew are taken into account in determining the layout. >

Clock synchronization in MAFT

Abstract: The steady-state clock synchronization algorithm of MAFT (multicomputer architecture for fault tolerance), an extremely reliable system for real-time applications, is discussed. The synchronization algorithm has been implemented in hardware and a system prototype constructed. The algorithm uses an interactive convergence approach, based on synchronized rounds of message transmission. The authors derive the maximum skew between nonfaulty clocks in terms of basic system parameters. The problem of detecting clock faults is also addressed, with attention to the minimum amount of synchronization error guaranteed to be unambiguously detected. The authors discuss the various practicalities which arise in the implementation of the algorithm as an integrated part of the whole system. Relationships between the synchronization subsystem and the total system are discussed. >

Performance aspects of reference clock distribution for evolving digital networks

Abstract: Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT. >

Building a Global Time on Parallel Machines

Abstract: This paper presents a pragmatic algorithm to build a global time on any distributed system, which is optimal for homogeneous parallel machines. After some discution on time, clocks and distributed systems, we survey and criticize the classical approaches based on clock synchronisation techniques. Satisfying better our purposes, a statistical method is chosen as a building block to derive an original algorithm valid for any topology. This algorithm is particularly well suited for distributed algorithm experimentation purposes because, after an acquisition phasis, it induces neither CPU nor message overhead. We provide in the conclusion some data about its behavior and performances on some parallel machines.

A new probabilistic algorithm for clock synchronization

Abstract: Presented is an averaging probabilistic clock-synchronization algorithm that is based on the redundant transmission of multiple synchronization messages. The algorithm can guarantee a much lower upper bound on the deviation between clocks than can most existing algorithms. The algorithm is probabilistic in the sense that the upper bound on the deviation that it guarantees has an associated probability of invalidity. The probability of invalidity, i.e. the probability that the deviation exceeds the guaranteed maximum deviation, may be made extremely small by sufficiently increasing the number of messages transmitted. It is proved that an upper bound on the probability of invalidity decreases exponentially with the number of messages, i.e. the probability of invalidity itself decreases exponentially or better. >

Synchronization costs on multiprocessors

Abstract: Various types of processor synchronization are introduced and analyzed with regard to execution time and waiting time. It is shown that while barrier synchronization requires a large execution time on systems with many processors, other less restrictive forms of synchronization do not have this drawback. It is also shown that for most reasonable distributions of processor times, a relatively small amount of time is spent waiting at synchronization points. The conclusion is that if barriers can be replaced by the less restrictive synchronization forms, then, for problems with appropriate size granularity, the synchronization costs on most multiprocessors will be small.

Electronic exchange apparatus synchronized with digital network

Abstract: A private branch exchange includes an oscillator for generating a reference clock defining the transmission frequency of a digital network, a clock generating circuit for generating a clock, whose frequency is slightly higher than that of the reference clock, in synchronization with the clock extracted from the digital network, and a selector which monitors whether or not the clock generating circuit is in a state in which it can operate properly, selects the output of the clock generating circuit when it is normal or the output of the oscillator when it is abnormal, and applies the selected output as a drive clock to a time-division switch for performing time-division multiplex transmission while keeping frame synchronization with the digital network. The clock generating circuit comprises an oscillator for generating a clock of a frequency which is slightly higher than that of the reference clock to such an extent as to allow the frame synchronization, and a gate circuit which is enabled in synchronization with the clock extracted from the digital network and disabled upon completion of the exchange of one-frame-signal to provide the output of the oscillator to the selector as a drive clock.

Device to operate absolute time clocks in a process control system comprising a central clock and participants

Abstract: The subject-matter of the invention is a device for operating real-time clocks which are located in participants (2, 3) of a process control system hierarchically connected by bus systems. The real time is prescribed by a central clock and transmitted to the individual participants (2, 3) and synchronised via the available bus systems.

Implementation and measurements of efficient communication facilities for distributed database systems

Abstract: Experimentation with several methods of providing efficient communication facilities for distributed database systems is described. These studies give insight into the delays incurred by applications running on distributed systems. Five different mechanisms for local interprocess communications (two variations with message queues, named pipes, shared memory, and UDP sockets) have been implemented, compared, and analyzed. The most efficient of these is three times as fast as UDP for 1000-byte messages. Kernel-level software multicast and hardware multicast have also been implemented and their performance analyzed. The results show the significant advantage of using these techniques instead of using multiple sends and receives at the user level. The design of a facility that allows the dynamic addition of user-level protocols such as two-phase commit, clock synchronization, etc. to an operating system kernel is presented. The facility is based on a simple stack-based language that provides the functionality and security required. >

Design of fault-tolerant clocks with realistic failure assumptions

Abstract: The authors address the problem of designing fault-tolerant, phase-locked clocks in the presence of different types of clock failures and show that significant improvements in hardware complexity and reliability can be achieved when failed clock modules are partitioned into two classes: malicious and nonmalicious. They show that the condition N>2t+max(t1, 1) is necessary and sufficient to tolerate up to t failed clock modules out of which a maximum of t1 can behave maliciously. The practical value of this design concept is demonstrated by examples. >

Clock synchronizing system in packet transmission and packet transmitter and packet receiver

Abstract: PURPOSE: To simply constitute the circuit and to stably establish clock synchronization between the transmitter and the receiver by controlling the frequency of a clock of the receiver so that each relative frequency of the transmitter and receiver clocks with respect to a clock (ATM clock) of a packet transmission network is coincident. CONSTITUTION: In order to make a sender oscillating frequency ω 1 and a receiver oscillating frequency ω 3 coincident, relative frequencies ωi, ωo with respect to a reference oscillating frequency ω 2 available for the both (equivalent to ATM clock) are obtained. Then the frequencies are compared to control the receiver oscillating frequency ω 3 . Thus, in the case of packet transmission for a television signal or an audio signal, the clock synchronization between the transmitter and the receiver is established without use of an expensive equipment but having a problem in the quality of the information signal or use of a phase locked loop difficult of realization in the performance and without being affected by fluctuation of the packet arrival time. COPYRIGHT: (C)1991,JPO&Japio

Efficient fault tolerant broadcasting algorithm for the cube-connected cycles network

Abstract: The cube-connected cycles network is discussed as a cube whose 2k vertices are cycles of k nodes each. It is suitable for realization for VLSI since it satisfies the properties of degree boundedness of nodes (=3). Broadcasting is a procedure by which a processor can pass a message to all other processors in the network nonredundantly. This is extremely important for diagnosis of the network, distribution agreement or clock synchronization. A simple yet efficient algorithm is developed for broadcasting in the cube-connected cycles network. Another broadcasting algorithm for the cube-connected cycles network in the presence of some faulty processors is also developed. >

Calculation of clock path delay and skew in VLSI synchronous systems

Abstract: In this paper different clock distribution structures in a synchronous VLSI system are investigated and a new structure is proposed. Then a statistical approach is employed to estimate the variations of the clock path delay due to technological variations. The impact of scaling on clock path delay and its variations is also demonstrated. >

Generating a fault tolerant global clock in a high speed distributed system

Abstract: A technique is described for constructing a fault-tolerant global clock in a point-to-point distributed system with an arbitrary topology, which constitutes a wide-area network. It is assumed that the network is constructed of optical links with very high transmission rates. The approach used is to generate a global clock from the ensemble of the local transmission clocks, and not to synchronize these high-speed clocks directly. The steady-state algorithm which generates the global system clock is executed in hardware by the network interface of each node. As a result, it is possible to estimate accurately intermodal delays and thereby to achieve a much tighter synchronization than with other methods. The basic synchronization time step is proportional to the error or uncertainty in the measurement of the end-to-end network delay rather than to the actual value of the end-to-end network delay. Node and network models are presented, and the synchronization condition is defined. The synchronization algorithm, its bound, and its correctness proof are presented. A procedure is described for detecting and isolating a faulty component, while maintaining the integrity of the global clock. >

A design approach for self-diagnosis of fault-tolerant clock synchronization

Abstract: A general design approach for self-diagnosis of faulty clocking modules in a fault-tolerant clock synchronization (FTCS) system is presented. The approach is based on a statistical testing method. The major advantages are better self-stability control and lower overhead. The design methodology includes a self-diagnosis algorithm to transform a partially self-stabilizing clocking system into a self-stabilizing one. Compound to partially self-stabilizing clocking systems, this approach offers several advantages. First, the self-stabilization of the FTCS system is achieved with the support of repair techniques. Second, the system availability for performing synchronization and coordinated actions is controlled by the designer. Third, the transformation overhead is kept to a minimum. Finally, the approach is not limited to the situation in which single clock failure occurs between successive diagnoses. >

Timing extraction system and communication system utilizing same

Abstract: PURPOSE: To apply a system for high speed transmission by discriminating only a cross timing coincident with the identification point of a multivalue signal, outputting the clock of a baud rate synchronously with the cross timing and identifying the data from the multivalue signal with the clock. CONSTITUTION: Zero cross timings of (N-1) kinds are detected from an N-value signal by a zero cross detection section 2. A PLL 3 generates the clock of (N-1)-fold a baud rate to be synchronously with all zero cross points. Moreover, a frequency divider 4 generates (N-1)-fold baud rate clocks different from the phases from the (N-1)-fold clock. Then a discrimination section 5 uses the output data of an identification device 02 to select one of baud rate clocks. Thus, when a multivalue transmission code is applied, the correct clock is extracted and the system is applied to the high speed transmission of several mega-bit per second or above. COPYRIGHT: (C)1991,JPO&Japio