Showing papers on "Clock synchronization published in 1990"

Clock skew optimization

Abstract: Improving the performance of a synchronous digital system by adjusting the path delays of the clock signal from the central clock source to individual flip-flops is investigated. Using a model to detect clocking hazards, two linear programs are investigated: (1) minimizing the clock period, while avoiding clock hazards, and (2) for a given period, maximizing the minimum safety margin against clock hazard. These programs are solved for a simple example, and circuit simulation is used to contrast the operation of a resulting circuit with the conventionally clocked version. The method is extended to account for clock skew caused by relative variations in the drive capabilities of N-channel versus P-channel transistors in CMOS. >

Fault-tolerant clock synchronization in distributed systems

Abstract: Existing fault-tolerant clock synchronization algorithms are compared and contrasted. These include the following: software synchronization algorithms, such as convergence-averaging, convergence-nonaveraging, and consistency algorithms, as well as probabilistic synchronization; hardware synchronization algorithms; and hybrid synchronization. The worst-case clock skews guaranteed by representative algorithms are compared, along with other important aspects such as time, message, and cost overhead imposed by the algorithms. More recent developments such as hardware-assisted software synchronization and algorithms for synchronizing large, partially connected distributed systems are especially emphasized. >

Multiprocessor system having synchronization control mechanism

Abstract: A synchronization controller is provided for each processor in a multiprocessor system. The synchronization controllers are commonly connected to a synchronization signal bus. Each of the synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor, signal means for transmitting a synchronization wait signal to the synchronization signal bus, a synchronization register for specifying the other processors to be synchronized with the corresponding processor, a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization resister, and a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of comparison by the comparator means.

Cost-sensitive analysis of communication protocols

Abstract: : This paper introduces the notion of cost-sensitive communication complexity and exemplifies it on the following basic communication problems: computing a global function, network synchronization, clock synchronization, controlling protocols' worst-case execution, connected components, spanning tree, etc., constructing a minimum spanning tree, constructing a shortest path tree. (Author)

Time warp on a shared memory multiprocessor

Abstract: : A variation of the Time Warp parallel discrete event simulation mechanism is presented that is optimized for execution on a shared memory multiprocessor. In particular, the direct cancellation mechanism is proposed that eliminates the need for anti-messages and provides an efficient mechanism for canceling erroneous computations. The mechanism thereby eliminates many of the overheads associated with conventional, message-based implementations of Time Warp. More importantly, this mechanism effects rapid repairs of the parallel computation when an error is discovered. Initial performance measurements of an implementation of the mechanism executing on a BBN Butterfly multiprocessor are presented. These measurements indicate that the mechanism achieves good performance, particularly for many workloads where conservative clock synchronization algorithms perform poorly. Speedups as high as 56.8 using 64 processors were obtained. However, our studies also indicate that state saving overheads represent a significant stumbling block for many parallel simulations using Time Warp.

An overview of clock synchronization

Abstract: A distributed system consists of a set of processors that communicate by message transmission and that do not have access to a central clock. Nonetheless, it is frequently necessary for the processors to obtain some common notion of time, where ~time :~ can mean either an approximation to real time or simply an integer-valued counter. The technique that is used to coordinate the notion of time is known as clock synchronization.

Extended frequency range variable delay locked loop for clock synchronization

Abstract: A Delay Locked Loop For Clock Synchronization is disclosed that solves the problem of aligning a clock signal (V OUT ) with a reference signal (REF) in the shortest time and without instability. The clock signal (V OUT ) is passed through an conventional, variable delay line (20) whose phase delay is controlled by a charge (V CTRL ) on a capacitor (C). The invention employs an improved phase detection system (21) including first and second phase detectors (22), (26) and a first logic gate (28). The reference signal (REF) is delayed at the second phase detector (26). A logic circuit (30) is reset by a pulse (nReset) charging the capacitor (C) to a maximum voltage (V CTRL ). Maximum voltage (V CTRL ) drives the variable delay line (20) to the minimum achievable delay. The reset pulse (nReset) is then removed, and the voltage (V CTRL ) is bled from the capacitor (C), increasing the phase delay between the clock signal (V OUT ) and the reference signal (REF). When the clock signal (V OUT ) has been delayed sufficiently that the first and second phase detectors (22), (26) agree that more phase delay will bring the clock signal (V OUT ) into alignment with the reference signal (REF), the set-reset circuit (32) is set. This enables the complimentary output (nQ) of the first phase detector (22) to regulate the voltage (V CTRL ) on the capacitor (C), adjusting the variable delay line (20) to bring the clock signal (V OUT ) into alignment with the reference signal (REF).

Hardware-assisted software clock synchronization for homogeneous distributed systems

Abstract: A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed scheme is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-cast skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures. >

Digital frequency estimation in burst mode QPSK transmission

Abstract: In burst digital transmission using PSK (phase shift keying) modulation with coherent detection, the recovery of the carrier reference phase and the symbol clock is a key aspect. If all users have a common clock synchronization, symbol timing needs not to be recovered in each burst. A digital processor for carrier recovery without preambles, in the presence of frequency offset, is considered. As an example, a 2 Mb/s QPSK transmission system is considered in which E/sub b//N/sub o/=10 dB, and the burst and estimation interval length L=15. Using the algorithm described and averaging eight successive estimated frequency offsets, in order to eliminate anomalous errors, the BER (bit error rate) degradation is equal to 0.14 dB when Delta f=20 kHz. >

Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals

Abstract: A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides first and second clocks to the clock path of the bus, the second clock having a different frequency than the first clock, and a master circuit and a slave circuit connected to the system bus. The master circuit includes master speed indication circuitry which provides a master speed indicator indicating the operating speed of the master circuit to the master speed indicator path. The slave circuit includes slave speed indication circuitry which provides a slave speed indicator indicating the operating speed of the slave circuit to the slave speed indicator path. The bus controller provides the second clock when the master speed indicator and the slave speed indicator indicate that the master circuit and the slave circuit both may function at the different frequency of the second clock.

Clock acquisition in a spread spectrum system

Abstract: A circuit and method is disclosed for recovering the transmitter clock at a receiver in a direct sequence spread spectrum communication system where a transmitter and receiver run independent clocks of nominally the same frequency. At the receiver, to select the phase of the local clock that yields the strongest signal, a clock recovery circuitry cycles through M phases of the locally generated receiver clock. The cycling is halted and the phase is locked soon as an indication is obtained that a phase is valid. Alternatively, all M phases of the local clock are tested for validity or invalidity, and depending on the resulting pattern of valid and invalid phases, a particular phase is selected for the local clock. A phase is valid or invalid depending on whether there is a second correlation crossing at the expected instant one data bit period after a first correlation crossing.

Concurrent reading and writing of clocks

Abstract: As an exercise in synchronization without mutual exclusion, algorithms are developed to implement both a monotonic and a cyclic multiple-word clock that is updated by one process and read by one or more other processes.

Distributed Function Evaluation in the Presence of Transmission Faults

Abstract: We consider the problems of computing functions and of reaching an agreement in a distributed synchronous network of processors in the presence of dynamic transmission faults. We characterize the maximum number of transmission faults per clock cycle that can be tolerated for the computation of arbitrary or specific functions, with several types of faults. The n processors communicate by sending messages through dedicated communication links. Each processor has a one-way link to each other processor. In each clock cycle, each processor may send one message. The message is received in the same clock cycle by all other processors apart from those to which it travels on faulty communication links. Each link may be faulty at some points in time, and operate correctly at others. In a transmission, a faulty link can either omit a message (a message is sent, but none arrives), corrupt a message (a message arrives that is different from the message that was sent), or add a message (a message arrives, but none was sent). Messages are words over a finite alphabet, varying from single bits to strings of arbitrary length.

Information processing system having microprogram-controlled type arithmetic processing unit with clock synchronization instruction

Abstract: A method of exchanging information in a processing system including the steps of issuing a clock synchronizing instruction from an operating system, holding the clock synchronizing instruction in a communication information holding unit, suppressing the updating of internal state information in a first arithmetic unit in response to the holding signal, outputting a communication demand signal from the communication information holding unit to a system control unit, freezing the updating of the calendar clock values in respective first and second arithmetic processing units, receiving in the system control unit the first clock value from the first arithmetic processing unit, storing the first calendar clock value in the second arithmetic processing unit, issuing a restarting signal to the arithmetic processing units, and issuing a microprogram actuating instruction to the arithmetic processing units from the system control unit.

Servo pattern for location and positioning of information on a disk drive

Abstract: A servo pattern which provides for reference clock synchronization, track following and track crossing, and radial and angular head position information, is described. On each servo track, no two locations have the same pattern, and on each servo track, the pattern read is different from the pattern read on any other servo track. Off-track error signals are derived from the relative read signal amplitudes of adjacent track patterns and reference clock synchronization is derived from the timing of the pulses read. During drive operation, the pattern read from a servo track is compared to an identical pattern generated electronically. Radial and angular position can then be known with certainty when the two patterns match within predetermined bounds. The present invention allows all pulses in the pattern to be used for reference clock synchronization, track following and seeking, and radial and angular position acquisition.

System for synchronizing clocks between communication units by using data from a synchronization message which competes with other messages for transfers over a common communication channel

Abstract: In an arrangement for synchronizing data and other information in a computerized system which comprises a common serial data communication channel (212), two or several collaborating units (201) are arranged connectable to the channel, wherein a respective unit comprises a clock (207). A main clock is included in the system and the clock in one of the units can be used as main clock. The units with associated communication element and communication channel are arranged in such a manner that the time of the main clock can be transferred to the clocks of the other units. The clocks are arranged so that they can operate with a common time base. The units/communication elements comprise hard- and software or hardware which brings about the setting of a respective clock with predetermined accuracy in dependence on the main clock time.

VLSI clocking system using both overlapping and non-overlapping clocks

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge of the other non-overlapping clock rises and an edge which must rise after a clock edge of the other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent race conditions; however, the "dead" time between the falling of one clock edge and the rising of the other clock edge has performance costs. Overlapping clocks are used whenever such race conditions can be avoided, as at the ends of the register pipeline, with the resultant performance improvement. The non-overlapping clock signals are preferably derived from the overlapping clock signals inside each block rather than globally so that it is easier to control the skew between phases of the non-overlapping clock signals. Such use of local non-overlapping clock generators in each block also reduces the amount of capacitive loading on the global overlapping clock network, thereby allowing faster edges and smaller skews on the global overlapping clock which further improves the performance of critical timing paths which use the global overlapping clock.

Method for operating and maintaining a clock of a system

Abstract: A method of operating and maintaining the clock of the system for determining a reference clock of the system when starting an operation and maintenance processor (OMP), comprises the steps of: a first step of requesting and receiving a hardware clock from a network synchronizing processor (NSP); a second step of checking if the received hardware clock does not fall between a predetermined minimum and a predetermined maximum, and if so, providing an alarm message which requires an operator to provide information on a reference clock and if not, requesting reference clocks from all of the processors except an operation and maintenance processor (OMP); and a third step of comparing the hardware clock and the received reference clocks as many times as the number of the received reference clocks, and determining the hardware clock as a reference clock of the system if a difference is less than or equal to a predetermined time for more than the predetermined number of times and if not, providing an alarm message which requires the operator to provide information on a clock as necessary to determine the reference clock of the system.

System timing analysis by self-timing logic and clock paths

Abstract: A system and method of determining the propagation delay between LSSD (Level Sensitive Scan Delay) latch pairs is performed by modifying system and scan clock sequences. A set bit is initially scanned to the input of the sending trigger. This is done by inhibiting the last B clock. These A and B clocks are then gated off and the system clocks operate a complete cycle with the unique sequence of inhibiting the first latch pulse and the last trigger pulse. Finally, a unique scan clock sequence is used to scan out data from the receiving latch. If the data scanned out corresponds with expected data (the set bit), the process is repeated decreasing the cycle time of the system clocks until the set bit is no longer received. The measured delay is then taken as the preceding cycle time. By measuring the delays between a plurality of points and a common originating point and taking the differences in these delays, the skew in a clock distribution system can be readily determined.

Timing extraction method and communication system

Abstract: Clock timing is extracted from N level, multilevel codes of megabits per second data by determining a baud clock among the N-1 possible clocks synchronized to all the level cross points. A discriminator is used with a clock and if correct information is not obtained, the clock is changed.

Clock synchronization algorithm for address independent networks

Abstract: A distributed algorithm for clock synchronization in address independent networks such as token rings and token busses is described. Synchronization is accomplished by using the fastest clock in the network as the master clock against which all other clocks in the network are synchronized. An algorithm is implemented in which each node sends out a message to all the other nodes in the network when its timer times out to tell its time. If a node receives a message with a higher clock time before it has had an opportunity to send out its own message, that node assumes that it is not the fastest node and it will not send out its message. Provision is made for maximum and minimum delays that are expected within a particular network. It has been proven that after a few cycles, all nodes will be synchronized to the node with the fastest clock and that this node will be the only one to transmit its time.

Analysis of self-stabilizing clock synchronization by means of stochastic Petri nets

Abstract: A model for analyzing a FCS (fault-tolerant clock synchronization) system of the type supported by a statistical self-diagnosis is described. Once a self-diagnosis scheme is integrated into an FCS design, the problem of controlling and measuring the system's self-stability arises. A stochastic Petri net (SPN) model is constructed to derive the self-stability measures of such FCS systems. An example is given to demonstrate the entire modeling and analyzing procedure. The mapping from SPN model to Markov model shown in an example can be automated by using an SPN software package. The results show that the SPN model is an excellent tool for obtaining self-stability measures and that several important system features, such as synchronization and parallelism, can be modeled using the SPN method in a much clearer manner than they can be modeled using other available tools. >

Implementation issues in clock synchronization

Abstract: We present some results from an experimental implementation of a recent clock synchronization algorithm. This algorithm was designed to overcome arbitrary processor failures, and to achieve optimal accuracy, i.e., the accuracy of synchronized clocks (with respect to real time) is as good as that specified for the underlying hardware clocks. Our system was implemented on a set of workstations on a local area broad-cast network. Initial results indicate that this algorithm can form the basis of an accurate, reliable, and practical distributed time service.

Switching technique for attaining synchronization

Abstract: Synchronization of a local clock in a transmission system node is achieved by using synchronization circuitry such as a phase-locked loop (PLL). This synchronization circuitry is provided with a selected one of a multiplicity of timing signals derived from incoming bit streams to the node. The selected timing signal is employed by the synchronization circuity as a reference timing signal to which the local clock is synchronized. The timing-signal selection is facilitated by a switch controlled by a process or to relay the timing signal, derived from the most desirable bit stream, to the synchronization circuitry. This processor determines such a bit stream based on various indicators of the signal quality thereof. Moreover, the switch operates at such a speed that the synchronization circuitry is precluded from free-running during any switching period.

Minimizing selective availability error on Topex GPS measurements

Abstract: GPS measurements made at Topex/Poseidon and the accompanying ground tracking sites will be affected by the selective availability. Although in principle the effects may be removed by differencing between receivers observing the same GPS satellites, this requires accurate synchronization of all receiver clocks. In the case of Topex/Poseidon application, there are two sources of imperfect clock synchronization. The first and larger is due to the constantly drifting clock onboard Topex, which may cause a residual effect as large as 10 cm on Topex carrier phase and 1 m on Topex pseudorange. The second is due to light-time differences between receivers observing the same GPS satellites, which may amount to a few mm error. In this paper a data reduction scheme which incorporates a low-order polynomial interpolation and carrier phase smoothing on pseudorange acquired at Topex and ground receivers is described; a simulation analysis is given demonstrating the effectiveness of the scheme for reducing the GPS S/A effects; and comparison with other schemes is discussed.

Atomic Broadcast in a Real-Time Environment

Abstract: This paper presents a model for real-time distributed systems that is intermediate in complexity between the simple, perfectly synchronous model in which there are rounds of communication exchange among processors in a completely connected network and an asynchronous model in which there is no reasonable upper bound on the time required for transmission and processing of messages. In this model algorithms are described for atomic broadcast that can be used to update synchronous replicated storage, a distributed storage that displays the same contents at every correct processor as of any clock time. The algorithms are all based on a simple communication paradigm and differ only in the additional checking required to tolerate different classes of failures.

High stability clock synchronized on an external synchronization signal

Abstract: The synchronized clock receives a plurality of external synchronization signals and includes a servo-control signal generator in association with each of said external synchronization signals. The synchronized clock also includes a control unit which produces the control signal actually applied to a clock generator by selecting a particular one of the servo-control signals on the basis of quality criteria.

Efficient at-most-once messages based on synchronized clocks

Abstract: This paper describes a new message passing protocol that provides guaranteed detection of duplicate messages even when the receiver has no state stored for the sender. It also discusses how to use these messages to implement higher-level primitives such as at-most-once remote procedure calls and sequenced bytestream protocols, and describes an implementation of at-most-once RPCs using our method. Our performance measurements indicate that at-most-once RPCs can be provided at the same cost as less desirable RPCs that do not guarantee at-most-once execution. Our method is based on the assumption that clocks throughout the system are loosely synchronized. Modern clock synchronization protocols provide good bounds on clock skew with high probability; our method depends on the bound for performance but not for correctness.

Interleaved All-to-All Reliable Broadcast on Meshes and Hypercubes.

Abstract: All-to-all (ATA) reliable broadcast is the problem of reliably distributing information from every node to every other node in point-to-point interconnection networks. A good solution to this problem is essential for clock synchronization, distributed agreement, etc. We propose a novel solution in which the reliable broadcasts from individual nodes are interleaved in such a manner that no two packets contend for the same link at any given time-this type of method is particularly suited for systems which use virtual cut-through or wormhole routing for fast communication between nodes. Our solution, called the IHC Algorithm, can be used on a large class of regular interconnection networks including regular meshes and hypercubes. By adjusting a parameter /spl eta/ referred to as the interleaving distance, we can flexibly decrease the link utilization of the IHC algorithm (for normal traffic) at the expense of an increase in the time required for ATA reliable broadcast. We compare the IHC algorithm to several other possible virtual cut-through solutions and a store-and-forward solution. The IHC algorithm with the minimum value of /spl eta/ is shown to be optimal in minimizing the execution time of ATA reliable broadcast when used in a dedicated mode (with no other network traffic). >