Showing papers on "Clock synchronization published in 1991"

Internet time synchronization: the network time protocol

Abstract: The network time protocol (NTP), which is designed to distribute time information in a large, diverse system, is described. It uses a symmetric architecture in which a distributed subnet of time servers operating in a self-organizing, hierarchical configuration synchronizes local clocks within the subnet and to national time standards via wire, radio, or calibrated atomic clock. The servers can also redistribute time information within a network via local routing algorithms and time daemons. The NTP synchronization system, which has been in regular operation in the Internet for the last several years, is described, along with performance data which show that timekeeping accuracy throughout most portions of the Internet can be ordinarily maintained to within a few milliseconds, even in cases of failure or disruption of clocks, time servers, or networks. >

High-performance clock routing based on recursive geometric matching

Abstract: Minimizing clock skew is a very important problem in the design of high performance VLSI systems. We present a general clock routing scheme that achieves extremely small clock skews, while still using a reasonable amount of wire length. This routing solution is based on the construction of a binary tree using recursive geometric mat thing. We show that in the average case the total wire length of the perfect path-balanced tree is within a constant factor of the wire length in an opt imal Steiner tree, and that in the worst case, is bounded by O(@) when the n leaves are arbitrarily distributed in the unit square. we tested our algorithm on numerous random examples and also on industrial benchmark circuits and obtained very promising results: our clock routing yieIds near-zero average clock skew while using similar or even shorter total wire length in comparison with the methods of [7].

HARTS: a distributed real-time architecture

Abstract: The design, implementation, and evaluation of a distributed real-time architecture called HARTS (hexagonal architecture for real-time systems) are discussed, emphasizing its support of time-constrained, fault-tolerant communications and I/O (input/output) requirements. HARTS consists of shared-memory multiprocessor nodes, interconnected by a wrapped hexagonal mesh. This architecture is intended to meet three main requirements of real-time computing: high performance, high reliability, and extensive I/O. The high-level and low-level architecture is described. The evaluation of HARTS, using modeling and simulation with actual parameters derived from its implementation, is reported. Fault-tolerant routing, clock synchronization and the I/O architecture are examined. >

Maintaining digital clocks in step

Abstract: A system of simultaneously triggered clocks is designed to be stabilizing: if the clock values ever differ, the system is guaranteed to converge to a state where all clock values are identical, and are subsequently maintained to be identical. For an N-clock system, the design uses N registers of 2logN bits each and guarantees convergence to identical values within N2 "triggers".

Efficient at-most-once messages based on synchronized clocks

Abstract: This paper describes a new at-most-once message passing protocol that provides guaranteed detection of duplicate messages even when the receiver has no state stored for the sender. It also discusses how to use at-most-once messages to implement higher-level primitives such as at-once-remote procedure calls and sequenced bytestream protocols. Our performance measurements indicate that at-most-once RPCs can provide at the same cost as less desirable forms of RPCs that do not guarantee at-most-once execution. Our method is based on the assumption that clocks throughout the system are loosely synchronized. Modern clock synchronization protocols provide good bounds on clock skew with high probability; our method depends on the bound for performance but not for correctness.

Probabilistic clock synchronization in large distributed systems

Abstract: Synchronization algorithm is proposed which uses one of two probabilistic techniques to estimate remote clock values, and uses an interactive convergence algorithm on the resulting estimates to adjust the local clock. The algorithm does not require master/slave clocks and reduces the number of messages needed. As a result it is suitable for use in large distributed systems. >

Clock synchronization and the power of broadcasting

Abstract: We investigate the power of a broadcast mechanism in a distributed network. We do so by considering the problem of synchronizing clocks in an error-free network, under the assumption that there is no upper bound on message transmission time, but that broadcast messages are guaranteed to be received within an interval of size e, for some fixed constant e. This is intended to be an idealization of what happens in multiple access networks, such as the Ethernet. We then consider tradeoffs between the type and number of broadcasts, and the tightness of synchronization. Our results include (1) matching upper and lower bounds of (1 + 1/K;)e on the precision of clock synchronization attainable for n ≥ 3 process using K (n - 1)-casts, 3 ≥ K ≥ n, (2) matching upper and lower bounds of (1 + 1/n;)e on the precision of clock synchronization attainable for n ≥ 3 processes using an arbitrary number of (n - 1)-casts, and (3) matching upper and lower bounds of (1 + n - 2/n)e on the precision attainable using 2-casting.

Placement for clock period minimization with multiple wave propagation

Abstract: A linear program is used to direct the placement of Standard Cells such that the clock period is minimized. Constraints upon the logic path delays and the clock signal arrival times at the flipflops allow multiple signals, corresponding to several clock cycles, to exist simultaneously on the logic signal paths during operation. The linear program constraints relate the clock period to the maximum and minimum logic path delays. Delays are achieved in the clock and logic paths by the use of delay elements and resistive polysilicon wires in the interconnection network.

Monitoring selective availability dither frequencies and their effect on GPS data

Abstract: The signals transmitted by Block II satellites of the Global Positioning System (GPS) can be degraded to limit the highest accuracy of the system (10 m or better point positioning) to authorized users. This mode of degraded operation is called “Selective Availability” (S/A). S/A involves the degradation in the quality of broadcast orbits and satellite clock dithering. We monitored the dithered satellite oscillator and investigated the effect of this clock dithering on high accuracy relative positioning. The effect was studied over short 3-meter and zero-baselines with two GPS receivers. The equivalent S/A effects for baselines ranging from 0 to >10,000 km can be examined with short test baselines if the receiver clocks are deliberately mis-synchronized by a known and varying amount. Our results show that the maximum effect of satellite clock dithering on GPS double difference phase residuals grows as a function of the clock synchronization error according to: S/A effect =0.04 cm/msec, and it increases as a function of baseline length like: S/A effect =0.014 cm/100 km. These are equations for maximum observed values of post-fit residuals due to S/A. The effect on GPS baselines is likely to be smaller than the 0.14 mm for a baseline separation of 100 km. We therefore conclude, for our limited data set, and for the level of S/A during our tests, that S/A clock dithering has negligible effect on all terrestrial GPS baselines if double difference processing techniques are employed and if the GPS receivers remain synchronized to better than 10 msec. S/A may constitute a problem, however, if accurate point processing is required, or if GPS receivers are not synchronized. We suggest and test two different methods to monitor satellite frequency offsets due to S/A. S/A modulates GPS carrier frequencies in the range of-2 Hz to +2 Hz over time periods of several minutes. The methods used in this paper to measure the satellite clock dither could be applied by the civilian GPS community to continuously monitor S/A clock dithering. The monitored frequencies may aid high accuracy point positioning applications in a postprocessing mode (Malys and Ortiz 1989), and differential GPS with poorly synchronized receivers (Feigl et al. 1991).

Clock synchronization system between sender and receiver in packet network and clock synchronization device

Abstract: PURPOSE:To prevent the effect of fluctuation in a delay in a network in the case of clock synchronization in an asynchronous packet network working on a synchronous network. CONSTITUTION:A transmission data 601 is written in a transmission buffer 603 by using a sender side asynchronous clock 602 and when data by a packet length are stored, a time stamp block 605 expresses a phase of the asynchronous clock 602 of the sender side on the moment in a clock 604 of an asynchronous packet network 608 to obtain a time stamp and a packet generation block 607 generates a packet and sends it. The packet at the receiver side is given to a packet separation block 609, in which the packet is separated into the information part, the time stamp part and the header trailer part, and the data of the information part is written in a reception buffer 601 by using the clock 604, the time stamp part is written in the processing block 611 and the reception clock 613 is corrected based on the time stamp and the clock 604 of the asynchronous packet network to read the data.

Breaking the barrier of parallel simulation of digital systems

Abstract: We show that digital systems contain significantly more parallelism than previously thought. By reducing the dependency on time as the mechanism for synchronization. significant speedups are possible. By using asynchronous control ad Virtual Time synchronization with Lazy Cancellation, limited component sizes, special clock distribution and bounding windows, we get up to 23X speedup on a 32 processor system over a good sequential algorithm for mixed-level simulation.

Mechanical Verification of a Schematic Byzantine Clock Synchronization Algorithm

Abstract: Schneider generalizes a number of protocols for Byzantine fault tolerant clock synchronization and presents a uniform proof for their correctness. The authors present a machine checked proof of this schematic protocol that revises some of the details in Schneider''s original analysis. The verification was carried out with the EHDM system developed at the SRI Computer Science Laboratory. The mechanically checked proofs include the verification that the egocentric mean function used in Lamport and Melliar-Smith''s Interactive Convergence Algorithm satisfies the requirements of Schneider''s protocol.

Method for clocks synchronization for receiving pulse position encoded signals

Abstract: A method for clock synchronization for receiving pulse position encoded signals in which a clock signal defines slots or windows of time in which to receive pulse signals. The signal received within a slot is measured to obtain a value representing the amount of signal received within that slot. The values from adjacent slots are compared to determine into which slot the signal most fully fits, and to determine a clock correction value which would change the phase of the clock to make the slots more accurately center on the received pulses. During a time period in which clock adjustment will not affect received pulses, the clock correction value is applied to the clock. In a preferred form, the measurement of pulses, comparison between slots, and clock correction are all performed digitally. A list of energy values is maintained for all slots within a frame, so that the maximum energy value can be selected for assigning a pulse position to a slot within that frame.

Impulse clock system

Abstract: A clock system of the impulse type consisting of stepper motor driven secondary clocks (16) and a master control (10). Each secondary clock (16) includes a stepper motor (22) directly driving the minute hand (26), an hour hand (28) driven by the minute hand (26), and an emitter (90) and detector (92) on opposite sides of a gear (50) of the movement and coacting with a window (50a) in the gear to determine the absolute position of the clock for comparison to the master control time. At five minutes before 6:00, the sensor, (64) of each secondary clock (16) is activated by a signal from the master control (10) and a series of reset pulses are thereafter transmitted to the secondary clocks (16) with each secondary clock stopping as the window (50a) in its drive train gear (50) moves into alignment with the emitter (90) and detector (92) of its sensor mechanism (64), whereafter all of the remaining clocks are moved to 6:00 by a rapid pulse train.

Frame synchronization dependent type bit synchronization extraction circuit

Abstract: A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment (TE) connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data. To make the timing extraction jitter small and make the bit timing stable, it comprises a counter preset mode synchronization unit (21, 23, 26), a digital phase-lock loop mode synchronization unit (21,22,23,24,25), frame synchronization detection unit (30), and an inhibiting unit (27,28) for inhibiting the operation of the counter preset mode synchronization unit, and the bit synchronization is effected by only the digital phase locked loop mode synchronization unit after the frame synchronization is detected by the frame synchronization detection unit.

Telephone exchange apparatus with communication line clocking

Abstract: In a telephone exchange apparatus which accommodates digital communication liens and employs a slave synchronization system in which a clock is extracted from a signal received from the network, an exchange switch is operated in synchronism with the extracted clock so as to prevent data omission caused by a difference between operating frequencies of a network and an exchange apparatus. If there is a phase difference between a pre-switching clock and a post-switching clock when the extracted clocks are switched upon changing communication lines, the postswitching clock is delayed by the phase difference between the two clocks so as to cause the phase of the post-switching clock to coincide with the phase of the pre-switching clock.

Distributed multiple clock system and a method for the synchronization of a distributed multiple system

Abstract: A method for synchronizing a distributed multiple clock system in which the first clock to reach a first predetermined number of counts generates a polling request signal. The remaining clocks compare the content of their counters to determine if they are in synchronization with the clock that generated the polling request signal. Each clock will place itself inactive if it determines it is out of synchronization with the active clocks. The first active clock to reach a second predetermined number of counts will generate a synchronization interrupt signal which resets a counter in each clock to zero. A start subroutine readmits inactive clocks when after a synchronization interrupt signal is generated its counts are within a predetermined readmittance range or its counter counts up to a third predetermined value.

Modem with time-invariant echo path

Abstract: An ISDN modem. The modem includes an independent clock which controls the modem's input and output filters and two dependent clocks whose rates are functions of the independent clock and which are synchronized with external timing signals. When a dependent clock is synchronized, timing adjustment signals to other components of the modem specify the type and direction of synchronization. One of the dependent clocks and the independent clock are used to control a decimator which provides two samples of a symbol which are one independent clock cycle apart. One of the samples is a primary sample from which the symbol is interpreted and the other is a secondary sample which is used to continually train a jitter canceller. When a clock is synchronized, the secondary sample becomes the primary sample, providing the modem with a time-invariant echo path. On clock synchronization, the jitter canceller responds to the timing adjustment signals by providing adaptation information to the linear echo canceller.

A statistical clock synchronization algorithm for anisotropic networks

Abstract: A method to estimate the value of remote clocks in distributed systems is proposed. The method is able to deal with isotropic and anisotropic networks and includes a way to detect performance failures on single exchanges. It uses a statistical approach to estimate the relative drift of clocks and a round trip clock reading protocol to compute the offset. A good precision can be attained and maintained without exchanging too many specific extra messages. Numerical results obtained from a discrete event simulation are presented. >

Method and apparatus for correctly storing data recorded on a rotational disc-shaped recording medium despite occurrence of clock synchronization disorder

Abstract: This invention is intended for MCAV-based information processing which records and/or reproduces data. A disc-shaped recording medium having a record area formed in a plurality of concentric tracks is rotated at a constant angular velocity, the record area is partitioned into a plurality of zones depending on the radial position, base clock frequencies are assigned to the zones so that an outer zone has a higher clock frequency than an inner zone, and data is recorded and reproduced in each zone in accordance with the base clock of the assigned frequency. In recording and reproducing data, a VFO signal recorded together with the unit block data of recording and reproduction (sector) is reproduced thereby to produce a VFO clock which is synchronous with the reproduced VFO signal by means of a phase lock circuit (VFO), and, in introducing reproduced data which follows the VFO signal into the reproduced data introduction circuit, synchronization disorder (sync-disorder) of the VFO clock is detected. At detection of sync-disorder, reproduced data corresponding to recorded data following the data in the sector with the event of sync-disorder is introduced to the reproduced data introduction circuit in response to the VFO clock which is synchronous with the VFO signal recorded together with the recorded data, despite the sync-disorder.

Time control method in computer networks

Abstract: A method for controlling time in hierarchically constructed computer networks with continuous synchronisation of clock modules, provided at the individual network levels (E1 to E3), to the time of a central main clock (HU) by means of messages, in which method time stamps can be issued by each clock module which, in addition to a clock-time field and a date field exhibit additional information fields relating to the synchronisation source (CLOCKNR), type of synchronisation, synchronisation delay and clock time resolution.

Efficient synchronization of clocks in a distributed system

Abstract: A probabilistic clock synchronization algorithm is proposed where processors in the system exchange time stamps and synchronize to a common clock value. Most of the previous algorithms for this problem have been based on a master-slave approach where all the slave processors synchronize to the clock value of a master. These algorithms are not distributed in nature and some of the assumptions made in these algorithms may become invalid if a large number of slaves try to synchronize with a master. The only distributed algorithm that is available was earlier proposed by A. Olson and K.G. Shin (1991). It is based on finding a cyclic path connecting the processors in the system and exchanging time stamp messages through this path. For the same level of synchronization accuracy, the proposed algorithm uses a much smaller number of messages. >

Optimal clocking of circular pipelines

Abstract: A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described. >

Synchronizing system in digital communication line

Abstract: A synchronizing system in a digital communication line comprises a plurality of local switches for storing at least one digital line and monitoring a first piece of busy information when a clock source is already present, the local switches, if a first new clock source occurs while the first busy information is indicating no busy state, being capable of transmitting a master right request to turn the busy information to the busy state and to specify the first new clock source as a master clock and, on receiving a master right specification with respect to the master right request, being capable of outputting the first new clock source as the master clock; and a master switch connected to the plurality local switches in a star manner, by a link transmission line for transmitting control information including the master clock, master right request and master right specification, for monitoring a second piece of busy information indicating a busy state, the master switch, if a second new clock source occurs while the second busy information is indicating no busy state, being capable of transmitting the second new clock source as a master clock and, if the second new clock source competes with the first new clock source in the local switches that has output the master right request, being capable of arbitrating the competition between the first and second new clock sources and selecting one of the clock sources to turn the busy information to the busy state and, if the first clock source is selected, outputting the master right specification to the local switches that have transmitted the master right request.

Baseband signal processing

Abstract: The baseband signal processing of the ALTAIR wireless in-building network (WIN) is described. The discussion covers the 19-GHz oscillator, burst processing, packet detection, symbol clock synchronization and gain and offset correction. The algorithms described are carried out in a single ASIC composed of 60000 active gates. The implemented procedures allow for parallel processing, which significantly reduces the computation time and therefore leads to preserving high bandwidth efficiency. The learning processes that acquire information about packet parameters and the adjustment operations in the receivers are executed in 3 mu s. >

Frequency and Time Stability of GPS and GLONASS Clocks

Abstract: The frequency stability and reliability of the clocks are critical to the success of the GPS and GLONASS programs. We will show some of the similarities and differences between the clocks involved in these two systems. Because both systems plan to be operational in the next few years, the data leading up to this operational stage is of significant interest. On-board clocks and the stability of the master control clocks for these systems are analysed. We will discuss the attributes of these two systems as time and frequency references. Their relationship to UTC will also be illustrated. More data over a longer period of time was available for the authors from GPS than from GLONASS. Even so it is obvious that both systems have matured. Though the GLONASS system was developed later, its overall clock performance has improved more rapidly. Some of the more recent GLONASS clock performance is at about the same level as that of the GPS clocks. The analysis has yielded some very interesting contrasts, comparisons and changes in these systems that should be of great interest for time and frequency users, as well as for clock vendors and receiver vendors.

Protocols for distributed real-time systems

Abstract: Novel and specialized protocols will be necessary to deal with the requirements of time-constrained communication and synchronized clocks in an important area of technology, viz., the next generation of distributed real-time systems. Our research concentrates on developing distributed system protocols that realize these requirements. In this dissertation, we have proposed, analyzed and evaluated new protocols to meet these requirements. A clock synchronization protocol is used to provide support for a common system-wide time base. We have proposed and analytically evaluated a novel probabilistic algorithm for clock synchronization, that can guarantee a much lower bound on the deviation between clocks than most existing algorithms. The guarantee offered by our algorithm is however probabilistic, i.e., there is non-zero probability that the guarantee offered by our algorithm will fail to hold. The probability of invalidity of the guarantee, i.e., the probability that the deviation exceeds the guaranteed maximum deviation, can however be made extremely small by transmitting a sufficient number of messages. We have presented a detailed analysis of the protocol. Among other things, we considered three different bounds on the probability of invalidity, and showed that a bound on the probability of invalidity decreases exponentially with the number of messages. In our work on time-constrained communication, we have proposed RTLAN, a new local area network architecture for distributed real-time systems. RTLAN incorporates new communication abstractions (real-time virtual circuit, real-time data-gram) and provides new classes of connection-oriented (RTCOS) and connectionless services (RTCLS) that explicitly consider the timing requirements of messages. It employs specialized real-time communication protocols at the medium access control layer to support these services. We have developed, analyzed and evaluated a homogeneous suite of five real-time medium access control protocols based on a uniform window splitting paradigm. Performance evaluation studies by simulation show that these protocols perform well compared to idealized baseline protocols.

Method for transmitting or recording information, information recording and reproducing device and information transmitting device

Abstract: PURPOSE: To reduce the erroneous detection of a synchronous pattern and to improve the reliability of the recording and reproducing or transmission of information by using the combination of a VFO pattern with an excellent correlative characteristic and the synchronous pattern CONSTITUTION: A prescribed pattern for clock synchronization, a synchronizing pattern and 1, 7 RLL code data are read from a medium recording them by a signal detector 4 in a reproducing device After the information is binarized, and is inputted to a phase locked loop PLL circuit 6 and a clock signal is generated and the binarization signal is synchronized with the clock signal by a latch 7 and the synchronous pattern is detected by a synchronous pattern detector 8 Then, the data succeeding to the synchronous pattern is demodulated by a 1,7 code demodulator 9 and regenerative data and a regenerative synchronous clock are outputted Thus, the erroneous detection of the synchronous pattern is reduced by using the combination of the VFO pattern with most excellent correlativity and the synchronous pattern in a 1, 7 code COPYRIGHT: (C)1993,JPO&Japio

Self-synchronizing data queues

Abstract: A system for enabling processor cells in a high speed multi-processor environment to communicate with each other so as to resolve synchronization problems caused by propagation and other delays inherent in such an environment. The invention is for systems for which the data delay is both bounded and fixed wherein the maximum data delay is part of the system specifications and all cells operate at the same frequency. Data is transmitted along with a clock to allow the receiving cell to properly recover the data regardless of the state of the receiver's internal clocks. Both the transmitting cell and the receiving cell are operating at the same frequency (because their clock signals are derived from the same master oscillator), but the range of delays associated with the transmission of data places no bounds on the allowable phase difference between the received data's clock and the receiver's internal clock state.