Showing papers on "Clock synchronization published in 1992"

A security risk of depending on synchronized clocks

Abstract: Many algorithms or protocols, in particular cryptographic protocols such as authentication protocols, use synchronized clocks and depend on them for correctness. This note describes a scenario where a clock synchronization failure renders a protocol vulnerable to an attack even after the faulty clock has been resynchronized. The attack exploits a postdated message by first suppressing it and replaying it later.

Synchronous residual time stamp for timing recovery in a broadband network

Abstract: A Residual Time Stamp (RTS) technique provides a method and apparatus for recovering the timing signal of a constant bit rate input service signal at the destination node of a synchronous ATM telecommunication network. At the source node, a free-running P-bit counter counts cycles in a common network clock. At the end of every RTS period formed by N service clock cycles, the current count of the P-bit counter, defined as the RTS, is transmitted in the ATM adaptation layer. Since the absolute number of network clock cycles likely to fall within an RTS period will fall within a range determined by N, the frequencies of the network and service clocks, and the tolerance of the service clock, P is chosen so that the 2P possible counts, rather than representing the absolute number of network clock cycles an RTS period, provide sufficient information for unambiguously representing the number of network clock cycles within that predetermined range. At the destination node, a pulse signal is derived in which the periods are determined by the number of network clock cycles represented by the received RTSs. This pulse signal is then multiplied in frequency by N to recover the source node service clock.

Flow synchronization protocol

Abstract: High-speed networks still facilitate the advent of multimedia and distributed applications. An adaptive flow synchronization protocol that permits synchronized delivery of data to and from geographically distributed sites is presented. Applications include inter-stream synchronization, synchronized delivery of information in a multisite conference, and synchronization for concurrency control in distributed computations. The contributions of this protocol in the area of flow synchronization are the introduction of an adaptive synchronization delay, the flexibility to maintain multiple synchronization groups, and the use of a modular architecture that permits the client application to tailor synchronization calculations to its service requirements. Network protocols capable of maintaining network clock synchronization in the millisecond range are used. >

Base-site synchronization in a communication system

Abstract: A central-site (100) has located within it a synchronization system for purposes of backing-up a GPS external synchronization system. The central-site (100) is coupled to a plurality of base-sites (102, 103) which are required to be synchronized to one another. When the GPS signal is lost, the synchronization system within the central-site (100) allows the plurality of base-sites (102, 103) to maintain synchronization to one another. In this manner, the necessity for a synchronization system within each of the plurality of base-sites (102,103) is eliminated.

A posteriori agreement for fault-tolerant clock synchronization on broadcast networks

Abstract: The authors present a clock synchronization algorithm, a posteriori agreement, based on a new variant of the well-known convergence nonaveraging technique. Exploiting an obvious characteristic of broadcast networks, largely reduces the effect of message delivery delay variance. In consequence, the precision achieved by the algorithm is drastically improved. Accuracy preservation is near to optimal. The solution does not require the use of dedicated hardware. >

Rollback recovery in distributed systems using loosely synchronized clocks

Abstract: A rollback recovery scheme for distributed systems is proposed. The state-save synchronization among processes is implemented by bounding clock drifts such that no state-save synchronization messages are required. Since the clocks are only loosely synchronized, the synchronization overhead can be negligible in many applications. An interprocess communication protocol which encodes state-save progress information within message frames is introduced to checkpoint consistent system states. A rollback recovery algorithm that will force a minimum number of nodes to roll back after failures is developed. >

Mechanical Verification of a Generalized Protocol for Byzantine Fault Tolerant Clock Synchronization

Abstract: Schneider [Sch87] generalizes a number of protocols for Byzantine fault-tolerant clock synchronization and presents a uniform proof for their correctness. We present a mechanical verification of Schneider's protocol leading to several significant clarifications and revisions. The verification was carried out with the Ehdm system [RvHO91] developed at the SRI Computer Science Laboratory. The mechanically checked proofs include the verification that the egocentric mean function used in Lamport and Melliar-Smith's Interactive Convergence Algorithm [LMS85] satisfies the requirements of Schneider's protocol. Our mechanical verification raises a number of issues regarding the verification of fault-tolerant, distributed, real-time protocols that are germane to the design of a special-purpose logic for such problems.

HARTS: A Distributed Real-Time Architecture.

Abstract: The design, implementation, and evaluation of a distributed real-time architecture called HARTS (hexagonal architecture for real-time systems) are discussed, emphasizing its support of time-constrained, fault-tolerant communications and I/O (input/output) requirements HARTS consists of shared-memory multiprocessor nodes, interconnected by a wrapped hexagonal mesh This architecture is intended to meet three main requirements of real-time computing: high performance, high reliability, and extensive I/O The high-level and low-level architecture is described The evaluation of HARTS, using modeling and simulation with actual parameters derived from its implementation, is reported Fault-tolerant routing, clock synchronization and the I/O architecture are examined >

Hypercube clock synchronization

Abstract: Algorithms for synchronizing the times and frequencies of the clocks of Intel and Ncube hypercube multiprocessors are presented. Bounds for the error in estimating clock offsets and frequencies are formulated in terms of the clock read error and message transmission time. Clock and communication performance of the Ncube and Intel hypercubes are analysed, and performance of the synchronization algorithms is presented.

A Formal Model of Asynchronous Communication and Its Use in Mechanically Verifying a Biphase Mark Protocol

Abstract: In this paper we present a formal model of asynchronous communication as a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into the signal stream consumed by an independently clocked processor. This transformation "blurs" edges and "dilates" time due to differences in the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on asynchronous communications at ISO protocol level 1 (physical level). We develop part of the reusable formal theory that permits the convenient application of the model. We use the theory to show that a biphase mark protocol can be used to send messages of arbitrary length between two asynchronous processors. We study two versions of the protocol, a conventional one which uses cells of size 32 cycles and an unconventional one which uses cells of size 18. We conjecture that the protocol can be proved to work under our model for smaller cell sizes and more divergent clock rates but the proofs would be harder.

The problem of clock synchronization: A relativistic approach

Abstract: The problem of synchronization of the Earth-based clocks has been discussed in the framework of General Relativity Theory. The synchronization is considered as the transformation of the observers' proper time scales to the coordinate time scale of local inertial geocentric reference system, which is single for all the observers. The formulas for the relativistic corrections occurring in some methods of Earth-based clock synchronization (transported clock, duplex communication via geostationary satellite and meteor-burst link, LASSO experiments) have been derived enabling one to attain the accuracy of 0.1 ns.

System clock estimation based on clock slack minimization

Abstract: When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis. >

Synchronous clock distribution system

Abstract: A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions. The signal distribution system can be used at any or all levels of a network or complex and partitioning of the network or complex may be done based on the articulation of the clock distribution system.

Clock construction in fully asynchronous parallel systems and PRAM simulation

Abstract: The authors discuss the question of simulating synchronous computations on asynchronous systems. They consider an asynchronous system with very weak, or altogether lacking any, atomicity assumptions. The first contribution of this paper is a novel clock for asynchronous systems. The clock is a basic tool for synchronization in the asynchronous environment. It is a very robust construction and can operate in a system with no atomicity assumptions, and in the presence of a dynamic scheduler. The behavior of the clock is obtained with overwhelming probability (1-2/sup - alpha n/, alpha >0). The authors show how to harness this clock to drive a PRAM simulation on an asynchronous system. The resulting simulation scheme is more efficient than existing ones, while actually relaxing the assumptions on the underlying asynchronous system. >

A distributed real-time operating system

Abstract: Two versions of the HARTS operating system, which is based on Software Components Group's pSOS uniprocessor kernel, are presented. In one version, pSOS services are enhanced to provide interprocessor communication and a distributed naming service. In the second version, real-time fault-tolerant communication, including reliable broadcasting, clock synchronization, and group communication are added to the HARTS operating system. Three tools to evaluate the performance and fault tolerance dependability of HARTS hardware and software-a synthetic-workload generator, a monitor, and a fault injector-are described. The generator produces a synthetic workload, the monitor collects the performance data, and the fault injector simulates faulty behavior for further study. Together these tools create a facility that lets the user perform a wide range of experiments. The tools are independent, so they are equally effective separately or together, depending on the requirements. >

Static timing verification

Abstract: A method for static analysis of a software model of a circuit clocked by two clocks where the two clocks' periods are multiples of a greatest common divisor period. In the invention, a composite clock is determined with a period equal to the least common multiple of the periods of the two clocks, and the model is statically analyzed relative to the composite clock.

Continous Media Synchronization in Distributed Multimedia Systems

Abstract: Future integrated networks are expected to offer a variety of multimedia services, some of which may involve recording and playback of multiple media strands such as video and audio. Media synchronization, which refers to the temporal coordination of the playback of multiple media strands, is the subject matter of this paper. We compare the requirements for media synchronization against those of clock synchronization and argue that clock synchronization may not be necessary, sufficient or desirable for ensuring media synchronization of pre-recorded media strands. We present a synchronization technique targeted for environments in which non-deterministic variations exist in network delays and in the rates of recording and playback. In this technique, at the time of recording, temporal relationships among media strands are recorded in the form of relative time stamps. In order to facilitate synchronization, at the time of playback, the display sites transmit lightweight feedback units back to synchronizer nodes, concurrently with playback of media units. Using these feedback units, the synchronizers estimate playback times of media units of different media strands and readjust playback so as to enforce synchronization.

Clock distribution system for an integrated circuit device

Abstract: Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure. The clock generation system has a cycle-down mode wherein all the clock frequencies are divided by a desired divisor. The frequency division occurs in response to a cycle-down signal, but the different clock frequencies are not switched until all have their rising edges aligned. The result is that the state of the machine is preserved when the clocks are cycled down.

Elementary relativity with 'everyday' clock synchronization

Abstract: Although the importance of clock synchronization for relativity is discussed from time to time in the educational literature, the fact that different synchronization conventions imply different coordinizations of spacetime with ensuing changes of the form of possibly all coordinate-dependent quantities, has neither entered textbooks nor undergraduate physics education. As a consequence, there is a widespread belief among students that the familiar form of coordinate-dependent quantities like the measured velocity of light, the Lorentz transformation between two observers, 'addition of velocities', 'time dilation', 'length contraction', 'E=mc2 gamma ', which they assume under the standard clock synchronization, is relatively proper. In order to demonstrate that this is by no means so, the paper studies the consequences of a non-standard synchronization, and it is shown that drastic changes in the appearance of all these quantities are thus induced. For example, the phrases 'moving clocks go slow', and 'simultaneity is relative', which are usually considered as intrinsic features of relativity, turn out to be no longer true, whereas all coordinate-independent quantities remain of course indifferent to such a change in coordinization. Although Einstein's standard convention of clock synchronization enjoys distinct advantages over the 'everyday' method, the message clearly conveyed is that in the teaching of elementary relativity much more stress should be laid on the intrinsic (coordinate-independent) features of spacetime.

Timely Authentication in Distributed Systems

Abstract: This paper discusses the use of time in distributed authentication. Our first objective is to give reasons for the provision of authentication protocols whose correctness depends on the correct generation of timestamps. Our second objective is to explain that this proposal is not, at least theoretically, as insecure as it first seems to be. The conclusion of this paper motivated our current effort of designing a secure clock synchronization protocol as a part of our overall goal of building a secure distributed system.

Clocking strategies in high performance processors

Abstract: Recent improvements in processor implementation have focused attention on clock generation and distribution. The clocks and the latches connected to them must be carefully engineered to meet the performance requirements of the system. The author reports on the difficulty encountered in generating clocks for current processors, and describes techniques used to create these clocks, including minimizing both the internal clock skew and the skew between the internal logic and the external world. On-chip clock distribution, zero delay buffers, and self-timed systems are discussed. >

Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer gates of the registers in a pipeline maintain the important timing relationships of the non-overlapping clock signals combined with the control signals. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Overlapping clock signals are used whenever such race conditions can be avoided, as at the ends of the registered pipeline, with the resultant performance improvement.

Verifying the Interactive Convergence Clock Synchronization algorithm Using the Boyer-Moore Theorem Prover

Abstract: The application of formal methods to the analysis of computing systems promises to provide higher and higher levels of assurance as the sophistication of our tools and techniques increases. Improvements in tools and techniques come about as we pit the current state of the art against new and challenging problems. A promising area for the application of formal methods is in real-time and distributed computing. Some of the algorithms in this area are both subtle and important. In response to this challenge and as part of an ongoing attempt to verify an implementation of the Interactive Convergence Clock Synchronization Algorithm, we decided to undertake a proof of the correctness of the algorithm using the Boyer-Moore theorem prover. This paper describes our approach to proving the ICCSA using the Boyer-Moore prover.

Sub-Nanosecond Clock Synchronization and Precision Deep Space Tracking

Abstract: Interferometric spacecraft tracking is accomplished at the NASA Deep Space Network (DSN) by comparing the arrival time of electromagnetic spacecraft signals to ground antennas separated by baselines on the order of 8000 km. Clock synchronization errors within and between DSN stations directly impact the attainable tracking accuracy, with a 0.3 ns error in clock synchronization resulting in an 11 nrad angular position error. This level of synchronization is currently achieved by observing a quasar which is angularly close to the spacecraft just after the spacecraft observations. By determining the differential arrival times of the random quasar signal at the stations, clock synchronization and propagation delays within the atmosphere and within the DSN stations are calibrated. Recent developments in time transfer techniques may allow medium accuracy (50-100 nrad) spacecraft observations without near-simultaneous quasar-based calibrations. Solutions are presented for a global network of GPS receivers in which the formal errors in clock offset parameters are less than 0.5 ns. Comparisons of clock rate offsets derived from GPS measurements and from very long baseline interferometry and the examination of clock closure suggest that these formal errors are a realistic measure of GPS-based clock offset precision and accuracy. Incorporating GPS-based clock synchronization measurements into a spacecraft differential ranging system would allow tracking without near-simultaneous quasar observations. The impact on individual spacecraft navigation error sources due to elimination of quasar-based calibrations is presented. System implementation, including calibration of station electronic delays, is discussed.

Method and system for reduced metastability between devices which communicate and operate at different clock frequencies

Abstract: A method and system are provided for improved communication between devices. A first device having an associated first clock rate may communicate with a second device having an associated second clock rate. Particular periods of time are determined during which metastability may occur as a result of differences between the first clock rate and the second clock rate. Data transmitted from the first device to the second device is continually processed. During those particular periods of time when metastability may occur, the processed data is input into the second device. During all other periods of time, the data is input directly into the second device.

Semisynchrony and Real-Time (Extended Abstract)

Abstract: This paper represents the confluence of several streams of resarch on the real time complexity of distributed algorithms. The primary focus of our study is on two models and two problems: the timed automata model of Attiya and Lynch and the (“latency”) model of approximately synchronized clocks studied by Strong et. al., and the problems of consensus and atomic broadcast. We compare these models and problems, producing new results and significant improvements of previously known bounds. In particular, we are able to significantly improve the upper bound of Strong, Dolev, and Cristian on latency for Byzantine failures, giving an algorithm that is much simpler with vastly easier analysis. For this problem, we also improve the best known lower bound on latency. We also provide certain reductions between problems and models and provide preliminary answers to some new questions in the timed automata model.

Method and apparatus for the synchronization of a clock means of a telecommunication switching system

Abstract: Method and apparatus for synchronizing a clock of a telecommunication switching system. The clock of the telecommunication switching system is supplied, at least at times, with reference clock signals from a plurality of external reference clock sources. Every external reference clock source has a predetermined priority allocated to it. The supplied reference clock signals are checked for clock errors to which individual errors are allocated. For synchronization, the clock accepts an external reference clock signal dependent on the priorities allocated to the reference clock sources and dependent on the clock-error-associated error values. In an initialization, initial error values are allocated to the reference clock sources. In a re-initialization of the system, the synchronization procedure is continued from the current error values that are present at the time of the system outage.

Clocking system for asynchronous operations

Abstract: A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

A verified design of a fault-tolerant clock synchronization circuit: Preliminary investigations

Abstract: Schneider demonstrates that many fault tolerant clock synchronization algorithms can be represented as refinements of a single proven correct paradigm. Shankar provides mechanical proof that Schneider's schema achieves Byzantine fault tolerant clock synchronization provided that 11 constraints are satisfied. Some of the constraints are assumptions about physical properties of the system and cannot be established formally. Proofs are given that the fault tolerant midpoint convergence function satisfies three of the constraints. A hardware design is presented, implementing the fault tolerant midpoint function, which is shown to satisfy the remaining constraints. The synchronization circuit will recover completely from transient faults provided the maximum fault assumption is not violated. The initialization protocol for the circuit also provides a recovery mechanism from total system failure caused by correlated transient faults.

An extension to Schneider's general paradigm for fault-tolerant clock synchronization

Abstract: In 1987, Schneider presented a general paradigm that provides a single proof of a number of fault tolerant clock synchronization algorithms. His proof was subsequently subjected to the rigor of mechanical verification by Shankar. However, both Schneider and Shankar assumed a condition Shankar refers to as a bounded delay. This condition states that the elapsed time between synchronization events (i.e., the time that the local process applies an adjustment to its logical clock) is bounded. This property is really a result of the algorithm and should not be assumed in a proof of correctness. This paper remedies this by providing a proof of this property in the context of the general paradigm proposed by Schneider. The argument given is a generalization of Welch and Lynch's proof of a related property for their algorithm.