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Showing papers on "Clock synchronization published in 1993"


Proceedings ArticleDOI
22 Jun 1993
TL;DR: The Time-Triggered Protocol (TTP), which is intended for use in distributed real-time control applications that require a high dependability and guaranteed timeliness, is discussed.
Abstract: The Time-Triggered Protocol (TTP), which is intended for use in distributed real-time control applications that require a high dependability and guaranteed timeliness, is discussed. It integrates all services that are required in the design of a fault-tolerant real-time system, such as predictable message transmission, message acknowledgment in group communication, clock synchronization, membership, rapid mode changes, redundancy management, and temporary blackout handling. It supports fault-tolerant configurations with replicated nodes and replicated communication channels. TTP provides these services with a small overhead so it can be used efficiently on twisted pair channels as well as on fiber optic networks.

273 citations


Journal ArticleDOI
Ren-Song Tsay1
TL;DR: An exact zero-skew clock routing algorithm using the Elmore delay model is presented, ideal for hierarchical methods of constructing large systems that can be constructed in parallel and independently, then interconnected with exact zero skew.
Abstract: An exact zero-skew clock routing algorithm using the Elmore delay model is presented. The results have been verified with accurate waveform simulation. The authors first review a linear time delay computation method. A recursive bottom-up algorithm is then proposed for interconnecting two zero-skewed subtrees to a new tree with zero skew. The algorithm can be applied to single-staged clock trees, multistaged clock trees, and multi-chip system clock trees. The approach is ideal for hierarchical methods of constructing large systems. All subsystems can be constructed in parallel and independently, then interconnected with exact zero skew. Extensions to the routing of optimum nonzero-skew clock trees (for cycle stealing) and multiphased clock trees are also discussed. >

219 citations


Patent
16 Apr 1993
TL;DR: In this paper, the in-phase and quadrature phase components of received GMSK digital signals and utilization of time slots were sampled for initial synchronization, normal maintenance of synchronization during communication and a background procedure during normal operation.
Abstract: The high requirements of digital mobile radiotelephone communication under the GSM Standard with respect to synchronization of a mobile radiotelephone to a fixed radiotelephone station is performed by frequently (four times per so-called baseband frequency cycle) sampling contemporary in-phase and quadrature phase components of received GMSK digital signals and utilization of time slots respectively containing a frequency correction burst, a normal burst and an extended synchronization burst, respectively for initial synchronization, normal maintenance of synchronization during communication and a background procedure during normal operation. The decoding of the GMSK signal provides one-bit of information from each pair of in-phase and quadrature components sampled. The sampling of in-phase and quadrature components greatly simplifies the synchronizing procedure. Initial synchronization includes coarse frequency synchronization, coarse frame synchronization, fine frequency synchronization and fine frame synchronization. Normal maintenance of synchronization consists fine frame synchronization with fine frequency synchronization and a data signal preliminary processing. Extended synchronization consists of coarse frame synchronization and a fine frame synchronization with fine frequency synchronization.

126 citations


Patent
25 Oct 1993
TL;DR: In this article, a synchronization scheme for recording and playing independent media is presented, which allows media processes and single medium processes to achieve and maintain synchronization with each other without process interdependence and without interprocess communication.
Abstract: A computer-based multimedia presentation system is provided with a synchronization scheme for recording and playing independent media. The disclosed system and method allows media processes and single medium processes to achieve and maintain synchronization with each other without process interdependence and without interprocess communication. This capability is provided by assigning a common clock for all processes, requiring all participating media processes to reference the common clock, informing each process of, a synchronization basepoint called a "zero-time", and then allowing each process to independently synchronize itself to the common clock. The common clock itself does not provide any stimulus to a media process; it is a passive component in the synchronization. The media process is the active component, referring to the common clock as required to maintain synchronization for the particular media it is handling.

125 citations


Journal ArticleDOI
TL;DR: A strictly feedforward demodulator structure for minimum shift keying (MSK) modulation with joint nondata-aided symbol clock and frequency offset estimation is presented and is well suited for a digital implementation.
Abstract: A strictly feedforward demodulator structure for minimum shift keying (MSK) modulation with joint nondata-aided symbol clock and frequency offset estimation is presented. Due to its feedforward operation, clock synchronization and frequency offset compensation are hang-up free, and the demodulator is well suited for a digital implementation. The sampled baseband signal is passed through a nonlinearity and smoothed by a digital filter. The magnitude of the filter output directly drives the clock recovery process. The phase of the smoothed signal is an estimate of the carrier frequency offset and is used for offset compensation. Following synchronization, the signal is demodulated by differentially coherent detection. The performance of the demodulator is assessed for the AWGN and the Rayleigh flat and frequency-selective fading channel by computer simulations. >

106 citations


Patent
09 Jul 1993
TL;DR: In this paper, a distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value.
Abstract: A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard copy device, a given amount of RAM and ROM memory, a data storage device, a local clock, a transmitter/receiver, an antenna, a virtual master clock processor, and a common data bus. The method of the present invention comprises the inclusion of a node's local clock value in a message just prior to transmission over the network, storage of a node's local clock value in RAM after an incoming message has been received, and the calculation of the time delay between the sending node and the receiving node by the virtual master clock processor. The virtual master clock processor utilizes this time delay in maintaining a virtual master clock value, which it uses in adjusting the value of the node's local clock at periodic intervals. This synchronizes the receiving node to the virtual master clock value. If the magnitude of the time delay exceeds a maximum allowed value, the magnitude is clamped to the maximum allowed value, thereby maintaining synchronization within a predetermined tolerance. A node can receive a message transmitted over the FHSS LAN regardless of the message address. Synchronization is therefore maintained without requiring a node to be able to communicate with any specific node within the FHSS LAN group.

100 citations


Patent
14 Jan 1993
TL;DR: In this paper, a two-wire bus system consisting of a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses is presented.
Abstract: Two-wire bus system comprises a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses. A communication bus system has a single clock wire and a single data wire. Each wire has wired logic that upon presentation of any prevalence logic signal value imparts to that wire the prevalence logic value regardless of any non-prevalence value second presented thereto. The system has clock synchronization by a master station of any information transmission. The system arbitrates among coexistent prospective masters to select a single actual master. The protocol has a start condition by presenting said first value to the data wire with the clock line at the second value, and generates any subsequent data wire transition exclusively under existence of the prevalence value on the clock wire. The subsequent stop condition is represented by a transition to the second value on the data wire with the clock wire at the second value. The message format has an initial byte accommodating either a short slave address, or alternatively both a control signal indicating a long-format slave address inclusive of a high significance address part, to be followed in the next byte by a low significance part of the address. For enhancing the bit rate, the system has a switched pull up device, whereas furthermore each station has a slope controlled output stage.

96 citations


Patent
10 Sep 1993
TL;DR: In this article, a fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use.
Abstract: A fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use. A resistor is coupled in series between the crystal and the oscillation circuit in order to establish a desired duty cycle of the clock signal. A series connected diode capacitor network is connected between a node of the oscillator circuit and a power supply in order to ensure initiation of oscillation.

91 citations


Patent
16 Nov 1993
TL;DR: In this article, a method for synchronizing local times, maintained at nodes within a network architecture with a reference time, with a node according to the invention can synchronize its local time with the reference time source either actively or in a passive, or eavesdropping, manner.
Abstract: A method is provided for synchronizing local times, maintained at nodes within a network architecture, with a reference time A node according to the invention can synchronize its local time with the reference time source either actively or in a passive, or eavesdropping, manner Which of the two manners is to be used preferably depends on whether the node's error exceeds a threshold, and whether the node receives an unsolicited burst of synchronization messages The active manner is preferably a handshaking scheme, such as probabilistic clock synchronization, in which synchronization is initiated by a request from a node requiring synchronization, and a handshaking exchange of messages between the node and the reference time source establishes a temporal relationship, from which the node produces a synchronized time and a maximum error The passive manner is preferably a manner in which the reference time source broadcasts a burst of reference-time-stamped synchronization messages, and the node eavesdrops on the messages The receiving node establishes temporal relationships between certain ones of the local and reference time stamps Using the temporal relationships, the receiving node updates its local time and its maximum error

85 citations


Journal ArticleDOI
TL;DR: A number of distributed algorithms that make use of synchronized clocks are discussed and how clocks are used in these algorithms are analyzed.
Abstract: Synchronized clocks are interesting because they can be used to improve performance of a distributed system by reducing communication Since they have only recently become a reality in distributed systems, their use in distributed algorithms has received relatively little attention This paper discusses a number of distributed algorithms that make use of synchronized clocks and analyzes how clocks are used in these algorithms

82 citations


Journal ArticleDOI
TL;DR: An efficient algorithm for calculating the time-dependent quantities required by the numerical solution process of Deterministic and Stochastic Petri Nets (DSPNs), which employs the randomization technique and a stable calculation of Poisson probabilities is introduced.

Patent
Hovey Raymond Strong1
29 Dec 1993
TL;DR: In this article, a method for accommodating frequent discrete clock synchronization adjustments while maintaining a continuous logical clock time that amortizes the adjustments at a predetermined rate is presented. But it does not address the problem of clock synchronization adjustment amortization.
Abstract: A method for accommodating frequent discrete clock synchronization adjustments while maintaining a continuous logical clock time that amortizes the adjustments at a predetermined rate. Two distinct logical clocks are used to decouple clock synchronization procedures from adjustment amortization procedures. One logical clock is discretely synchronized to an external time reference and a second logical clock is adjusted with amortization to provide a continuous monotonically non-decreasing logical clock time.

Patent
David W. Kuddes1
14 Oct 1993
TL;DR: In this paper, a method and system for detecting and measuring a phase difference, linearly over a range of 360°, between the output signals from a primary stratum clock module (100) and a standby stratum computer (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference.
Abstract: A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360°, between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Patent
19 Nov 1993
TL;DR: In this paper, a method and apparatus for synchronizing a received communication signal is provided for synchronization, where a synchronization signal is derived from a received signal having a plurality of synchronization words and each synchronization word has a predetermined number of synchronization symbols.
Abstract: A method and apparatus is provided for synchronizing a received communication signal. A synchronization signal is derived from a received signal having a plurality of synchronization words. Each synchronization word has a predetermined number of synchronization symbols. The synchronization signal is filtered. The filtering is characterized by spacing each filter tap to correspond to synchronization word length increments. Synchronization information is generated which is based on a comparison of the filtered synchronization signal to a threshold. Finally, the synchronization information is output based on a confidence decision derived from the synchronization information.

Patent
27 Aug 1993
TL;DR: A clock synchronization system for synchronizing a number of paging stations (24) with a system controller (23) is described in this paper, where each paging station has a clock that includes a counter (52) that indicates the current local time and which is sequentially incremented by a counter advance signal applied thereto.
Abstract: A clock synchronization system for synchronizing a number of paging stations (24) with a system controller (23). Each paging station has a clock that includes a counter (52) that indicates the current local time and which is sequentially incremented by a counter advance signal applied thereto. A voltage controlled oscillator (58) generates the clocking signal that controls the advancement of the counter. A CPU (50) in the system controller monitors the time indicated by the counter and compares it to timing information received from a system clock. The timing information includes a time mark and a time mark send time. The system clock transmits to each paging system the time mark. At a future time, the system clock transmits the time mark send time which is the precise time at which the time mark was transmitted. The paging stations each measure the time interval between the time at which the time mark arrived and the time at which the time mark was transmitted by the system clock period. By subtracting the time at which the time mark was transmitted by the system clock and the propagation time to each paging station, each paging station can determine and correct the error in its clock.

Journal ArticleDOI
TL;DR: In this paper, a large class of problems that can be solved using logical clocks as if they were perfectly synchronized clocks is formally characterized, and a broadcast primitive is also proposed to simplify the task of designing and verifying distributed algorithms.
Abstract: Time and knowledge are studied in synchronous and asynchronous distributed systems. A large class of problems that can be solved using logical clocks as if they were perfectly synchronized clocks is formally characterized. For the same class of problems, a broadcast primitive that can be used as if it achieves common knowledge is also proposed. Thus, logical clocks and the broadcast primitive simplify the task of designing and verifying distributed algorithms: The designer can assume that processors have access to perfectly synchronized clocks and the ability to achieve common knowledge.

Patent
23 Dec 1993
TL;DR: In this paper, a fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads is presented, where the oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry are all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop.
Abstract: A fault tolerant multiple phase clock distribution system for providing synchronized clock signals to multiple circuit loads. Multiple electrically isolated power domains are powered by redundant AC and DC power sourcing circuits to ensure continued operation upon partial failure of the AC or DC power sourcing circuits. Multiple oscillators from the multiple power domains are synchronized to produce a group of simultaneously synchronized clock signals. Multiple synchronized clock signals from this group are then selected by selection circuitry and selection control circuitry, and are distributed to multiple circuit loads requiring simultaneous synchronization. The oscillator circuitry, synchronization circuitry, selection circuitry, and distribution circuitry is all provided in redundant form, so that the partial failure of any of the circuitry will not result in a system stop. Error recovery circuitry monitors for proper synchronization of the synchronized clock signals, and provides for automatic or manual error recovery upon detection of a synchronization error. A single phase synchronized clock signal is generated to minimize synchronization complexities, and circuitry exists at the circuit loads to generate multiple phase enable signals to emulate a multiple phase clock.

Proceedings ArticleDOI
01 Sep 1993
TL;DR: A new notion of fault-tolerance for clock synchronization algorithms is defined, tailored to the requirements and failure patterns of shared memory multiprocessors.
Abstract: Multiprocessor computer systems are becoming increasingly important as vehicles for solving computationally expensive problems. Synchronization among the processors is achieved with a variety of clock configurations. A new notion of fault-tolerance for clock synchronization algorithms is defined, tailored to the requirements and failure patterns of shared memory multiprocessors. Algorithms in this class can tolerate any number of napping processors, where a napping processor can fail by repeatedly ceasing operation for an arbitrary time interval and then resume operation without necessarily recognizing that a fault has occurred. These algorithms guarantee that, for some fixed k, once a processor P has been working correctly for at least k time, then as long as P continues to work correctly, (1) P does not adjust its clock, and (2) P's clock agrees with the clock of every other processor that has also been working correctly for at least k time. Because a working processor must synchronize in a fixed amount of time regardless of the actions of the other processors, these algorithms are called wait-free. Another useful type of fault-tolerance is called self-stabilization: starting with an arbitrary state of the system, a self-stabilizing algorithm eventually reaches a point after which it correctly performs its task.

Proceedings ArticleDOI
18 May 1993
TL;DR: The complete structure of a fully digital all feed forward synchronization unit is presented, establishing clock and carrier synchronization, and it is shown that frame and frequency synchronization can be efficiently combined.
Abstract: The complete structure of a fully digital all feed forward synchronization unit is presented, establishing clock and carrier synchronization. Although the basic synchronization concept is able to operate solely on random data, a structure is presented which is tailored to spontaneous packet transmission and time division multiple access (TDMA) applications, where additional frame synchronization has to be performed. It is shown that frame and frequency synchronization can be efficiently combined. The key features of the scheme, which are presented in terms of estimation error variances and bit error rate (BER), ensure high speed synchronization with negligible decoder performance degradation.

Journal ArticleDOI
TL;DR: An approach to checkpointing and rollback recovery in a distributed computing system using a common time base and the idea of pseudo-recovery points to develop a checkpointing algorithm that has the following advantages: reduced wait for commitment for establishing recovery lines, fewer messages to be exchanged, and less memory requirement.
Abstract: An approach to checkpointing and rollback recovery in a distributed computing system using a common time base is proposed. A common time base is established in the system using a hardware clock synchronization algorithm. This common time base is coupled with the idea of pseudo-recovery points to develop a checkpointing algorithm that has the following advantages: reduced wait for commitment for establishing recovery lines, fewer messages to be exchanged, and less memory requirement. These advantages are assessed quantitatively by developing a probabilistic model. >

Proceedings ArticleDOI
01 Sep 1993
TL;DR: The new notion of optimality applies to systems where the worst-case behavior of any clock synchronization algorithm is inherently un- bounded, and is stronger than the more common notion ofworst-case optimality.
Abstract: The problem of achieving optimal clock synchronization in a communication network with arbitrary topology and perfect clocks (that do not drift) is studied. Clock synchronization algorithms are presented for a large family of delay assumptions. Our algorithms are modular and consist of three major components. The first component holds for any type of delay assumptions; the second component holds for a large, natural family of local delay assumptions; the third component must be tailored for each specific delay assumption. Optimal clock synchronization algorithms are derived for several types of delay assumptions by appropriately tuning the third component. The delay assumptions include lower and upper delay bounds, no bounds at all, and bounds on the difference of the delay in opposite directions. In addition, our model handles systems where some processors are connected by broadcast networks in which every message arrives at all the processors at approximately the same time. A composition theorem allows combinations of different assumptions for different links or even for the same link; such mixtures are common in practice. Our results achieve the best possible precision in each execution. This notion of optimality is stronger than the more common notion ofworst-case optimality. The new notion ofoptimality applies to systems where the worst-case behavior of any clock synchronization algorithm is inherently un- bounded.

Patent
Jukka Kainulainen1
08 Nov 1993
TL;DR: In this article, a hierarchical synchronization method for a telecommunications system employing message-based synchronization and comprising a plurality of nodes interconnected by transmission lines is proposed. But the method is not suitable for wireless networks.
Abstract: The invention relates to a hierarchical synchronization method for a telecommunications system employing message-based synchronization and to a telecommunications system employing message-based synchronization and comprising a plurality of nodes interconnected by transmission lines (A, B). In the method the nodes interchange signals containing synchronization messages with information on the priority of the respective signal in the internal synchronization hierarchy of the system. In order to shorten the time periods of state transitions occurring in system failures without any risk of losing synchronization, a transmission line between two nodes is monitored to verify its bidirectionality, and as soon as the bidirectionality of the line cannot be verified, the use of the line for synchronization is prohibited.

Journal ArticleDOI
TL;DR: Given a system that guarantees only precision, the “lazy” protocol developed incurs the cost of high accuracy only when needed while keeping the basic synchronization procedure extremely simple and cheap.
Abstract: We show how synchronized clocks can be realized in a distributed system as a byproduct of a common communication paradigm where processors periodically perform broadcasts. Our approach decouples the precision concern of clock synchronization - limiting how much correct clocks can differ from each other - from the accuracy concern - limiting the rate at which any correct clock may drift from real time. Given a system that guarantees only precision, we develop a protocol whereby high accuracy can be achieved on demand. In this manner, the "lazy" protocol we obtain incurs the cost of high accuracy only when needed while keeping the basic synchronization procedure extremely simple and cheap.

Patent
17 Jun 1993
TL;DR: In this paper, a dual-phase correlator circuit is used to detect frame synchronization while a multiphase commutator (200) circuit detects bit clock synchronization in a serial bit stream.
Abstract: Simultaneously detecting both frame (52, 54) synchronization in a serial bit stream reduces the time required to have a receiver lock up to a transmitted (100) serial data signal. A dual-phase correlator circuit is used to detect frame synchronization while a multiphase commutator (200) circuit detects bit clock synchronization.

01 Jun 1993
TL;DR: In this article, the authors present a non-mathematical approach for time-scale estimation with as few equations as possible, based on a simple thought experiment, where a time scale is composed of two noiseless clocks having equal and opposite frequencies.
Abstract: The term clock is usually used to refer to a device that counts a nearly periodic signal. A group of clocks, called an ensemble, is often used for time keeping in mission critical applications that cannot tolerate loss of time due to the failure of a single clock. The time generated by the ensemble of clocks is called a time scale. The question arises how to combine the times of the individual clocks to form the time scale. One might naively be tempted to suggest the expedient of averaging the times of the individual clocks, but a simple thought experiment demonstrates the inadequacy of this approach. Suppose a time scale is composed of two noiseless clocks having equal and opposite frequencies. The mean time scale has zero frequency. However if either clock fails, the time-scale frequency immediately changes to the frequency of the remaining clock. This performance is generally unacceptable and simple mean time scales are not used. First, previous time-scale developments are reviewed and then some new methods that result in enhanced performance are presented. The historical perspective is based upon several time scales: the AT1 and TA time scales of the National Institute of Standards and Technology (NIST), the A.1(MEAN) time scale of the US Naval observatory (USNO), the TAI time scale of the Bureau International des Poids et Measures (BIPM), and the KAS-1 time scale of the Naval Research laboratory (NRL). The new method was incorporated in the KAS-2 time scale recently developed by Timing Solutions Corporation. The goal is to present time-scale concepts in a nonmathematical form with as few equations as possible. Many other papers and texts discuss the details of the optimal estimation techniques that may be used to implement these concepts.

Proceedings ArticleDOI
29 Nov 1993
TL;DR: Two novel carrier frequency estimation schemes are proposed which are well suited for a fully digital receiver and are able to cope with frequency offsets in the range of 100% and more without requiring that clock synchronization has to be performed in advance or that known symbols are available.
Abstract: Proposes two novel carrier frequency estimation schemes which are well suited for a fully digital receiver Both algorithms are able to cope with frequency offsets in the range of 100% and more without requiring that clock synchronization has to be performed in advance or that known symbols are available The authors analyze and compare their performance in terms of their acquisition speed as well as in terms of the estimation error mean and variance Computer simulations are used to verify the analysis >

Proceedings ArticleDOI
06 Oct 1993
TL;DR: A clock synchronization algorithm given by P. Verissimo et al. (1989), dubbed a posteriori agreement, a variant of the convergence nonaveraging technique, which is able to provide improved precision without compromising accuracy and reliability.
Abstract: A clock synchronization algorithm was given by P. Verissimo et al. (1989), dubbed a posteriori agreement, a variant of the convergence nonaveraging technique. By exploiting the characteristics of broadcast networks, the effect of message delivery delay variance is largely reduced. In consequence, the precision achieved by the algorithm is drastically improved. Accuracy preservation is near to optimal. A particular materialization of this algorithm, implemented as a time service of the xAMp group communications system, is given here. The algorithm was implemented using some of the primitives offered by xAMp, which simplified the work and stressed its advantages. Performance results for this implementation obtained on two different infrastructures are presented. Timings validate the design choices and clearly show that the algorithm is able to provide improved precision without compromising accuracy and reliability. >

Patent
25 Jun 1993
TL;DR: In this article, a clock synchronization start signal S 1 is transmitted by a communication controller to a terminal equipment to improve accuracy by correcting a synchronizing time with a transmission control queuing time required for the transmission of a synchronized signal to an equipment in which a clock is built in.
Abstract: PURPOSE:To improve accuracy by correcting a synchronizing time with a transmission control queuing time required for the transmission of a synchronizing signal to an equipment in which a clock is built in. CONSTITUTION:A CPU 1 of a time management device 11 reads a current time T0 from a master clock 2 and makes the request of transmission of a clock synchronization start signal S1 including the current time T0 to a terminal equipment 12 to a communication controller 3. Simultaneously a tentative clock 14 starts the measurement of an elapsed time T1. The measurement of the tentative clock 14 is stopped when the transmission of the clock synchronization start signal S1 is made possible after the queu of transmission control processing. Then a time calculation means calculates a time T1 to update a clock 6 and sends it to the terminal equipment 12 as the clock synchronization start signal S1. Upon the receipt of the clock synchronization start signal S1 by a communication controller 5, the terminal equipment 12 uses a time revision means to update the time of the clock 6 into the time T1.

Patent
16 Mar 1993
TL;DR: In this paper, a real-time clock is linked to a micro-controller, and the microcontroller only needs to be supplied in stand-by mode by a power supply.
Abstract: Currently today, the vertical blanking interval lines of TV signals are used to carry digital information, e.g. teletext, pay TV, program marking. One part of this information can be the current real time. Often consumer products are equipped with a real time clock which is linked to a micro-controller driving the complete device, e.g. a VCR. This allows to perform some programming tasks. But this real time clock needs a power supply in order to work. In case of power failure, it looses the time unless it is backed up by an expensive accumulator or a battery. A central microcontroller (1) drives a real time clock (3) and the standby function of a power supply (4) . A data extractor (2) receives a signal containing the real time, e.g. a video signal, and extracts the expected data related to the real time and transfers this data to the microcontroller. The microcontroller sets the clock after preselected time periods, e.g. once per day, and after switching on the whole apparatus. The microcontroller and the real time clock only have to be supplied in stand by mode.

Proceedings ArticleDOI
25 May 1993
TL;DR: The authors derive clock conditions for ordering operations on an object and provide clock maintenance schemes for time-stamping execution events and an algorithm is described for large-grained objects where operations are nested and non-atomic.
Abstract: Past research has concentrated on ordering events in a system where processes communicate through messages. The authors look at issues in ordering events in a distributed system based on shared objects that interact via remote procedure calls (RPCs). They derive clock conditions for ordering operations on an object and provide clock maintenance schemes for time-stamping execution events. An object clock is associated with every shared object for clock exchange among processes. A clock maintenance algorithm is incrementally presented for objects where operations are atomic and an algorithm is described for large-grained objects where operations are nested and non-atomic. >