Showing papers on "Clock synchronization published in 2010"

On Fast and Accurate Detection of Unauthorized Wireless Access Points Using Clock Skews

Abstract: We explore the use of clock skew of a wireless local area network access point (AP) as its fingerprint to detect unauthorized APs quickly and accurately. The main goal behind using clock skews is to overcome one of the major limitations of existing solutions - the inability to effectively detect Medium Access Control (MAC) address spoofing. We calculate the clock skew of an AP from the IEEE 802.11 Time Synchronization Function (TSF) time stamps sent out in the beacon/probe response frames. We use two different methods for this purpose - one based on linear programming and the other based on least-square fit. We supplement these methods with a heuristic for differentiating original packets from those sent by the fake APs. We collect TSF time stamp data from several APs in three different residential settings. Using our measurement data as well as data obtained from a large conference setting, we find that clock skews remain consistent over time for the same AP but vary significantly across APs. Furthermore, we improve the resolution of received time stamp of the frames and show that with this enhancement, our methodology can find clock skews very quickly, using 50-100 packets in most of the cases. We also discuss and quantify the impact of various external factors including temperature variation, virtualization, clock source selection, and NTP synchronization on clock skews. Our results indicate that the use of clock skews appears to be an efficient and robust method for detecting fake APs in wireless local area networks.

Time synchronization in wireless sensor networks: a survey

Abstract: Time synchronization is a critical piece of infrastructure for any distributed system. Wireless sensor networks have emerged as an important and promising research area in the recent years. Time synchronization is important for many sensor network applications that require very precise mapping of gathered sensor data with the time of the events, for example, in tracking and vehicular surveillance. It also plays an important role in energy conservation in MAC layer protocols. The paper studies different existing methods, protocols, significant time parameters (clock drift, clock speed, synchronization errors, and topologies) to achieve accurate synchronization in a sensor network. The studied Synchronization protocols include conventional time sync protocols (RBS, Timing-sync Protocol for Sensor Networks -TPSN, FTSP), and other application specific approaches such as all node-based approach, a diffusion-based method and group sync approaches aiming at providing network-wide time. The goal for writing this paper is to study most common existing time synchronization approaches and stress the need of a new class of secure-time synchronization protocol that is scalable, topology independent, fast convergent, energy efficient, less latent and less application dependent in a heterogeneous hostile environment. Our survey provides a valuable framework by which protocol designers can compare new and existing synchronization protocols from various metric discussed in the paper. So, we are hopeful that this paper will serve a complete one-stop investigation to study the characteristics of existing time synchronization protocols and its implementation mechanism in a Sensor network environment.

High-resolution, low-power time synchronization an oxymoron no more

Abstract: We present Virtual High-resolution Time (VHT), a power-proportional time-keeping service that offers a baseline power draw of a low-speed clock (e.g. 32 kHz crystal), but provides the time resolution that only a higher frequency clock could offer (e.g. 8 MHz crystal), and scales essentially linearly with access (i.e. the "reading" and "writing" of the clock). We achieve this performance by revisiting a basic assumption in the design of time-keeping systems -- that to achieve a given time-stamping resolution, a free-running timebase of equivalent frequency is needed. We show that this assumption is false and argue that the dependence is not on usage (i.e. whether on or off) but rather on access (i.e. reading and writing). Therefore, it is possible to duty cycle the free-running timebase itself, and augment it with a lower-frequency, temperature-compensated one, which achieves comparable resolution, at a fraction of the power, for typical workloads. The key technical challenge lies in duty cycling the fast clock and synchronizing the fast and slow clocks. To assess the viability of the approach, we explore how VHT could be implemented on several different platform architectures, and to study the power/performance tradeoff, we characterize VHT on one particular architecture in detail. Our results show power-proportional operation with a 10x improvement in average power and a synchronization accuracy exceeding 1 μs at duty cycles below 0.1%.

RTbox: a device for highly accurate response time measurements

Abstract: Although computer keyboards and mice are frequently used in measuring response times (RTs), the accuracy of these measurements is quite low. Specialized RT collection devices must be used to obtain more accurate measurements. However, all the existing devices have some shortcomings. We have developed and implemented a new, commercially available device, the RTbox, for highly accurate RT measurements. The RTbox has its own microprocessor and high-resolution clock. It can record the identities and timing of button events with high accuracy, unaffected by potential timing uncertainty or biases during data transmission and processing in the host computer. It stores button events until the host computer chooses to retrieve them. The asynchronous storage greatly simplifies the design of user programs. The RTbox can also receive and record external signals as triggers and can measure RTs with respect to external events. The internal clock of the RTbox can be synchronized with the computer clock, so the device can be used without external triggers. A simple USB connection is sufficient to integrate the RTbox with any standard computer and operating system.

Feedback-Based Clock Synchronization in Wireless Sensor Networks: A Control Theoretic Approach

Abstract: Most wireless sensor networks (WSNs) employ a sleep clock to enable sensor on-off mode to save energy. Since the sleep clock usually works at a relatively low frequency, it is important to correct the long-term synchronization error caused by instability and nonlinearity. In this paper, the time synchronization issue in a WSN is formulated as a closed-loop control problem. Using the proportional-integral (PI) control principle, we propose a feedback-based synchronization (FBS) scheme to compensate the clock drift caused by both internal perturbation and external disturbance. Synchronization accuracy and FBS dynamics are analyzed in terms of response time and overshoot. We also derive a formula to determine the controller parameters for different synchronization accuracy and response-time requirements. Extensive experiments have been conducted to evaluate this synchronization scheme. The results indicate that FBS is much more robust than the delay measurement time-synchronization (DMTS) protocol in different synchronization durations and sensor node configurations. It is shown that FBS achieves almost the same accuracy as the flooding time-synchronization protocol (FTSP) when synchronization period P is less than 60 s, and it outperforms FTSP when P is longer than 60 s. Furthermore, the experimental results reveal that FBS's response to an external disturbance is faster than that of FTSP in one- or two-hop WSN scenarios. In addition, FBS consumes fewer resources than FTSP.

Time synchronization using packet-layer and physical-layer protocols

Abstract: In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time.

Emergent Slot Synchronization in Wireless Networks

Abstract: This paper presents a biologically inspired approach for distributed slot synchronization in wireless networks. This is facilitated by modifying and extending a synchronization model based on the theory of pulse-coupled oscillators. The proposed Meshed Emergent Firefly Synchronization (MEMFIS) multiplexes synchronization words with data packets and adapts local clocks upon the reception of synchronization words from neighboring nodes. In this way, a dedicated synchronization phase is mitigated, as a network-wide slot structure emerges seamlessly over time as nodes exchange data packets. Simulation results demonstrate that synchronization is accomplished regardless of the arbitrary initial situation. There is no need for the selection of master nodes, as all nodes cooperate in a completely self-organized manner to achieve slot synchrony. Moreover, the algorithm is shown to scale with the number of nodes, works in meshed networks, and is robust against interference and collisions in dense networks.

Method, apparatus, and system for time synchronization

Abstract: A method, apparatus, and system for time synchronization are disclosed. The method comprising: obtaining a master sending time stamp, a slave receiving time stamp, a slave sending time stamp, and a master receiving time stamp; and adjusting the time of the slave clock according to the offset calculated from the time stamps to synchronize with the clock time of the master clock. With the present invention, in passband transmission systems that transmit signals continuously in units of symbols, the time synchronization is implemented between the master clock and the slave clock.

Statistical abstraction and model-checking of large heterogeneous systems

Abstract: We propose a new simulation-based technique for verifying applications running within a large heterogeneous system. Our technique starts by performing simulations of the system in order to learn the context in which the application is used. Then, it creates a stochastic abstraction for the application, which takes the context information into account. This smaller model can be verified using efficient techniques such as statistical model checking. We have applied our technique to an industrial case study: the cabin communication system of an airplane. We use the BIP toolset to model and simulate the system. We have conducted experiments to verify the clock synchronization protocol i.e., the application used to synchronize the clocks of all computing devices within the system.

Tight bounds for clock synchronization

Abstract: We present a novel clock synchronization algorithm and prove tight upper and lower bounds on the worst-case clock skew that may occur between any two participants in any given distributed system. More importantly, the worst-case clock skew between neighboring nodes is (asymptotically) at most a factor of two larger than the best possible bound. While previous results solely focused on the dependency of the skew bounds on the network diameter, we prove that our techniques are optimal also with respect to the maximum clock drift, the uncertainty in message delays, and the imposed bounds on the clock rates. The presented results all hold in a general model where both the clock drifts and the message delays may vary arbitrarily within pre-specified bounds.Furthermore, our algorithm exhibits a number of other highly desirable properties. First, the algorithm ensures that the clock values remain in an affine linear envelope of real time. A better worst-case bound on the accuracy with respect to real time cannot be achieved in the absence of an external timer. Second, the algorithm minimizes the number and size of messages that need to be exchanged in a given time period. Moreover, only a small number of bits must be stored locally for each neighbor. Finally, our algorithm can easily be adapted for a variety of other prominent synchronization models.

ISPD 2010 high performance clock network synthesis contest: benchmark suite and results

Abstract: In the talk, the details of ISPD 2010 high performance clock network synthesis contest will be introduced. Compared to first clock network synthesis contest in 2009, the rules have been revised to better reflect the real problems from the industry. Instead of clock latency range upon two simulations with different supply voltage settings, the total clock power (modeled by capacitance) is set to be the major judging criteria. However, a valid clock distribution network solution must have local clock skew under a preset limit. Only local clock skew constraints will be enforced because (1) early mode timing violations are often limited in local regions, and (2) local timing violations often directly lead to congestion problems which are very hard to fix. Moreover, delay variation will be formulated in the contest and simplified Monte Carlo simulation will be used to evaluate valid solutions. More importantly, a new set of benchmarks will be announced and used to decide the winner of the contest. These test-cases are all directly derived from real industrial microprocessor and high-performance ASIC designs and they have over 1000 clock sinks. More than ten academic clock synthesis tools have participated in the contest and the final results will be announced during this talk.

An Enhanced IEEE 1588 Time Synchronization for Asymmetric Communication Link in Packet Transport Network

Abstract: IEEE 1588 is a standard to synchronize independent clocks running on separate nodes of a distributed measurement and control system. In PTN (Packet Transport Network), it is considered as a key technology for supporting legacy TDM services and synchronizing 3G base stations. However, conventional IEEE 1588 synchronization algorithm assumes symmetrical links, and makes errors for asymmetric links for the calculation of the time difference between the master clock and the slave clock. We proposed an enhanced time synchronization method to calculate the time difference and the proposed method enhances an accuracy of the time synchronization.

Ethernet network synchronization systems and methods

Abstract: The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.

On the interaction of clocks, power, and synchronization in duty-cycled embedded sensor nodes

Abstract: The efficiency of the time synchronization service in wireless sensor networks is tightly connected to the design of the radio, the quality of the clocking hardware, and the synchronization algorithm employed. While improvements can be made on all levels of the system, over the last few years most work has focused on the algorithmic level to minimize message exchange and in radio architectures to provide accurate time-stamping mechanisms. Surprisingly, the influences of the underlying clock system and its impact on the overall synchronization accuracy has largely been unstudied.In this work, we investigate the impact of the clocking subsystem on the time synchronization service and address, in particular, the influence of changes in environmental temperature on clock drift in highly duty-cycled wireless sensor nodes. We also develop formulas that help the system architect choose the optimal resynchronization period to achieve a given synchronization accuracy. We find that the synchronization accuracy has a two region behavior. In the first region, the synchronization accuracy is limited by quantization error, while int he second region changes in environmental temperature impact the achievable accuracy. We verify our analytic results in simulation and real hardware experiments.

Improving Fault Tolerance in High-Precision Clock Synchronization

Abstract: The very popular Precision Time Protocol (PTP or IEEE 1588) is widely used to synchronize distributed systems with high precision. The underlying principle is a master/slave concept based on the regular exchange of synchronization messages. This paper investigates an approach to enhance PTP with fault tolerance and to overcome the transient deterioration of synchronization accuracy during a recovery from a master failure. To this end, a concept is proposed where a group of masters negotiates a fault-tolerant agreement on the system-wide time and transparently synchronizes the associated IEEE 1588 slaves. Experimental verification on the basis of an Ethernet implementation shows that the approach is feasible and indeed improves the overall synchronization accuracy in terms of fault tolerance.

A case against routing-integrated time synchronization

Abstract: To achieve more accurate global time synchronization, this paper argues for decoupling the clock distribution network from the routing tree in a multihop wireless network. We find that both flooding and routing-integrated time synchronization rapidly propagate node-level errors (typically due to temperature fluctuations) across the network. Therefore, we propose that a node chooses synchronization neighbors that offer the greatest frequency stability. We propose two methods to estimate a neighbor's stability. The first approach selects the neighbor whose Frequency Error Variance, or simply FEV, is smallest with respect to the local clock. The second approach selects the neighbor that reports the lowest FEV relative to its synchronization parent. We also propose the node-level time-variance FEV as an additive metric for selecting more stable clock trees than either naive flooding or routing-integrated time synchronization can provide. We incorporate these techniques into FTSP, a widely-used time synchronization protocol, and show that the mean error in global time significantly improved (by a factor of five) when some nodes are warmed and others are not.

Method and system for precise-clock synchronization, and device for precise-clock frequency/time synchronization

Abstract: A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

Experiences and Lessons from Implementing a Wireless Sensor Network MAC Protocol in the Castalia Simulator

Abstract: We describe our experience from the implementation of the T-MAC protocol for wireless sensor networks in the open-source Castalia simulator. Notwithstanding the popularity of the protocol in the research literature in recent years, we find several practical issues that are not addressed in the original protocol description, which lead to a degree of freedom in the protocol design and implementation and have an impact on its resulting performance. These issues include the ability of the underlying physical layer and hardware to efficiently detect the activation events in the protocol, and necessary changes to the collision resolution and clock synchronization procedures in the presence of varying sleep patterns. Our results highlight the need for rigorous detail in protocol descriptions in the research literature and provide important insights into some of the common pitfalls.

On the Seamless Interconnection of IEEE1588-Based Devices Using a PROFINET IO Infrastructure

Abstract: Several types of industrial Real-Time Ethernet (RTE) networks could be present in the same plant. This work deals with the clock synchronization problems that arise when different RTE network infrastructures are interconnected. Specifically, this paper is focused on the exploitation of PROFINET IO Conformance Class C infrastructure for the interconnection of other industrial communication devices or measurement instruments that use IEEE1588 for clock synchronization. Actually, such devices (e.g., LXI instruments, EtherNet/IP devices, etc.) cannot be satisfactorily synchronized if directly connected to the PROFINET infrastructure, because of the large time errors (up to 100 μs). The solution proposed in this paper is an intelligent clock synchronization converter that has fewer limitations if compared with other systems, like boundary clocks. The basic idea is the creation of a “black-box” (a sort of remote bridging device) for the interconnection of IEEE1588 nodes through a PROFINET IO host plant, with zero-configuration on both systems. The proposed approach differs from boundary clock since its goal is to keep the PROFINET IO and the IEEE1588 synchronization domains separated, exploiting the possibility to tunnel the IEEE1588 time information through the PROFINET IO infrastructure with sufficient precision. In order to verify the practical feasibility of the proposed solution, LXI Class B instruments have been connected to the infrastructure of a real PROFINET IO network. The results show that the standard deviation of the synchronization accuracy is only 10 ns higher than the one measured in the case of a dedicated (separated) network for the LXI instruments.

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement

Abstract: Clock gating is one of the most effective techniques to reduce clock tree power. Although it has already been studied considerably, most of the previous works are restricted to either register transfer level (RTL) or clock tree synthesis stage. Clock gating design at RTL is coarse and it pays no attention to the physical information, therefore, it often results in large wirelength overhead. While if clock gating is considered only at clock tree synthesis, the optimization space is largely limited due to the fixing of registers. To fully use the logical and physical information between registers, we propose a new flow for low-power gated clock tree design in this work. It mainly includes three parts: gated clock tree aware register placement, gated clock tree construction, and incremental placement. Compared with the previous works on clock gating, our algorithm reduces the clock tree power with much fewer gating logics, therefore, the overhead to the placement is also reduced.

Coupling-Based Internal Clock Synchronization for Large-Scale Dynamic Distributed Systems

Abstract: This paper studies the problem of realizing a common software clock among a large set of nodes without an external time reference (i.e., internal clock synchronization), any centralized control, and where nodes can join and leave the distributed system at their will. The paper proposes an internal clock synchronization algorithm which combines the gossip-based paradigm with a nature-inspired approach, coming from the coupled oscillators phenomenon, to cope with scale and churn. The algorithm works on the top of an overlay network and uses a uniform peer sampling service to fulfill each node's local view. Therefore, differently from clock synchronization protocols for small scale and static distributed systems, here, each node synchronizes regularly with only the neighbors in its local view and not with the whole system. An evaluation of the convergence speed and the synchronization error of the coupled-based internal clock synchronization algorithm has been carried out, showing how convergence time and the synchronization error depends on the coupling factor and the local view size. Moreover, the variation of the synchronization error with respect to churn and the impact of a sudden variation of the number of nodes have been analyzed to show the stability of the algorithm. In all these contexts, the algorithm shows nice performance and very good self-organizing properties. Finally, we showed how the assumption on the existence of a uniform peer-sampling service is instrumental for the good behavior of the algorithm and how, in system models where network delays are unbounded, a mean-based convergence function reaches a lower synchronization error than median-based convergence functions exploiting the number of averaged clock values.

A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop

Abstract: This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 ?W/MHz power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.

Optimal gradient clock synchronization in dynamic networks

Abstract: We study the problem of clock synchronization in highly dynamic networks, where communication links can appear or disappear at any time. The nodes in the network are equipped with hardware clocks, but the rate of the hardware clocks can vary arbitrarily within specific bounds, and the estimates that nodes can obtain about the clock values of other nodes are inherently inaccurate. Our goal in this setting is to output a logical clock at each node, such that the logical clocks of any two nodes are not too far apart, and nodes that remain close to each other in the network for a long time are better synchronized than distant nodes. This property is called gradient clock synchronization. Gradient clock synchronization has been widely studied in the static setting. We show that the bounds for the static case also apply to our highly dynamic setting: if two nodes remain at distance d from each other for sufficiently long, it is possible to synchronize their clocks to within O(d log(D/d)), where D is the diameter of the network. This is known to be optimal for static networks, and since a static network is a special case of a dynamic network, it is optimal for dynamic networks as well. Furthermore, we show that our algorithm has optimal stabilization time: when a path of length d appears between two nodes, the time required until the skew between the two nodes is reduced to O(d log(D/d)) is O(D), which we prove is optimal.

Networked clock synchronization based on second order linear consensus algorithms

Abstract: In this paper a distributed algorithm for clock synchronization is proposed. This algorithm is based on an extension of the consensus algorithm able to synchronize a family of double integrators. Since the various clocks may have different drifts, the algorithm needs to be designed so that it can work also in case of heterogeneous double integrators. Through a robust control analysis it is possible to determine the maximum admissible level of heterogeneity yielding synchronization. The first part of the paper is devoted to the analysis of an unrealistic synchronous implementation of the algorithm. However, in the last part of the paper we propose a realistic pseudo-synchronous implementation which is proved to be a perturbation of the synchronous one. From arguments related the center manifold theorem, the stability of the pseudo-synchronous is finally proved.

Network slave node and time synchronization method in network applying the same

Abstract: Provided are a network slave node and a time synchronization method using precision time protocol-like (PTP-like) in a network. The network slave node includes a packet detection unit for detecting whether the slave node receives or sends a synchronization protocol packet and recording a synchronization protocol packet receiving time and a synchronization protocol packet sending time; a hardware clock; and a control unit controlling the packet detection unit and the hardware clock. The control unit reads out the packet receiving time and the packet sending time from the packet detection unit and informs a local master node. The local master node calculates a time offset between the local master node and the slave node, and informs the control unit. The control unit adjusts the hardware clock based on the time offset so that the local master node and the slave node are time synchronized.

On Minimum Variance Unbiased Estimation of Clock Offset in a Two-Way Message Exchange Mechanism

Abstract: For many applications, distributed networks require the local clocks of the constituent nodes to run close to an agreed upon notion of time. Most of the widely used clock synchronization algorithms in such systems employ the sender-receiver protocol based on a two-way timing message exchange paradigm. Maximum likelihood estimator (MLE) of the clock offset based on the timing message exchanges between two clocks was derived in D. R. Jeske, On maximum likelihood estimation of clock offset[IEEE Trans. Commun., vol. 53, pp. 53-54, Jan. 2005], when the fixed delays are symmetric and the variable delays in each direction assume an exponential distribution with an unknown mean. Herein, the best linear unbiased estimate using order statistics (BLUE-OS) of the clock offset between two nodes is derived assuming both symmetric and asymmetric exponential network delays, respectively. The Rao-Blackwell-Lehmann-Scheffe? theorem is then exploited to obtain the minimum variance unbiased estimate (MVUE) for the clock offset which it is shown to coincide with the BLUE-OS. In addition, it is found that the MVUE of the clock offset in the presence of symmetric network delays also coincides with the MLE. Finally, in the presence of asymmetric network delays, although the MLE is biased, it is shown to achieve lesser mean-square error (MSE) than the MVUE in the region around the point where the bidirectional network link delays are symmetric and hence its merit as the most versatile estimator is fairly justified.

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS

Abstract: High density multilink interfaces such as QPI and HyperTransport include a dedicated link to carry a synchronous clock from the transmitter to receiver and shared by 5 – 20 data transceivers. Sub-rate clocks ameliorate jitter amplification in lossy channels. The forwarded clock must be frequency-multiplied and aligned with the data at each receiver. Per pin deskewing is done at startup [1]; the optimum deskew setting is stored and the calibration circuitry turned off during normal operation. Jitter on the forwarded clock is correlated with jitter on the data because both are generated by the same transmitter. Hence, jitter tolerance is improved by retiming the data with a clock that tracks correlated jitter on the forwarded clock [2]. However, since the delay of the data and clock paths typically differ by several UI, very high frequency jitter will appear out-of-phase at the receiver and should not be tracked. For a delay mismatch of L UI between clock and data, jitter tolerance is improved by tracking jitter up to f bit /4L [2]. If the mismatch is 5UI, at 4Gb/s and 8Gb/s the clock path jitter tracking bandwidth (JTB) should be 200MHz and 400MHz respectively. In summary, the clock path in a clock forwarded transceiver should provide flexible clock multiplication, a controlled phase shift, and a JTB adjustable over 100's of MHz to accommodate different channel losses, bit rates, and path delay mismatches.

Systems and methods for detecting and rejecting defective absorbent articles from a converting line

Abstract: The present disclosure relates to systems and processes for detecting and rejecting defective absorbent articles from a converting line. In particular, the systems and methods may utilize feedback from technologies, such as vision systems, sensors, remote input and output stations, and controllers with synchronized embedded clocks to accurately correlate inspection results and measurements from an absorbent article converting process. As such, the systems and methods may accurately apply the use of precision clock synchronization for both instrumentation and control system devices on a non-deterministic communications network. In turn, the clock synchronized control and instrumentation network may be used to control a reject system on converters of absorbent articles. In some embodiments, the controller will reject only defective absorbent articles without the need to reject non-defective absorbent articles.

Clock network design for ultra-low power applications

Abstract: Robust design is a critical concern in ultra-low voltage operation due to large sensitivity to process and environmental variations. In particular, clock networks need careful attention to ensure robust distribution of well-defined clock signals to avoid setup and hold time violations. In this paper, we investigate the design methodology of robust clock networks for ultra-low voltage applications. A case study shows that an optimally-chosen clock network improves skew variation by 36× and energy consumption by 49%, compared to a typical clock network. Additionally, the impact of supply voltage and technology scaling on the optimal clock network construction is investigated.

Analysis and Comparative Study of Clock Synchronization Schemes in Wireless Sensor Networks

Abstract: — Time synchronization is an important issue in wireless sensor networks. Many applications based on these WSNs assume local clocks at each sensor node that need to be synchronized to a common notion of time. Some intrinsic properties of sensor networks such as limited resources of energy, storage, computation, and bandwidth, combined with potentially high density of nodes make traditional synchronization methods unsuitable for these networks. Hence there has been an increasing research focus on designing synchronization schemes. This paper contains a survey, relative study and analysis of existing clock synchronization protocols for wireless sensor networks, based on a various factors that include precision, accuracy, cost, and complexity. The design considerations presented in this paper will help the designer in structuring a successful clock synchronization system. Specifically, the comparisons presented based on various factors will provide basic guidelines to the designer in integrating various solution features to create an efficient clock synchronization scheme for the application.