Showing papers on "Clock synchronization published in 2012"

Consensus Clock Synchronization for Wireless Sensor Networks

Abstract: Wireless sensor networks (WSN) are emerging as a valuable tool in many fields of science and industry. Time synchronization is an important issue for WSN's due to the collaborative and distributed nature of the tasks they perform. This paper describes a new technique for clock synchronization in WSNs called consensus clock synchronization that provides internal synchronization to a virtual consensus clock. It is sensitive to the limited resources available to sensor nodes and is robust to many of the challenges faced in dynamic ad-hoc networks. Simulations are presented to analyse the effectiveness of the synchronization protocol in a mesh network.

A computationally efficient approach for estimating high-rate satellite clock corrections in realtime

Abstract: Realtime satellite clock corrections are usually estimated using undifferenced phase and range observations from a global network. Because a large number of ambiguity parameters must be estimated, the computation is time-consuming. Consequently, only a sparse global network of limited number of stations is processed by most IGS Realtime Analysis Centers with an update rate of 5 s. In addition, it is very desirable to build the capability to simultaneously estimate clock corrections for multi-GNSS constellations. Although the estimation can be sped up by epoch-differenced observations that eliminate ambiguities, the derived clocks can contain a satellite-specific bias that diminishes the contribution of range observations. We introduce a computationally efficient approach for realtime clock estimation. Both the epoch-differenced phase and undifferenced range observations are used together to estimate the epoch-differenced satellite clocks and the initial clock bias for each satellite and receiver. The biased clock corrections accumulated from the estimated epoch-differenced clocks are then aligned with the estimated clock biases and provided as the final clock corrections to users. The algorithm is incorporated into the EPOS-RT software developed at GFZ (GeoForschungsZentrum) and experimentally validated with the IGS global network. The comparison with the GFZ rapid products shows that the accuracy of the clock estimation with the new approach is comparable with that of the undifferenced approach, whereas the computation time is reduced to one-tenth. As a result, estimation of high-rate satellite clocks from a large reference network and tracking satellites of multi-GNSS constellations becomes achievable.

DCS: Distributed Asynchronous Clock Synchronization in Delay Tolerant Networks

Abstract: In this paper, we propose a distributed asynchronous clock synchronization (DCS) protocol for Delay Tolerant Networks (DTNs). Different from existing clock synchronization protocols, the proposed DCS protocol can achieve global clock synchronization among mobile nodes within the network over asynchronous and intermittent connections with long delays. Convergence of the clock values can be reached by compensating for clock errors using mutual relative clock information that is propagated in the network by contacted nodes. The level of clock accuracy is depreciated with respect to time in order to account for long delays between contact opportunities. Mathematical analysis and simulation results for various network scenarios are presented to demonstrate the convergence and performance of the DCS protocol. It is shown that the DCS protocol can achieve faster clock convergence speed and, as a result, reduces energy cost by half for neighbor discovery.

Environment-aware clock skew estimation and synchronization for wireless sensor networks

Abstract: Clock synchronization is a fundamental requirement for network systems. It is particularly crucial and challenging in wireless sensor networks (WSNs), because WSN environments are dynamic and unpredictable. To tackle this problem, how to accurately estimate clock skew, the inherent reason causing clock desynchronization, is investigated. According to the measurement results, clock skew is a non-stationary random process highly correlated to temperature, and its measurements contain severe noises. Based on the observation, an additional information aided multi-model Kalman filter (AMKF) algorithm is proposed, which uses temperature measurements to assist clock skew estimation. Using AMKF, an environment-aware clock synchronization (EACS) scheme is proposed to dynamically compensate clock skew. The scheme is simple, scalable, and of low computation and energy cost. Using EACS as an additional component of the conventional synchronization protocols, the clock is updated with local information before the clock re-synchronization process is triggered, so it can substantially prolong the re-synchronization period, which not only reduces the energy consumption but also is essential for the scenarios where frequent synchronization is infeasible. The theoretical lower bound of clock skew estimation error is derived as a benchmark. Extensive simulation and experimental verification results have demonstrated the feasibility and effectiveness of the proposed scheme which can prolong the time resynchronization period by an order of magnitude in dynamic environments.

Tracking low-precision clocks with time-varying drifts using kalman filtering

Abstract: Clock synchronization is essential for a large number of applications ranging from performance measurements in wired networks to data fusion in sensor networks. Existing techniques are either limited to undesirable accuracy or rely on specific hardware characteristics that may not be available in certain applications. In this paper, we examine the clock synchronization problem in networks where nodes lack the high-accuracy oscillators or programmable network interfaces some previous protocols depend on. This paper derives a general model for clock offset and skew and demonstrates its application to real clock oscillators. We design an efficient algorithm based on this model to achieve high synchronization accuracy. This algorithm applies the Kalman filter to track the clock offset and skew. We demonstrate the performance advantages of our schemes through extensive simulations and real clock oscillator measurements.

Statistical abstraction and model-checking of large heterogeneous systems

Abstract: We propose a new simulation-based technique for verifying applications running within a large heterogeneous system Our technique starts by performing simulations of the system to learn the context in which the application is used Then, it creates a stochastic abstraction for the application, which considers the context information This smaller model can be verified using efficient techniques such as statistical model checking We have applied our technique to an industrial case study: the cabin communication system of an airplane We use the BIP toolset to model and simulate the system We have conducted experiments to verify the clock synchronization protocol ie, the application used to synchronize the clocks of all computing devices within the system

Clock synchronization in IEEE 802.11 wireless LANs using physical layer timestamps

Abstract: Packet-based clock synchronization protocols, such as IEEE 1588, depend on the quality of the timestamps taken at the reception and transmission of packets. As software-based timestamping generates large non-deterministic delays, Ethernet synchronization implementations have moved the timestamping closer to the physical layer. However, most wireless synchronization approaches are restricted to software timestamping due to the lack of hardware timestamping features. This paper1 presents a physical layer timestamping approach for IEEE 802.11b, which is able to generate timestamps with sub-100 picosecond accuracy. When synchronizing the clocks of two WLAN devices with the proposed approach, the measurements show that the system can reach synchronization accuracies below 1 ns even with standard crystal oscillators.

Semiconductor integrated circuit and control method for clock signal synchronization

Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Distributed low-power monitoring system

Abstract: A distributed wireless monitoring system with low-power remote sensors includes data encoding/compression at sensors to reduce power use from transmission and storage (where the compact data representation is decoded after upload), event activated operation/data logging, remote configuration of event triggering thresholds and correlation templates, distributed processing capabilities, and sensor clock synchronization from a network time service.

Slave diversity: Using multiple paths to improve the accuracy of clock synchronization protocols

Abstract: Running clock synchronization protocols over packet based networks introduces a considerable challenge, since clock accuracy is highly sensitive to the network latency behavior. As packet based networks are becoming the common transport for most applications requiring clock synchronization, accuracy requirements are becoming increasingly stringent. In this paper we introduce a novel approach that uses multiple communication paths between the master and slave clocks to improve the clock accuracy without increasing the total rate of protocol messages. We show that the multi-path approach can also be used to reduce the time error caused by asymmetric communication paths. We present simulation results that demonstrate the effectiveness of our approach.

An Accuracy Enhanced IEEE 1588 Synchronization Protocol for Dynamically Changing and Asymmetric Wireless Links

Abstract: IEEE 1588 is the clock synchronization protocol for networked measurement and control system, and widely used for both wire-line and wireless network environments. IEEE 1588 was initially considered for wire-line networks, but its application is extended to wireless network especially for indoor wireless networks which can not use Global Positioning System (GPS) technology. However, the conventional IEEE 1588 assumes symmetric/asymmetric fixed data rate links, and time accuracy errors are caused for dynamically changing wireless links. We propose an enhanced synchronization algorithm for IEEE 1588 in order to compensate the offset error due to the dynamically changing data rate of the wireless link and to enhance the accuracy of time.

A randomized linear algorithm for clock synchronization in multi-agent systems

Abstract: A broad family of randomized clock synchronization protocols based on a second order consensus algorithm is proposed. Under mild conditions on the graph connectivity, it is proved that the parameters of the algorithm can always be tuned in such a way that the clock synchronization is achieved in the probabilistic mean—square sense. This family of algorithms contains, as particular cases, several known approaches which range from distributed asynchronous to hierarchical synchronous protocols. This is illustrated by specializing the algorithm for the well-known broadcast and gossip scenarios in wireless communications, and for the standard hierarchical protocol used in the context of wired communications in data networks. In these cases, we show how the feasible range for the algorithm parameters can be explicitly computed. Finally, the performance of this strategy is validated by actual implementation in a real testbed and by numerical simulations.

Methods and devices for clock synchronization

Abstract: This invention relates to methods and devices for clock synchronization. The invention makes particular use of IEEE 1588 with offset and skew correction. In embodiments of the invention, the IEEE 1588 Precision Time Protocol is used to exchange time stamps between a time server and a client from which the client can estimate the clock offset and skew. In embodiments of the invention a free running clock at the client is provided with an estimation technique based on the time stamps from the IEEE 1588 PTP message exchange between the server and client clocks. The offset and skew from the estimation process can be combined with the local free running clock to give a synchronized local clock which is an accurate image of the master clock.

Inter-Packet Gap Network Clock Synchronization

Abstract: A network component comprising at least one processor configured to implement a method comprising adding a clock synchronization data to a data stream comprising a plurality of Ethernet packets, wherein the clock synchronization data is located in a gap between two of the Ethernet packets. Also disclosed is a method comprising adding a clock synchronization data to a gap between a plurality of Ethernet packets in a data stream, wherein the clock synchronization data comprises a timestamp, a first bit that indicates whether the clock synchronization data is a request or an acknowledgement, and a second bit that indicates a requested operational mode.

Methods and apparatus for synchronizing clock signals in a wireless system

Abstract: A system for verifying clock synchronization between master and slave network equipment is provided. The master includes a transmitter, first control logic, and a first processor. The slave includes a receiver, second control logic, and a second processor. The transmitter may send synchronization packets to the receiver. When a synchronization packet is sent, the first control logic forwards a first timestamp sample to the first processor. In response to receiving a synchronization packet, the receiver may generate a second timestamp sample that is forwarded to the second processor. When a number of first timestamp samples are collected at the first processor, the transmitter may send a timestamp packet to the receiver. In response to receiving the timestamp packet, the receiver may compare the first and second timestamp samples in an effort to synchronize a slave reference clock in the slave to a master reference clock in the master.

A Factor Graph Approach to Clock Offset Estimation in Wireless Sensor Networks

Abstract: The problem of clock offset estimation in a two-way timing message exchange regime is considered when the likelihood function of the observation time stamps is Gaussian, exponential, or log-normally distributed. A parameterized solution to the maximum likelihood (ML) estimation of clock offset is analytically obtained, which differs from the earlier approaches where the likelihood function is maximized graphically. In order to capture the imperfections in node oscillators, which may render a time-varying nature to the clock offset, a novel Bayesian approach to the clock offset estimation is proposed by using a factor graph representation of the posterior density. Message passing using the max-product algorithm yields an exact expression for the Bayesian inference problem. Several lower bounds on the variance of an estimator are derived for arbitrary exponential family distributed likelihood functions which, while serving as stepping stones to benchmark the performance of the proposed clock offset estimators, can be useful in their own right in classical as well Bayesian parameter estimation theory. To corroborate the theoretical findings, extensive simulation results are discussed for classical as well as Bayesian estimators in various scenarios. It is observed that the performance of the proposed estimators is fairly close to the fundamental limits established by the lower bounds.

Network node, time synchronization method and network system

Abstract: In order to select a synchronization signal higher in accuracy, thereby increasing the accuracy of the time synchronization, it is provided a network node for transferring data in a network, comprising: a network interface having a plurality of ports; a transfer control module; a time synchronizing module; a fluctuation measurement module; and a clock. The time synchronization module uses a received time synchronization packet to synchronize the clock. The fluctuation measurement module determines an accuracy of a time contained in the received time synchronization packet based on a result of comparison between the time contained in the received time synchronization packet and a time of the clock.

Reconciling fault-tolerant distributed computing and systems-on-chip

Abstract: Classic distributed computing abstractions do not match well the reality of digital logic gates, which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large Scale Integrated (VLSI) circuits: Massively concurrent, continuous computations undermine the concept of sequential processes executing sequences of atomic zero-time computing steps, and very limited computational resources at gate-level make even simple operations prohibitively costly. In this paper, we introduce a modeling and analysis framework based on continuous computations and zero-bit message channels, and employ this framework for the correctness & performance analysis of a distributed fault-tolerant clocking approach for Systems-on-Chip (SoCs). Starting out from a “classic” distributed Byzantine fault-tolerant tick generation algorithm, we show how to adapt it for direct implementation in clockless digital logic, and rigorously prove its correctness and derive analytic expressions for worst case performance metrics like synchronization precision and clock frequency. Rather than on absolute delay values, both the algorithm’s correctness and the achievable synchronization precision depend solely on the ratio of certain path delays. Since these ratios can be mapped directly to placement & routing constraints, there is typically no need for changing the algorithm when migrating to a faster implementation technology and/or when using a slightly different layout in an SoC.

Distributed robust clock synchronization

Abstract: Technology is provided for synchronization of clock information between networked devices. One or more of the devices may include one or more applications needed access to data and a common time reference between devices. In one embodiment, the devices have applications utilizing data shared in a network environment with other devices, as well as having a reference to a local clock signal on each device. A device may have a layer of code between the operating system and software applications that processes the data and maintains a remote clock reference for one or more of the other devices on the network.

Pluggable synchronization clocks, networks, systems and methods related thereto

Abstract: A pluggable synchronization clock comprising: a pluggable transceiver and a system clock synchronization subsystem embodied within the pluggable transceiver. The system clock synchronization subsystem may be adapted to implement a packet based precision time protocol. The system clock synchronization subsystem may be further adapted to include a time stamp unit capable of adding a time stamp to a frame using hardware or software.

A Simple and Robust Clock Synchronization Scheme

Abstract: Previous studies on clock synchronization problem have resulted in diverse techniques ranging from computationally expensive to simple statistical methods. The common conclusion from this investigation has been the classic complexity-performance tradeoff. This research presents a synchronization scheme that is computationally simpler and robust to the underlying network delay density function.

Network element for a packet-switched network

Abstract: A network element for a packet-switched network has a plurality of network ports for exchanging synchronization messages with further network elements, a local clock, a timestamp generation module associated to each network port for triggering generation of a timestamp, and a synchronization control module selectively configurable in a first operating mode and a second operating mode as a function of a configuration signal. When the synchronization control module is configured in the first operating mode, it is adapted to adjust an offset of the local clock as a function of the timestamps of the synchronization messages received through the slave port. When the synchronization control module is configured in the second operating mode, it is adapted to compute a residence time of a synchronization message in the network element as a function of the timestamps obtained at the time of receiving and sending the synchronization message.

Concepts for Distributed Systems Design

Abstract: I: The Nature of Distributed Systems.- 1. Distributed systems: examples and definition.- 1.1 Distribution of control and data in existing systems.- 1.1.1 Systems distributed over long distance.- 1.1.1.1 Remote access.- 1.1.1.2 Computer networks.- 1.1.1.3 Systems for distributed processing.- 1.1.2 Locally distributed systems.- 1.1.3 Multi-processor systems.- 1.1.4 Virtual distribution.- 1.2 Classification of distributed systems.- 1.2.1 Degree of coupling.- 1.2.2 Interconnection structure.- 1.2.3 Interdependence of components.- 1.2.4 Synchronization between components.- 1.3 Definition of "distributed system".- 2. Parallelism.- 2.1 Parallel processes and applications.- 2.2 Constraints on independence.- 2.3 Modular system structure and abstraction.- 3. Common problems.- 3.1 Cooperation.- 3.1.1 Compatibility.- 3.1.2 Synchronization.- 3.2 Distributed resource sharing.- 3.3 Naming and addressing.- 3.3.1 Search strategies for link editors.- 3.3.2 Naming of I/O flows.- 3.3.3 Addressing scheme of telephone networks.- 3.3.4 Process addressing by ports.- 3.4 Protection.- 3.4.1 Protection in distributed systems.- 3.5 Error recovery.- 3.5.1 Error detection.- 3.5.2 Recovery by retry.- 3.5.3 Redundant hardware.- 3.5.4 The design principle of recovery blocks.- 3.6 Real time considerations.- 3.6.1 Time-outs.- 3.6.2 Clock synchronization in distributed systems.- II: Distributed System Architecture and Communication Protocols.- 4. Architecture of distributed systems.- 4.1 Layered hierarchical system structure and physical distribution.- 4.2 Typical structure of a distributed system.- 4.2.1 Communication over a dedicated circuit.- 4.2.2 Communication through a network.- 4.2.3 A uniform transport service.- 4.2.4 Higher level protocols.- 4.3 Compatibility and interworking issues.- 4.3.1 Requirements for compatibility.- 4.3.2 Network interconnection.- 4.3.3 System interworking and adaptation.- 5. Message transport requirements and data transmission networks.- 5.1 Message transport requirements.- 5.2 Data transmission services.- 5.2.1 Dedicated circuits.- 5.2.2 Switching.- 5.2.3 Circuit and packet switching.- 5.3 The transport protocol.- 6. Link protocols.- 6.1 Transmission of bits.- 6.1.1 Interface procedures.- 6.1.2 Physical transmission media.- 6.1.3 Bit synchronization.- 6.2 Transparency and framing.- 6.2.1 Bit-oriented method.- 6.2.2 Character-oriented method.- 6.2.3 Method based on envelope transmission.- 6.3 Transmission error detection and correction.- 6.3.1 Principles.- 6.3.2 Error detecting codes.- 6.3.3 Error correcting codes.- 6.4 Retransmission protocols.- 6.4.1 Principles.- 6.4.2 The "alternating bit" protocol.- 6.4.3 The HDLC classes of procedures.- 6.4.4 Multiplexing.- 7. Technological developments and standards.- III: Formal Description Techniques.- 8. Role of specifications in the design of distributed systems.- 8.1 Specification of different scope and detail.- 8.1.1 The "reference model".- 8.1.2 Service specifications.- 8.1.3 Protocol specifications.- 8.1.4 Implementation specifications.- 8.2 System design validation.- 8.3 Protocol implementation assessment.- 8.4 Protocol implementation.- 9. A state transition formalism for the description of systems.- 9.1 The basic model.- 9.1.1 Transition systems.- 9.1.2 Operations.- 9.1.3 Transitions and relations between states.- 9.1.4 Abstraction.- 9.1.5 Parallelism and functionality.- 9.2 Reachability and execution sequences.- 9.2.1 Possible operation sequences.- 9.2.2 Liveness.- 9.2.3 Equivalence between systems.- 9.3 Synchronization mechanisms.- 9.4 Non-instantaneous operations.- 9.4.1 Mutual exclusion.- 9.4.2 Queueing condiserations and scheduling.- 9.5 Processes.- 9.5.1 The concept.- 9.5.2 Cooperation.- 9.5.3 Mutual exclusion.- 9.6 The induction principle.- 9.7 Distinction between "control structure" and "interpretation".- 9.8 Assertions.- 9.9 Formalized specification methods for systems with parallelism.- 10. A formal description technique for distributed systems.- 10.1 Discussion of specification concepts.- 10.1.1 Components and their interactions.- 10.1.2 Ports and interconnections.- 10.1.3 Elements of a specification.- 10.2 A transport service specification.- 10.2.1 Ports and interaction primitives.- 10.2.2 Local rules for a service access point.- 10.2.3 Specification of the service provider component.- 10.3 Step-wise refinement of specifications.- 10.3.1 The internal structure of components: examples.- 10.3.2 Comments on component substructure.- 10.3.3 Port refinements.- References.- Annex: Possible approaches to stepwise refinement, protocol specification and implementation.- Annex 1: A general transition model for protocols and communication services (G.v. Bochmann).- Annex 2: Development and structure of an X.25 implementation (G.v. Bochmann and J. Tankoano).- Annex 3: Structured specification of communicating systems (G.v. Bochmann and M. Raynal).

A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms

Abstract: We demonstrate a new type of adaptive continuous-time linear equalizer (CTLE) based on asynchronous undersampling histograms. Our CTLE automatically selects the optimal equalizing filter coefficient among several predetermined values by searching for the coefficient that produces the largest peak value in histograms obtained with asynchronous undersampling. This scheme is simple and robust and does not require clock synchronization for its operation. A prototype chip realized in 0.13-μm CMOS technology successfully achieves equalization for 5.4-Gbit/s 231 - 1 pseudorandom bit sequence data through 40-, 80-, and 120-cm PCB traces and 3-m DisplayPort cable. In addition, we present the results of statistical analysis with which we verify the reliability of our scheme for various sample sizes. The results of this analysis are confirmed with experimental data.

Network and method for implementing a high-availability grand master clock

Abstract: In a network based on IEEE 1588, comprising a plurality of nodes (201, 501) and a plurality of connections where each connection connects at least two nodes to allow communication between nodes including the exchange of messages according to a network protocol, the the synchronization of IEEE 1588 is improved by allowing multiple grandmaster clocks (701) to operate simultaneously in the system. Thus, the re-election protocol of IEEE 1588 is made obsolete. For this, a multitude of nodes form a subsystem implementing a high-availability grand master clock (301) according to the IEEE 1588 Standard, wherein the subsystem is configured to tolerate the failure of at least one of said nodes forming said subsystem. Bi-directional communication link (401) are configured for physically connecting a IEEE 1588 Master clocks (201) and/or IEEE 1588 Slave clocks (201) to the subsystem implementing a high-availability grand master clock (301).

Synchronization in computer network

Abstract: A method, apparatus, and computer program product for operating a network node of a computer network is provided. According to an embodiment, the network node of a first synchronization island detects that at least one communication port of the network node is connected to a network node of a second synchronization island, wherein the first synchronization island and the second synchronization island are synchronized to different master clocks; acquires an announce message from the communication port connected to the second synchronization island, the announce message comprising operational parameters of a master clock of the second synchronization island, wherein the operational parameters comprise a priority parameter representing priority of the master clock of the second synchronization island; and overwrites automatically the priority parameter of the acquired announce message by a new priority parameter that indicates that the priority of the master clock of the second synchronization island is lower than the priority of the at least one master clock of the first synchronization island.

Highly Accurate Timestamping for Ethernet-Based Clock Synchronization

Abstract: It is not only for test and measurement of great importance to synchronize clocks of networked devices to timely coordinate data acquisition. In this context the seek for high accuracy in Ethernet-based clock synchronization has been significantly supported by enhancements to the Network Time Protocol (NTP) and the introduction of the Precision Time Protocol (PTP). The latter was even applied to instrumentation and measurement applications through the introduction of LXI. These protocols are usually implemented in software; however, the synchronization accuracy can only substantially be improved by hardware which supports drawing of precise event timestamps. Especially, the quality of the timestamps for ingress and egress synchronization packets has a major influence on the achievable performance of a distributed measurement or control system. This paper analyzes the influence of jitter sources remaining despite hardware support and proposes enhanced methods for up to now unmatched timestamping accuracy in Ethernet-based synchronization protocols. The methods shown in this paper reach sub-nanosecond accuracy, which is proven in theory and practice.

Joint localization and clock synchronization for wireless sensor networks

Abstract: A fully-asynchronous network with one target sensor and a few anchors (nodes with known locations) is considered. Localization and synchronization are traditionally treated as two separate problems. In this paper, localization and synchronization is studied under a unified framework. We present a new model in which time-stamps obtained either via two-way communication between the nodes or with a broadcast based protocol can be used in a simple estimator based on least-squares (LS) to jointly estimate the position of the target node as well as all the unknown clock-skews and clock-offsets. The Cramer-Rao lower bound (CRLB) is derived for the considered problem and is used as a benchmark to analyze the performance of the proposed estimator.