Showing papers on "Clock synchronization published in 2018"
TL;DR: A localization system that permits multiple robots to localize themselves simultaneously within a given area, which has been outfitted with a network of stationary radio modules, is developed and the functionality of the system is demonstrated by multiple micro-quadrocopters localizing and flying simultaneous within a space.
Abstract: In this paper, we concern ourselves with the development of a localization system that permits multiple robots to localize themselves simultaneously within a given area, which has been outfitted with a network of stationary radio modules. We derive a clock synchronization scheme for the radio modules, show how each module is able to compute its position within the network, and finally demonstrate how multiple robots are able to operate simultaneously within the space by using time-difference-of-arrival measurements to localize themselves. Since robots are passive receivers in this system and are able to compute their position based only on received and local information, multiple robots can operate simultaneously and without the need for central coordination or centralized localization infrastructure. All results presented in this paper are supported by experimental results, and the functionality of the system is demonstrated by multiple micro-quadrocopters localizing and flying simultaneously within a space.
102 citations
TL;DR: This paper has an enhancement of allowing a mixture of the priority-based scheduling and time-triggered, which expand the solution space for the GCLs, and analyzes the latency bounds for the critical traffic in the TSN network.
Abstract: Distributed safety-critical applications in industrial automation, aerospace, and automotive, require worst-case end-to-end latency analysis for critical communication flows in order to prove their correct behavior in the temporal domain. With the advent of time sensitive networks (TSNs), distributed applications can be built on top of standard Ethernet technologies without sacrificing real-time characteristics. The time-based transmission selection and clock synchronization mechanism defined in the TSN enable the real-time transmission of frames based on a global schedule configured through so-called gate control lists (GCLs). This paper has an enhancement of allowing a mixture of the priority-based scheduling and time-triggered, which expand the solution space for the GCLs. Then, it is necessary to analyze the latency bounds for the critical traffic in the TSN network. In this paper, we start from the assumption that the GCLs, i.e., the communication schedules, and the traffic class (priority) assignment for critical flows are given for each output port and derive, using network calculus, an analysis of the worst-case delays that individual critical flows can experience along the hops from sender to receiver(s). Our method can be employed for the analysis of the TSNs where the GCLs have been created in advance, as well as for driving the GCL synthesis that explores a larger solution space than previous methods, which required a complete isolation of transmission events from different traffic classes. We validate our model and analysis by performing experiments on both synthetic and real-world use-cases, showing the scalability of our implementation as well as the impact of certain GCL properties (gate overlapping and traffic class assignments) on the worst-case latency of critical communication flows.
90 citations
TL;DR: In this article, the authors introduce the concepts of cooperative dilution intensity (CDI) and relative CDI to characterize the interaction between agents, which can be interpreted as properties of a random walk over the network.
Abstract: Accurate clock synchronization is required for collaborative operations among nodes across wireless networks. Compared with traditional layer-by-layer methods, cooperative network synchronization techniques lead to significant improvement in performance, efficiency, and robustness. This paper develops a framework for the performance analysis of cooperative network synchronization. We introduce the concepts of cooperative dilution intensity (CDI) and relative CDI to characterize the interaction between agents, which can be interpreted as properties of a random walk over the network. Our approach enables us to derive closed-form asymptotic expressions of performance limits, relating them to the quality of observations as well as the network topology.
89 citations
Proceedings Article•
09 Apr 2018TL;DR: This paper presents HUYGENS, a software clock synchronization system that uses a synchronization network and leverages three key ideas to achieve synchronization to within a few 10s of nanoseconds under varying loads, with a negligible overhead upon link bandwidth due to probes.
Abstract: Nanosecond-level clock synchronization can be an enabler of a new spectrum of timing- and delay-critical applications in data centers. However, the popular clock synchronization algorithm, NTP, can only achieve millisecond-level accuracy. Current solutions for achieving a synchronization accuracy of 10s-100s of nanoseconds require specially designed hardware throughout the network for combatting random network delays and component noise or to exploit clock synchronization inherent in Ethernet standards for the PHY.
In this paper, we present HUYGENS, a software clock synchronization system that uses a synchronization network and leverages three key ideas. First, coded probes identify and reject impure probe data--data captured by probes which suffer queuing delays, random jitter, and NIC timestamp noise. Next, HUYGENS processes the purified data with Support Vector Machines, a widely-used and powerful classifier, to accurately estimate one-way propagation times and achieve clock synchronization to within 100 nanoseconds. Finally, HUYGENS exploits a natural network effect--the idea that a group of pairwise synchronized clocks must be transitively synchronized-- to detect and correct synchronization errors even further.
Through evaluation of two hardware testbeds, we quantify the imprecision of existing clock synchronization across server-pairs, and the effect of temperature on clock speeds. We find the discrepancy between clock frequencies is typically 5-10ms/sec, but it can be as much as 30ms/sec. We show that HUYGENS achieves synchronization to within a few 10s of nanoseconds under varying loads, with a negligible overhead upon link bandwidth due to probes. Because HUYGENS is implemented in software running on standard hardware, it can be readily deployed in current data centers.
88 citations
TL;DR: To achieve master-salve synchronization, the stochastic scheduling and the Round-Robin scheduling protocols are proposed and utilized and some sufficient synchronization criteria regarding to the gain matrices, sampling intervals and communication delays are derived for the closed-loop master–salve system.
Abstract: Under the mild assumption that only the sampled-data output information about the master system is available, synchronization of networked master–salve system consisting of a high-order master system and a low-order slave system is investigated in this paper. Specifically, the dynamics of the master system and those of the slave system are allowed to be characterized by heterogeneous nonlinear systems. The communication between these two systems are transmitted by multiple sensors over a communication network, while at each sampling instant, only one sensor is allowed to transmit its current information to the controller’s side according to some carefully designed scheduling protocols. To achieve master–salve synchronization, the stochastic scheduling and the Round-Robin scheduling protocols are, respectively, proposed and utilized. By appropriately designing observer and controller for the slave system, some sufficient synchronization criteria regarding to the gain matrices, sampling intervals and communication delays are derived for the closed-loop master–salve system under respectively the stochastic scheduling and the Round-Robin scheduling protocols. Last, two numerical examples are simulated to validate the effectiveness of the theoretical results.
67 citations
TL;DR: This paper proposes a resilient consensus-type algorithm based on the so-called mean subsequence reduced (MSR) technique, where each normal node ignores the outliers in the clock data collected from its neighbors and makes updates using data from the past if new data have not arrived yet.
Abstract: In this paper, we study a distributed approach based on consensus algorithms for clock synchronization in wireless sensor networks. The sensor nodes face two types of uncertainties. One is that some of the nodes in the network can be faulty and transmit arbitrary signals by not following the given protocol; similar effects may be caused by false data injection by an external malicious attacker. The other is that the communication is unreliable and the packets exchanged may become lost. To deal with these uncertainties, we propose a resilient consensus-type algorithm based on the so-called mean subsequence reduced (MSR) technique, where each normal node ignores the outliers in the clock data collected from its neighbors and makes updates using data from the past if new data have not arrived yet. We establish network connectivity conditions in terms of graph robustness for the MSR algorithm to attain resilient properties.
61 citations
TL;DR: PISync protocols have better or comparable performance over existing protocols in the WSN literature in terms of rate of convergence and steady-state error with the additional advantages of requiring minimal CPU overhead, memory allocation, and code footprint independent of network size and topology, and of employing blind communication.
Abstract: In this paper, we present a novel control-theoretic time synchronization algorithm, named PISync for synchronizing sensor nodes in wireless sensor networks (WSNs). The PISync algorithm is based on an adaptive proportional–integral controller. It applies a proportional feedback (P) and an integral feedback (I) on the local measured synchronization errors to compensate the differences between the clock offsets and the clock speeds. We present practical flooding-based and fully distributed protocol implementations of the PISync algorithm, and we provide theoretical analysis to highlight the benefits of this approach in terms of improved steady-state error and scalability as compared with existing synchronization algorithms. We show through theoretical analysis, real-world experiments, and simulations that PISync protocols have better or comparable performance over existing protocols in the WSN literature in terms of rate of convergence and steady-state error with the additional advantages of requiring minimal CPU overhead, memory allocation, and code footprint independent of network size and topology, and of employing blind communication.
55 citations
TL;DR: Two medium access control protocols are proposed that are capable of providing time division multiple access (TDMA) to sensor nodes without the need for centralized clock synchronization and significantly outperform T-Lohi, a classical contention-based MAC protocol for underwater acoustic networks.
Abstract: This paper investigates the application of underwater acoustic sensor networks for large scale monitoring of the ocean environment. The low propagation speed of acoustic signals presents a fundamental challenge in coordinating the access to the shared communication medium in such networks. In this paper, we propose two medium access control (MAC) protocols, namely, Transmit Delay Allocation MAC (TDA-MAC) and Accelerated TDA-MAC, that are capable of providing time division multiple access (TDMA) to sensor nodes without the need for centralized clock synchronization. A comprehensive simulation study of a network deployed on the sea bed shows that the proposed protocols are capable of closely matching the throughput and packet delay performance of ideal synchronized TDMA. The TDA-MAC protocols also significantly outperform T-Lohi, a classical contention-based MAC protocol for underwater acoustic networks, in terms of network throughput and, in many cases, end-to-end packet delay. Furthermore, the assumption of no clock synchronization among different devices in the network is a major advantage of TDA-MAC over other TDMA-based MAC protocols in the literature. Therefore, it is a feasible networking solution for real-world underwater sensor network deployments.
53 citations
TL;DR: By incorporating clock drift factor, the accuracy of clock offset estimation of conventional PTP scheme can be significantly improved, and in order to enhance the application of proposed clock synchronization scheme, typically in non-line-of-sight industrial communication environment.
Abstract: In this paper, an enhanced precision time protocol (PTP) to enable precise clock synchronization between the nodes within an industrial wireless sensor network deployed for critical control and automation applications is proposed. As it will be shown, by incorporating clock drift factor, the accuracy of clock offset estimation of conventional PTP scheme can be significantly improved. Furthermore, in order to enhance the application of proposed clock synchronization scheme, typically in non-line-of-sight industrial communication environment, the problem of efficient symbol timing synchronization is also studied, and a simplified, yet efficient, start of the frame detector that enables robust timestamp message decoding during clock synchronization period is also proposed.
48 citations
TL;DR: It is shown that all one-way time transfer protocols are vulnerable to replay attacks that can potentially compromise timing information, and IEEE 1588 PTP, although a two-way synchronization protocol, is not compliant with these conditions, and is therefore insecure.
Abstract: This paper establishes a fundamental theory of secure clock synchronization. Accurate clock synchronization is the backbone of systems managing power distribution, financial transactions, telecommunication operations, database services, etc. Some clock synchronization (time transfer) systems, such as the global navigation satellite systems, are based on one-way communication from a master to a slave clock. Others, such as the network transport protocol, and the IEEE 1588 precision time protocol (PTP), involve two-way communication between the master and slave. This paper shows that all one-way time transfer protocols are vulnerable to replay attacks that can potentially compromise timing information. A set of conditions for secure two-way clock synchronization is proposed and proved to be necessary and sufficient. It is shown that IEEE 1588 PTP, although a two-way synchronization protocol, is not compliant with these conditions, and is therefore insecure. Requirements for secure IEEE 1588 PTP are proposed, and a second example protocol is offered to illustrate the range of compliant systems.
44 citations
TL;DR: This paper investigates the clock synchronization schemes of active node and overhearing node with immediate clock readjustment and proposes the maximum-likelihood estimators of the clock skew and the corresponding Cramer–Rao lower bounds, derived assuming Gaussian delays.
Abstract: Time synchronization is indispensable for convenient network management, device monitoring, security, and other fundamental operations in industrial wireless sensor networks (IWSNs) Over the past few decades, a wide variety of highly accurate clock synchronization protocols have been investigated by employing powerful statistical signal processing techniques However, most two-way exchange estimation schemes do not readjust the node's local clock upon every resynchronization before the clock parameters are estimated And it may not be appropriate in IWSNs where time synchronization is consistently required Based on the two-way message exchange mechanism, this paper investigates the clock synchronization schemes of active node and overhearing node with immediate clock readjustment The maximum-likelihood estimators of the clock skew and the corresponding Cramer–Rao lower bounds are derived assuming Gaussian delays Simulation and experimental results validate the performance of the proposed estimators
TL;DR: An alternate approach for GPS clock prediction is proposed: coefficients of linear polynomial and sinusoidal terms are estimated with the epoch-differenced clock offsets from the IGU observed part, while the constant coefficient is computed with the latest RTS clock corrections.
Abstract: The international GNSS service (IGS) has been providing an open-access real-time service (RTS) since 2013, which allows users to carry out real-time precise point positioning (RT-PPP). As the availability of RTS products is vital for RT-PPP, a disruption in receiving RTS products will be a concern. Currently, the IGS Ultra-rapid (IGU) orbit is accurate enough to be used as an alternative orbit for RTS during RTS outages, while the precision of the IGU predicted clock offsets is far below that of the RTS clock product. The existing clock prediction methods based on received RTS clock data will not work well if the discontinuity arises shortly after the start of the RT-PPP processing due to the lack of RTS clock data to fit the prediction model or to predict clock offsets at a high precision. Even if there is a sufficient amount of RTS clock data available, saving large amounts of RTS clock data would also use processor memory. An alternate approach for GPS clock prediction is proposed. The prediction model, composed of linear polynomial and sinusoidal terms, is similar to those used by the precious methods. The main innovation is the determination of the model coefficients: coefficients of linear and sinusoidal terms are estimated with the epoch-differenced clock offsets from the IGU observed part, while the constant coefficient is computed with the latest RTS clock corrections. There is no need to save the received RTS clock corrections, and clock prediction can be carried out even with only one epoch of RTS data. Evaluation of the proposed method shows that the predicted clock offsets within a short period of prediction time, e.g., 5 min, are slightly worse than RTS clock data. Even when the predicted time reaches up to 1 h, the precision of the predicted clock offsets is still higher than that of IGU predicted clock offsets by about 50%.
TL;DR: The study reveals advantages, drawbacks, and practical limitations of the control schemes caused by the clocks drifts and facilitates the selection of the most suitable control scheme for the practical deployment of microgrids.
Abstract: In inverter-based microgrids, individual inverters operate usually with their own digital processor. The clocks used to generate the time signals of these processors differ from each other due to clock drifts. This paper analyzes the impact that the drifts of the processors clocks produce on the operation of inverter-based islanded microgrids. Several communication-free secondary control schemes, which avoid well-known problems caused by digital communication networks, are considered. Active power sharing and frequency regulation are the metrics used to evaluate the performance of the control schemes. The study reveals advantages, drawbacks, and practical limitations of the control schemes caused by the clocks drifts. Therefore, it facilitates the selection of the most suitable control scheme for the practical deployment of microgrids. The theoretical results are validated by experimental tests in a laboratory microgrid equipped with three inverters and three digital signal processors driven by autonomous internal clocks.
TL;DR: A novel high-efficiency blind clock synchronization mechanism without knowing the channel parameters of the diffusion coefficient and the transmitter–receiver distance is presented, which may help chronopharmaceutical drug delivery applications.
Abstract: Molecular communication offers new possibilities in the micro- and nano-scale application environments. Similar to other communication paradigms, molecular communication also requires clock synchronization between the transmitter and the receiver nanomachine in many time- and control-sensitive applications. This letter presents a novel high-efficiency blind clock synchronization mechanism. Without knowing the channel parameters of the diffusion coefficient and the transmitter–receiver distance, the receiver only requires one symbol to achieve synchronization. The samples are used to estimate the propagation delay by least square method and achieve clock synchronization. Single-input multiple-output diversity design is then proposed to mitigate channel noise and therefore to improve the synchronization accuracy. The simulation results show that the proposed clock synchronization mechanism has a good performance and may help chronopharmaceutical drug delivery applications.
15 Oct 2018
TL;DR: An architecture for clock synchronization in IoT devices that is designed to be scalable, flexibly accommodate diverse hardware, and maintain tight synchronization over a range of operating conditions is described.
Abstract: In this paper, we describe an architecture for clock synchronization in IoT devices that is designed to be scalable, flexibly accommodate diverse hardware, and maintain tight synchronization over a range of operating conditions. We begin by examining clock drift on two standard IoT prototyping platforms. We observe clock drift on the order of seconds over relatively short time periods, as well as poor clock rate stability, each of which make standard synchronization protocols ineffective. To address this problem, we develop a synchronization system, which includes a lightweight client, a new packet exchange protocol called SPoT and a scalable reference server. We evaluate the efficacy of our system over a range of configurations, operating conditions and target platforms. We find that SPoT performs synchronization 22x and 17x more accurately than MQTT and SNTP, respectively, at high noise levels, and maintains a clock accuracy of within ~15ms at various noise levels. Finally, we report on the scalability of our server implementation through microbenchmark and wide area experiments, which show that our system can scale to support large numbers of clients efficiently.
TL;DR: A novel clock synchronization algorithm for wireless sensor networks (WSNs) that is derived using a fast finite-time average consensus idea, and is fully distributed, meaning that each node relies only on its local clock readings and reading announcements from its neighbours.
TL;DR: A method for autonomously compensating temperature-dependent clock rate changes and allowing reduction in the total energy spent for time synchronization, which is practically relevant concern for low data rate, low energy budget TSCH networks, especially those exposed to environments with changing temperature.
Abstract: Networks deployed in real-world conditions have to cope with dynamic, unpredictable environmental temperature changes. These changes affect the clock rate on network nodes, and can cause faster clock de-synchronization compared to situations where devices are operating under stable temperature conditions. Wireless network protocols, such as time-slotted channel hopping (TSCH) from the IEEE 802.15.4-2015 standard, are affected by this problem, since they require tight clock synchronization among all nodes for the network to remain operational. This paper proposes a method for autonomously compensating temperature-dependent clock rate changes. After a calibration stage, nodes continuously perform temperature measurements to compensate for clock drifts at runtime. The method is implemented on low-power Internet of Things (IoT) nodes and evaluated through experiments in a temperature chamber, indoor and outdoor environments, as well as with numerical simulations. The results show that applying the method reduces the maximum synchronization error more than ten times. In this way, the method allows reduction in the total energy spent for time synchronization, which is practically relevant concern for low data rate, low energy budget TSCH networks, especially those exposed to environments with changing temperature.
TL;DR: The ultimate limits of short-term synchronization performance due to FPGA implementation have been derived through analysis and then demonstrated using the existing WRS enhanced with an additional daughterboard, achieving a tenfold improvement in terms of phase noise, jitter, and short- term stability with respect to the current WR performance.
Abstract: This paper investigates the ultimate limits of White Rabbit (WR), an high-accuracy time distribution system based on field-programmable gate array (FPGA). The knowledge of such limits is essential for new emerging applications that are evaluating WR. In this paper, we identify and study the key elements in the WR synchronization: the digital dual mixer time difference phase detector and the Gigabit Ethernet transceiver. The benchmarks and experimental analysis of these key elements allow us to determine the WR switch (WRS) performance limits and evaluate their evolution with newer FPGAs. The identified performance limits are achievable by the present-day generation of WRS. The ultimate limits of short-term synchronization performance due to FPGA implementation have been derived through analysis and then demonstrated using the existing WRS enhanced with an additional daughterboard. This combination (WRS and daughterboard) achieves a tenfold improvement in terms of phase noise, jitter, and short-term stability with respect to the current WR performance. Both phase detectors and Gigabit transceivers have a similar phase noise contribution equal to a short-term stability of modified Allan deviation 4E−13 at $\tau = 1$ s (dominated by flicker phase modulation noise).
TL;DR: In this article, a point-to-point clock synchronization protocol based on bidirectionally exchanging photons produced in spontaneous parametric down conversion (SPDC) was proposed, which exploits tight timing correlations between photon pairs to achieve a precision of 51ps in 100s with count rates of order 200s$^{-1}
Abstract: We demonstrate a point-to-point clock synchronization protocol based on bidirectionally exchanging photons produced in spontaneous parametric down conversion (SPDC). The technique exploits tight timing correlations between photon pairs to achieve a precision of 51ps in 100s with count rates of order 200s$^{-1}$. The protocol is distance independent, secure against symmetric delay attacks and provides a natural complement to techniques based on Global Navigation Satellite Systems (GNSS). The protocol works with mobile parties and can be augmented to provide authentication of the timing signal via a Bell inequality check.
TL;DR: A novel received signal strength (RSS) based localization algorithm is proposed that only requires the energy of the received signal rather than the PD pulse itself to locate a PD source for nine different positions.
Abstract: The term partial discharge (PD) refers to a partial bridging of insulating material between electrodes that sustain an electric field in high-voltage (HV) systems. Long-term PD activity can lead to catastrophic failures of HV systems resulting in economic, energy and even human life losses. Such failures and losses can be avoided by continuously monitoring PD activity. Existing techniques used for PD localization including time of arrival (TOA) and time difference of arrival (TDOA), are complicated and expensive because they require time synchronization. In this paper, a novel received signal strength (RSS) based localization algorithm is proposed. The reason that RSS is favoured in this research is that it does not require clock synchronization and it only requires the energy of the received signal rather than the PD pulse itself. A comparison was made between RSS based algorithms including a proposed algorithm, the ratio and search and the least squares algorithm to locate a PD source for nine different positions. The performance of the algorithms was evaluated by using two field scenarios based on seven and eight receiving nodes, respectively. The mean localization error calculated for two-field-trial scenarios show, respectively, 1.80 m and 1.76 m for the proposed algorithm for all nine positions, which is the lowest of the three algorithms.
01 Sep 2018
TL;DR: This paper proposes an extended time-of-flight (TOF) error estimation model for TWR methods, based on the IEEE 802.15.4 standard, and demonstrates the pitfalls of the symmetric double-sided TWR (SDS-TWR) method, which is commonly used to reduce the TOF error due to clock drifts.
Abstract: In absence of clock synchronization, Two-Way Ranging (TWR) is the most commonly used technique for measuring the distance between two wireless transceivers. The existing time-of-flight (TOF) error estimation model, the IEEE 802.15.4-2011 standard, is specifically based on clock drift error. However, it is insufficient when an in-depth comparative analysis of different TWR methods is required. In this paper, we propose an extended TOF error estimation model for TWR methods, based on the IEEE 802.15.4 standard. Using the proposed model, we perform an analytical study of TOF error estimation among different TWR methods. The model is validated with numerical simulation results. Moreover, we demonstrate the pitfalls of the symmetric double-sided TWR (SDS-TWR) method, which is commonly used to reduce the TOF error due to clock drifts.
12 Feb 2018
TL;DR: By incorporating a barker-code based beacon for time alignment and cross-technology transmission of timestamps, Crocs achieves robust and accurate synchronization among WiFi and ZigBee devices, with the synchronization error lower than 1 millisecond.
Abstract: Clock synchronization is a key function in embedded wireless systems and networks. This issue is equally important and more challenging in IoT systems nowadays, which often include heterogeneous wireless devices that follow different wireless standards. Conventional solutions to this problem employ gateway-based indirect synchronization, which suffer low accuracy. This paper for the first time studies the problem of cross-technology clock synchronization. Our proposal called Crocs synchronizes WiFi and ZigBee devices by direct cross-technology communication. Crocs decouples the synchronization signal from the transmission of a timestamp. By incorporating a barker-code based beacon for time alignment and cross-technology transmission of timestamps, Crocs achieves robust and accurate synchronization among WiFi and ZigBee devices, with the synchronization error lower than 1 millisecond. We further make attempts to implement different cross-technology communication methods in Crocs and provide insight findings with regard to the achievable accuracy and expected overhead.
TL;DR: The role of time and frequency in SLR as well as the error sources are discussed before it address the transfer of time between ground and space.
Abstract: Highly precise time and stable reference frequencies are fundamental requirements for space geodesy. Satellite laser ranging (SLR) is one of these techniques, which differs from all other applications like Very Long Baseline Interferometry (VLBI), Global Navigation Satellite Systems (GNSS) and finally Doppler Orbitography and Radiopositioning Integrated by Satellite (DORIS) by the fact that it is an optical two-way measurement technique. That means that there is no need for a clock synchronization process between both ends of the distance covered by the measurement technique. Under the assumption of isotropy for the speed of light, SLR establishes the only practical realization of the Einstein Synchronization process so far. Therefore it is a powerful time transfer technique. However, in order to transfer time between two remote clocks, it is also necessary to tightly control all possible signal delays in the ranging process. This paper discusses the role of time and frequency in SLR as well as the error sources before it address the transfer of time between ground and space. The need of an improved signal delay control led to a major redesign of the local time and frequency distribution at the Geodetic Observatory Wettzell. Closure measurements can now be used to identify and remove systematic errors in SLR measurements.
TL;DR: This paper studies the impact of clock mismatches and quantization on networked control systems, and presents necessary conditions and sufficient conditions for stabilizability, which show that a larger clock offset requires a finer quantization.
Abstract: This paper studies the impact of clock mismatches and quantization on networked control systems. We consider a scenario where the plant's state is measured by a sensor that communicates with the controller through a network. Variable communication delays and clock jitter do not permit a perfect synchronization between the clocks of the sensor and controller. We investigate limitations on the clock offset tolerable for stabilization of the feedback system. For a process with a scalar-valued state, we show that there exists a tight bound on the offset above which the closed-loop system cannot be stabilized with any causal controllers. For higher dimensional plants, if the plant has two distinct poles, then the effect of clock mismatches can be canceled with a finite number of measurements, and hence there is no fundamental limitation. We also consider the case where the measurements are subject to quantization in addition to clock mismatches. For first-order plants, we present necessary conditions and sufficient conditions for stabilizability, which show that a larger clock offset requires a finer quantization.
TL;DR: An improved quadratic constraint weighted least-squares estimator that accounts for synchronization errors is proposed to reduce the positioning errors and an alternative performance measure, namely the localization success probability, is introduced to evaluate the location accuracy.
Patent•
19 Jun 2018TL;DR: In this paper, the authors provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals and/or alignment to phase information lost in decimation.
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
TL;DR: This paper presents a fully uncoordinated matrix-based CH algorithm termed ABIO, which consists of one fixed Anchor column and several variable Binary extended columns in each CH period and presents a probability-based dynamic discovery (PDD) algorithm, which can achieve timely rendezvous in the unstable environment with high probability.
Abstract: Neighbor discovery is a significant communication primitive for adjacent unmanned aerial vehicles (UAVs) to construct a flying ad hoc network (FANET). The multi-channel nature of FANETs makes channel hopping (CH) a feasible rendezvous method for UAVs to hop to the same available channel simultaneously and initiate a connection. However, due to the intrinsic uncoordinated constraints of dispersed UAVs (e.g., lack of clock synchronization, heterogeneous local channels, symmetric roles, and oblivious identifiers), it is challenging to design a performant CH algorithm that can achieve fast neighbor discovery in dynamic FANETs. In this paper, we present a fully uncoordinated matrix-based CH algorithm termed ABIO, which consists of one fixed Anchor column and several variable Binary (i.e., I/O-bit) extended columns in each CH period. The deterministic overlaps as well as the co-primality property of channel numbers among different kinds of columns provide the rendezvous guarantee. Furthermore, for the case with frequently varying channel status, we present a probability-based dynamic discovery (PDD) algorithm. By virtue of the cumulative probability estimation and selection of the qualified channels, the PDD algorithm can achieve timely rendezvous in the unstable environment with high probability. We rigorously analyze the theoretical neighbor discovery latency. We also validate the feasibility and efficiency of the proposed algorithms through extensive simulations. Evaluation results demonstrate the superiority of our algorithms in both stable and unstable communication environments.
TL;DR: This work presents the first fault-tolerant distributed clock synchronization algorithm that deterministically guarantees correct behavior in the presence of metastability, and as a consequence, clock domains can be synchronized without using synchronizers, enabling metastability-free communication between them.
Abstract: In digital circuits, metastability can cause deteriorated signals that neither are logical 0 nor logical 1, breaking the abstraction of Boolean logic. Synchronizers, the only traditional countermeasure, exponentially decrease the odds of maintained metastability over time. We propose a fundamentally different approach: It is possible to deterministically contain metastability by fine-grained logical masking so that it cannot infect the entire circuit. At the heart of our approach lies a time- and value-discrete model for metastability in synchronous clocked digital circuits, in which metastability is propagated in a worst-case fashion. The proposed model permits positive results and passes the test of reproducing Marino's impossibility results. We fully classify which functions can be computed by circuits with standard registers. Regarding masking registers, we show that more functions become computable with each clock cycle, and that masking registers permit exponentially smaller circuits for some tasks. Demonstrating the applicability of our approach, we present the first fault-tolerant distributed clock synchronization algorithm that deterministically guarantees correct behavior in the presence of metastability. As a consequence, clock domains can be synchronized without using synchronizers, enabling metastability-free communication between them.
TL;DR: The CPS-Sim is realized by coordinating Matlab/Simulink as the physical system simulator and QualNet as the communication network simulator, and its efficacy is demonstrated by using a distributed algorithm in wireless sensor networks for clock synchronization.
01 Oct 2018
TL;DR: A new concept is presented, called System Level LET, which generalizes Logical Execution Time and extends it to the scope of the entire, distributed system while preserving determinism in time and data flow as well as composability.
Abstract: Cause-effect chains are omnipresent in automotive and other distributed software, where sensor data is first collected and then processed in order to control actuators. It is challenging to find a correct implementation which respects all latency and precedence constraints of the numerous cause-effect chains contained in the software and which is at the same time robust towards software updates and changes. The Logical Execution Time (LET) programming model has proven to be a very promising solution featuring determinism in time and data flow as well as composability, but it is inherently limited to the scope of an electronic control unit (ECU) due to strict requirements w.r.t. clock synchronization and zero-time communication. In this paper, we present and evaluate a new concept, called System Level LET, which generalizes LET and extends it to the scope of the entire, distributed system while preserving determinism in time and data flow as well as composability. System Level LET has relaxed synchronization requirements, is independent of scheduling policies and can be combined with different communication semantics.