Showing papers on "Clock synchronization published in 2020"

WiNar: RTT-based Sub-meter Indoor Localization using Commercial Devices

Abstract: WiFi time of flight (ToF) measurement has been supported recently by the wireless LAN protocols to improve WiFi localization. Specifically, the IEEE 802.11-2016 standard has a fine-time measurement (FTM) protocol that can be used to measure the WiFi signal round trip time (RTT). In this paper, we present the design and implementation of WiNar, a WiFi RTT-based indoor location determination system that combines the advantages of both fingerprint and ranging-based techniques to overcome the different challenges of indoor environments. Using commercial-off-the-shelf access points and mobile phones, WiNar leverages the propagation time of the wireless signal with a fingerprinting model to address the multipath, non-line-of-sight, signal attenuation, and interference challenges of the indoor environments. Moreover, when leveraging the round trip time measurements, WiNar does not require clock synchronization between the transmitter and the receiver. We discuss the different components of the system and its implementation on the Android operating system. Our results show that WiNar has a sub-meter localization accuracy with an average localization error of less than 0.86 meters for two different testbeds. This accuracy outperforms the performance of the traditional signal strength (RSS) fingerprinting technique by at least 38% and ranging-based multi-lateration technique by at least 148%. Finally, our system is also robust to heterogeneous devices.

BLAS: Broadcast Relative Localization and Clock Synchronization for Dynamic Dense Multiagent Systems

Abstract: Spatiotemporal information plays crucial roles in a multiagent system (MAS). However, for a highly dynamic and dense MAS in unknown environments, estimating its spatiotemporal states is a difficult problem. In this article, we present BLAS—a wireless broadcast relative localization and clock synchronization system to address these challenges. Our BLAS system exploits a broadcast architecture, under which a MAS is categorized into parent agents that broadcast wireless packets and child agents that are passive receivers, to reduce the number of required packets among agents for relative localization and clock synchronization. We first propose an asynchronous broadcasting and passively receiving protocol. The protocol schedules the broadcast of parent agents using a distributed time division multiple access scheme and delivers interagent information used for joint relative localization and clock synchronization. We then present distributed state estimation approaches in parent and child agents that utilize the broadcast interagent information for joint estimation of spatiotemporal states. The simulations and real-world experiments based on ultra-wideband illustrate that our proposed BLAS can not only enable accurate, high-frequency, and real-time estimation of relative position and clock parameters but also support theoretically an unlimited number of agents.

Distributed Clock Synchronization Based on Intelligent Clustering in Local Area Industrial IoT Systems

Abstract: Accurate clock synchronization in the industr-ial-Internet-of-Things systems forms the cornerstone of distributed interaction and coordination among various infrastructures and machines in an industrial environment. However, due to the widespread use of wireless networks in industrial applications, constraints inherent to wireless networks including uncertain propagation delays, random packets losses, and unguaranteed communication resources are unavoidable, leading to dramatically increased clock synchronization error and unreliable or even outdated information. Meanwhile, time information transmissions are vulnerable to suffer from malicious attacks, causing unreliable timestamps and insecure synchronization. In this article, we proposed a distributed clock synchronization protocol based on an intelligent clustering algorithm to achieve accurate, secure, and packet-efficient clock synchronization. The varying rate of skew of every clock is collected and utilized for cluster formation as well as malicious node detection. According to established clusters, various synchronization frequencies are assigned, which can avoid excessive network access contention, reduce overall communication resource consumption, and improve synchronization accuracy. Meanwhile, a two-tier fault detection algorithm consists of outlier detection and second-order regressive model prediction is applied to determine potential malicious nodes. The simulation results demonstrate that the proposed protocol overwhelms simultaneous synchronization protocols in terms of synchronization performance and faulty node detection.

Semidefinite Programming Methods for Alleviating Clock Synchronization Bias and Sensor Position Errors in TDOA Localization

Abstract: This paper investigates the problem of source localization using signal time-difference-of-arrival (TDOA) measurements in the presence of clock synchronization bias and sensor position errors. Our existing work has developed a unified solution for TDOA localization in the presence of sensor position errors but clock synchronization bias was not considered. Clock synchronization bias is a more complex problem often encountered in practical localization networks. This paper further generalizes this framework to include clock synchronization bias. The proposed technique employs multiple calibration emitters to simultaneously alleviate both the sensor position errors and clock synchronization bias. The maximum likelihood estimator (MLE) for this problem is optimal, but too complex to be applied in practice. We develop a semidefinite programming (SDP) based localization algorithm to effectively solve the MLE problem. This SDP algorithm can reach the Cram $\acute{\text{e}}$ r-Rao lower bound when sensor position errors are not unrealistically large.

Synchronous subnanosecond clock and data recovery for optically switched data centres using clock phase caching

Abstract: The rapid growth in the amount of data being transferred within data centres, combined with the slowdown in Moore’s Law, creates challenges for the future scalability of electronically switched data-centre networks Optical switches could offer a future-proof alternative, and photonic integration platforms have been demonstrated with nanosecond-scale optical switching times End-to-end switching time is, however, currently limited by the clock and data recovery time, which typically takes microseconds, removing the benefits of nanosecond optical switching Here we show that a clock phase caching technique can provide clock and data recovery times of under 625 ps (16 symbols at 256 Gb s−1) Our approach uses the measurement and storage of clock phase values in a synchronized network to simplify clock and data recovery versus conventional asynchronous approaches We demonstrate the capabilities of our technique using a real-time prototype with commercial transceivers and validate its resilience against temperature variation and clock jitter A clock synchronization method, which is based on optical clock distribution and clock phase caching, can provide subnanosecond clock and data recovery times for fast optical switching in large-scale data centre networks using off-the-shelf commercial transceivers

Overview of time synchronization for iot deployments: Clock discipline algorithms and protocols

Abstract: Internet of Things (IoT) is expected to change the everyday life of its users by enabling data exchanges among pervasive things through the Internet. Such a broad aim, however, puts prohibitive constraints on applications demanding time-synchronized operation for the chronological ordering of information or synchronous execution of some tasks, since in general the networks are formed by entities of widely varying resources. On one hand, the existing contemporary solutions for time synchronization, such as Network Time Protocol, do not easily tailor to resource-constrained devices, and on the other, the available solutions for constrained systems do not extend well to heterogeneous deployments. In this article, the time synchronization problems for IoT deployments for applications requiring a coherent notion of time are studied. Detailed derivations of the clock model and various clock relation models are provided. The clock synchronization methods are also presented for different models, and their expected performance are derived and illustrated. A survey of time synchronization protocols is provided to aid the IoT practitioners to select appropriate components for a deployment. The clock discipline algorithms are presented in a tutorial format, while the time synchronization methods are summarized as a survey. Therefore, this paper is a holistic overview of the available time synchronization methods for IoT deployments.

Sundial: Fault-tolerant Clock Synchronization for Datacenters

Abstract: Clock synchronization is critical for many datacenter applications such as distributed transactional databases, consistent snapshots, and network telemetry. As applications have increasing performance requirements and datacenter networks get into ultra-low latency, we need submicrosecond-level bound on time-uncertainty to reduce transaction delay and enable new network management applications (e.g., measuring one-way delay for congestion control). The state-of-the-art clock synchronization solutions focus on improving clock precision but may incur significant time-uncertainty bound due to the presence of failures. This significantly affects applications because in large-scale datacenters, temperature-related, link, device, and domain failures are common. We present Sundial, a fault-tolerant clock synchronization system for datacenters that achieves ∼100ns time-uncertainty bound under various types of failures. Sundial provides fast failure detection based on frequent synchronization messages in hardware. Sundial enables fast failure recovery using a novel graphbased algorithm to precompute a backup plan that is generic to failures. Through experiments in a >500-machine testbed and large-scale simulations, we show that Sundial can achieve ∼100ns time-uncertainty bound under different types of failures, which is more than two orders of magnitude lower than the state-of-the-art solutions. We also demonstrate the benefit of Sundial on applications such as Spanner and Swift congestion control.

A Novel Rapid-Flooding Approach With Real-Time Delay Compensation for Wireless-Sensor Network Time Synchronization.

Abstract: One-way-broadcast-based flooding time synchronization algorithms are commonly used in wireless-sensor networks (WSNs). However, the packet delay and clock drift pose a challenge to accuracy, as they entail serious by-hop error accumulation problems in the WSNs. To overcome this, a rapid-flooding multibroadcast time synchronization with real-time delay compensation (RDC-RMTS) is proposed in this article. By using a rapid-flooding protocol, flooding latency of the referenced time information is significantly reduced in the RDC-RMTS. In addition, a new joint clock skew-offset maximum-likelihood estimation (MLE) is developed to obtain the accurate clock parameter estimations and the real-time packet delay estimation. Moreover, an innovative implementation of the RDC-RMTS is designed with an adaptive clock offset estimation. The experimental results indicate that the RDC-RMTS can easily reduce the variable delay and significantly slow the growth of by-hop error accumulation. Thus, the proposed RDC-RMTS can achieve accurate time synchronization in large-scale complex WSNs.

IEEE 1588 for Clock Synchronization in Industrial IoT and Related Applications: A Review on Contributing Technologies, Protocols and Enhancement Methodologies

Abstract: Precise time synchronization becomes a vital constituent due to the rigorous needs of several time-sensitive applications. The clock synchronization protocol is one of the fundamental factors that can define the quality of communication. Our study starts with a brief discussion on the application domain of precise time synchronization and comes with an in-depth study of the synchronization with the main focus on the IEEE 1588 Precision Time Protocol (PTP). We have compared the well-known synchronization techniques and conclude that the PTP is the most appropriate answer to robust clock synchronization though challenges are there that requires thoughtful efforts and modification in the current version. The working mechanism and main components of the PTP network are discussed. We have established a testbench using commercially available devices and development boards to evaluate the PTP performance under different configurations. Major sources of synchronization error and other aspects contributing to precision are examined. This paper discussed numerous approaches that could enhance the performance of the PTP protocol. Structures for PTP based wireless clock synchronization required by advanced applications has also been discussed. In the end, paper focuses on the main industrial application areas in which PTP plays an important role, including WLAN, optical data centers, Smart grid, IEC 61850, etc. We conclude the paper by identifying the future trends and research directions for PTP based clock synchronization.

E-DTDOA Based Localization for Wireless Sensor Networks With Clock Drift Compensation

Abstract: A high time resolution localization scheme, using ultra-wide band ranging signal with bandwidth of 2GHz, is proposed for a fully asynchronous wireless sensor network (WSN). The proposed scheme is specifically useful for sensor nodes which are designed to operate at very low ADC sampling rate, in the order of 2–3 MHz, but still achieves the sampling resolution in the order of sub-nanoseconds. To achieve low sampling rate, equivalent time sampling (ETS) technique is used at the sensor nodes. Reconstructed signal obtained by ETS technique, that require periodic transmission of the same signal repetitively, is severely affected by the variation in transmitter and receiver clock drift as against the real time sampling where the variations are due to receiver node clock drift only. Thus, it requires a protocol to precisely estimate the transmitter and receiver clock parameters. A scheme, which uses a novel mathematical equivalent time of arrival (E-TOA) model for ETS based system, for clock drift estimation is presented. Based on clock drift estimation parameters, receiver nodes are tuned to the same frequency. E-TOA measurements are further used to propose an equivalent differential time difference of arrival (E-DTDOA) based ranging algorithm, which relaxed the time synchronization requirement between the wireless nodes, and still achieving high time resolution. The E-DTDOA range measurements are subsequently used to obtain precise localization of the target node/s. The feasibility of the algorithm proposed is demonstrated experimentally using in house designed wireless sensor nodes.

Consensus-Based Clock Synchronization in Wireless Sensor Networks With Truncated Exponential Delays

Abstract: Clock synchronization is a significant basis for many operations in wireless sensor networks. The distributed consensus-based clock synchronization has gained popularity for its robustness and scalability. However, most consensus-based clock synchronization protocols either ignore communication delay, or consider bounded delay without distribution model. In this article, based on the consensus theory, the clock synchronization problem with truncated exponential delay is investigated. We use the maximum likelihood method to estimate relative drift between nodes. A recursive method is presented to cope with the maximum likelihood estimation, which largely reduces the computational complexity and the storage overhead. Then, the estimated relative drift is adopted in the two main parts of consensus clock synchronization: drift compensation and offset compensation. We give the rigorous theoretical proof of the convergence of the network-wide synchronization. Simulations further verify the theoretical analysis and show that the synchronization performance of the proposed algorithm is better than existing similar schemes under truncated exponential delays.

Clock Synchronization in Wireless Sensor Networks Based on Bayesian Estimation

Abstract: Clock synchronization is essential for the operation of upper layer applications in Wireless Sensor Networks. When the network hops needed for clock synchronization message transmission is large, synchronization error will accumulate and synchronization accuracy may be reduced significantly. Moreover, in the existing synchronization algorithms, large number of communication resources and node energy will be expended in sending and receiving time messages. To solve the problem, this paper proposes a Bayesian estimation-based time synchronization (BETS) algorithm which uses synchronization error compensation to reduce the amount of time message interaction in clock synchronization. The key idea of BETS is to calibrate the prior information of synchronization error with a small amount of field sampling time information, which will eliminate the impact of environment on clock synchronization accuracy. In addition, the gradient descent method is used to estimate the relative clock drift rate, which provides the reference for setting algorithm execution cycle and ensures clock synchronization during network operation time. In order to evaluate the theoretical lower bound of the performance of BETS, the Bayesian Cramer-Rao bound (BCRB) is derived. Both simulation and hardware experiments show that BETS algorithm makes full use of the prior information of synchronization error, hence fewer time messages are required in synchronization and the resource constraints of WSNs are satisfied.

Solving Orthogonal Group Synchronization via Convex and Low-Rank Optimization: Tightness and Landscape Analysis

Abstract: Group synchronization aims to recover the group elements from their noisy pairwise measurements. It has found many applications in community detection, clock synchronization, and joint alignment problem. This paper focuses on the orthogonal group synchronization which is often used in cryo-EM and computer vision. However, it is generally NP-hard to retrieve the group elements by finding the least squares estimator. In this work, we first study the semidefinite programming (SDP) relaxation of the orthogonal group synchronization and its tightness, i.e., the SDP estimator is exactly equal to the least squares estimator. Moreover, we investigate the performance of the Burer-Monteiro factorization in solving the SDP relaxation by analyzing its corresponding optimization landscape. We provide deterministic sufficient conditions which guarantee: (i) the tightness of SDP relaxation; (ii) optimization landscape arising from the Burer-Monteiro approach is benign, i.e., the global optimum is exactly the least squares estimator and no other spurious local optima exist. Our result provides a solid theoretical justification of why the Burer-Monteiro approach is remarkably efficient and effective in solving the large-scale SDPs arising from orthogonal group synchronization. We perform numerical experiments to complement our theoretical analysis, which gives insights into future research directions.

Efficient Joint Localization and Synchronization in Distributed MIMO Radars

Abstract: This letter addresses the problem of joint localization and clock synchronization in distributed multiple-input multiple-output (MIMO) radar systems. While the well-known two-stage weighted least squares (WLS) method provides an acceptable estimate of target position when a rough approximation of antennas clock parameters, the drifts and offsets, is available, its performance can degrade quickly if the level of uncertainty in these values increases. The proposed method offers a solution for synchronizing the clocks while simultaneously improving the target position estimate. The uncertainty in positions of antennas is also taken into account. The presented method is shown to be approximately unbiased and able to attain the Cramer-Rao lower bound (CRLB) under small Gaussian error assumption. Numerical simulations are employed to validate the theoretical findings.

Implementation of efficient clock synchronization using elastic timer technique in iot

Abstract: Synchronizing IoT is the way of executing synchronized tasks allowing the chronological sequential ordering of information. On the basis of existing literature, several research studies have been shown on synchronization approaches. Implementation of Elastic Timer Synchronization technique is proposed that works in the better form in case of Energy Consumption and Convergence Time as compared to standard or basic synchronization technique. The proposed work increases the elasticity of the algorithm and efficient in terms of Energy or Power consumption and network convergence time simultaneously.

Robust Clock Skew and Offset Estimation for IEEE 1588 in the Presence of Unexpected Deterministic Path Delay Asymmetries

Abstract: IEEE 1588, built on the classical two-way message exchange scheme, is a popular clock synchronization protocol for packet-switched networks. Due to the presence of random queuing delays in a packet-switched network, the joint recovery of the clock skew and offset from the timestamps of the exchanged synchronization packets can be treated as a statistical estimation problem. In this paper, we address the problem of clock skew and offset estimation for IEEE 1588 in the presence of possible unknown asymmetries between the deterministic path delays of the forward master-to-slave path and reverse slave-to-master path, which can result from incorrect modeling or cyber-attacks. First, we develop lower bounds on the mean square estimation error for a clock skew and offset estimation scheme for IEEE 1588 assuming the availability of multiple master-slave communication paths and complete knowledge of the probability density functions (pdf) describing the random queuing delays. Approximating the pdf of the random queuing delays by a mixture of Gaussian random variables, we then present a robust iterative clock skew and offset estimation scheme that employs the space alternating generalized expectation-maximization (SAGE) algorithm for learning all the unknown parameters. Numerical results indicate that the developed robust scheme exhibits a mean square estimation error close to the lower bounds.

Secure and scalable access control protocol for IoT environment

Abstract: Smart applications based on IoT has gained huge momentum in recent times. Typically, these applications involve the deployment of smart devices within the perception layer of three-tier IoT architecture. The smart devices may be required to be re-deployed due to adversary attacks, or outage of power. Deployment of new smart devices within the perception layer of IoT based applications is a significant security concern. The deployed smart device can be a malicious node that can disrupt the complete network operations. An access control protocol regulates the deployment of smart devices within the perception layer. Besides obliging the resource constraint nature of smart devices, an access control protocol must also fulfill specific security and functional requirements for its practical consideration. In this paper, an access control protocol based on Elliptical Curve Cryptography (ECC) has been presented. Besides sufficing to all other major security and functional requirements, the proposed protocol is also scalable and independent of clock synchronization issues. The correctness and the soundness of the proposed protocol has been validated using BAN logic. The proposed protocol has also been formally validated using automated validation of internet security protocols and applications (AVISPA) and Scyther tools. The proposed protocol has been compared with relevant existing schemes on various security and functional requirements. The comparison suggests that the proposed protocol has a better trade-off as compared to relevant existing schemes.

Finite-Time Consensus-Based Clock Synchronization Under Deception Attacks

Abstract: This paper concentrates on the finite-time clock synchronization problem for wireless sensor networks (WSNs) under deception attacks. Compared with adding additional communication links to a network, we introduce a new mechanism termed as “trusted link” to improve the resilience of the network, and show that with small changes (set a fraction of links as the trusted links) in the network structure the network robustness for deception attacks can be improved significantly. Then, an iterative learning control based consensus control methodology with built-in attack mitigation mechanism is proposed. Not only the security and robustness are guaranteed by the proposed controller, but also the convergence time is fixed, which makes the synchronization algorithm more suitable for practical WSNs. Finally, simulation results are provided to demonstrate the effectiveness of the theoretical results.

How to Make Firmware Updates over LoRaWAN Possible

Abstract: The requirements of embedded software management—due to concerns about security vulnerabilities or for feature updates in the Internet of Things (IoT) deployments—have raised the need for Firmware Updates Over The Air (FUOTA). With FUOTA's support, security updates, new functionalities, and optimization patches can be deployed with little human intervention to embedded devices over their lifetime. However, supporting FUOTA over one of the most promising IoT networking technologies, LoRaWAN, is not a straightforward task due to LoRaWAN's limitations that challenge bulk downlink data transfer such as a firmware image. Therefore, the LoRa Alliance has proposed new specifications to support multicast, fragmentation, and clock synchronization on top of LoRaWAN, which are essential features to enable efficient FUOTA. In this paper, we review these new specifications and evaluate the FUOTA process in order to quantify the impact of the different FUOTA parameters in terms of the firmware update time, the device's energy consumption, and the firmware update efficiency, showing different trade-offs among the parameters. For this, we developed FUOTASim, a simulation tool that allows us to determine the best FUOTA parameters.

Estimators for Time Synchronization—Survey, Analysis, and Outlook

Abstract: Time (or clock) synchronization is a large and vital field of research, as synchronization is a precondition for many applications. A few example applications are distributed data acquisition, distributed databases, and real-time communication. First, this survey paper introduces the research area of time synchronization and emphasizes its relation to other research areas. Second, we give an overview of the state-of-the-art of time synchronization. Herein, we discuss both established protocol and research approaches. We analyze all techniques according to three criteria: used estimation algorithm, achievable synchronization accuracy, and the experimental conditions. In our opinion, this analysis highlights potential improvements. The most important question in this survey is as follows: which estimation method can be used to achieve which accuracies under which conditions? The intention behind this is to identify estimation methods that are particularly worth considering, as these already achieve good results in the wireless area but have not yet been examined in the wired area (and vice versa). This survey paper differs from other surveys in particular through the consideration of wireless and wired synchronization and the focus on estimation algorithms and their achievable accuracy.

Extended Synchronization Protocol Based on IEEE802.1AS for Improved Precision in Dynamic and Asymmetric TSN Hybrid Networks

Abstract: This paper proposes an extension of the precision time protocol (IEEE 802.1AS) to improve clock synchronization in hybrid networks including both wireless and wire-bound segments. This extension targets systems based on Time Sensitive Networking (TSN) such as industrial applications and vehicular systems. By considering the deterministic delays and the clock drift, the precision of the clock synchronization of the standard 802.1AS scheme can be significantly improved. Furthermore, in order to support dynamic communication environments with mobile nodes, the problem of asymmetric delays in the transmission of the timing packets of the synchronization protocol is also considered. Therefore, a Path Deviation Delay (PDD) filter is introduced to monitor the traffic behavior of timing packets as well as to exclude outlier values which can occur as a result of dynamic and asymmetric scenarios. The paper presents a simulation framework for the proposed protocol to evaluate it with TSN-based systems that support the TSN features (e.g. IEEE 802.1Qci and IEEE 802.1Qbv sub-standards). The simulation results show that the proposed protocol improves the synchronization precision compared with the standard 802.1AS protocol. It shows that the proposed protocol enhances the synchronization precision to less than 1 microsecond. In contrast, the synchronization error increases significantly with the standard protocol in the presence of different asymmetric ratios and in mobile node scenarios.

A Detection Model Against Precision Time Protocol Attacks

Abstract: The IEEE 1588 Precision Time Protocol (PTP) is a widely used mechanism to provide time synchronization of computer clocks down to microsecond accuracy as required by many financial and industrial applications ("IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems," 2008). However, PTP is vulnerable to infrastructure cyber-attacks that reduce the desired accuracy. IEEE 1588 defined an experimental security extension (Annex K) in order to protect a PTP network, but various drawbacks have been discovered, resulting in further improvements including the use of public-key encryption ( Itkin & Wool, 2020 ) and reduce the three-way handshake mechanism to one way authentication ( Onal & Kirrmann, 2012 ). Today Annex K is deprecated in favor of L2 / L3 security mechanisms. Further on, in 2020 a backwards compatible IEEE 1588 version (v2.1) will be introduced, that contains a new security extension called Annex S. Annex S consists of four prongs as follows ("IEEE Draft Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems," 2019): • Prong (A) PTP Integrated Security Mechanism describes an authentication type-length-value (TLV) that is aligned with and integrated into the PTP message. • Prong (B) PTP External Transport Security Mechanisms describes the current external security mechanisms that can be used to provide protection to PTP message i.e., IPsec and MACsec. • Prong (C) Architecture Guidance describes a redundant time system, redundant grandmaster, and redundant paths. • Prong D (Monitoring and Management Guidance) suggests monitoring the slaves’ synchronization process.

USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication

Abstract: This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm 2 , respectively, at a supply voltage of 1.8 V and total pin number of 38.

DeepNar: Robust Time-based Sub-meter Indoor Localization using Deep Learning

Abstract: We propose DeepNar, a deep learning-based indoor localization system that leverages WiFi signals time of flight (ToF) as environment features, to provide accurate and robust indoor localization. DeepNar leverages the fine-time measure¬ment (FTM) protocol in the recent IEEE 802.11-2016 standard to measure WiFi signal round trip time (RTT). Our system combines the advantages of fingerprinting and ranging-based techniques by providing a deep learning model along with a probabilistic framework that captures the complex relation between the propagation times of the WiFi signals heard by the mobile phone and its location. By leveraging the signals RTT, collected using commercial-off-the-shelf access points and mobile phones, DeepNar overcomes the different challenges of indoor environments such as the multipath interference, non-line-of-sight transmissions, signal attenuation, and interference. Moreover, DeepNar does not require clock synchronization between the transmitter and the receiver. Our system is composed of various components that handle outlier detection, avoids over-training, and accommodates heterogeneous devices. We implement and evaluate DeepNar over two testbeds. Our results show that DeepNar has a sub-meter localization accuracy with a median error less than 0.75m. This accuracy outperforms ranging-based multi-lateration technique by at least 182% and traditional signal strength (RSS) fingerprinting techniques by more than 119% and 33% in both testbeds considered.

Intra-Network Clock Synchronization for Wireless Networks: From State of the Art Systems to an Improved Solution

Abstract: Since the announcement of Industry 4.0 (I4.0), the concepts and ideas behind this revolution have been overturning. On the communication side however, all scenarios can be reduced to similar requirements. I4.0 communication requires real-time capability, reliability and interconnectivity of many clients. The realization of these requirements is already made possible by the IEEE standardized TSN technology. A key enabler for the realization of these requirements is a common time understanding of all involved instances, in order to coordinate the complexity arising in such a scenario. For this purpose, clock synchronization is an essential component of TSN. However, there is another essential feature that many I4.0 use cases have in common, which is the spatial dynamics of clients that only wireless communication can provide. This paper presents an approach based on WLAN, which is also able to meet these requirements. The essential points of clock synchronization as used in TSN are analyzed and transferred to WLAN and further concepts and optimizations will be introduced. These concepts are evaluated and analyzed in simulations. The result is a communication concept, which is able to exceed the performance of wired TSN as shown by various KPIs.

Synchronization and efficient channel hopping for power efficiency in LoRa networks: A comprehensive study

Abstract: The usage of Low-Power Wide Area Networks (LPWAN) is increasing rapidly in many sectors of Internet of Things (IoT) applications. Long Range (LoRa) Wide Area Network (LoRaWAN) is a LPWAN, which has a long-range, low-cost and acts as a connectivity enabler. Most of the applications with real-time requirements, need reliable communication. This can be achieved by sharing a common time base across the network. However, making an efficient collaborative service of clock synchronization in LoRaWAN is challenging due to a lack of time notion. In this paper, We comprehensively study different approaches and design considerations for synchronization and tackle two problems of effective robustness in a LoRaWAN network. First, current research typically focuses on the benefits of LoRaWAN but ignores the requirement of reliability. To tackle this problem, we introduce a novel time synchronization scheme for radically reducing the usage of existing Aloha type protocol that handles energy consumption and service quality. Second, we look into the security space of LoRaWAN network, i.e. channel selection scheme for the given spectrum. Several security attacks are possible in LoRaWAN because the entire spectrum space is not used, and the utilization of few channels are comparatively higher. To tackle this problem, we present a channel hopping scheme that integrates cryptographic channel selection with the time notion. Finally, we evaluate the proposed time synchronization and channel hopping scheme for a real-world deployed peer to peer (P2P) model using commodity hardware. This paper concludes by suggesting the strategic research possibilities on top of this platform.

Feasibility Study of UAV-Assisted Anti-Jamming Positioning

Abstract: As the cost and technical difficulty of jamming devices continue to decrease, jamming has become one of the major threats to positioning service. Unfortunately, most conventional technologies are vulnerable to jamming attacks due to their inherent shortcomings like weak signal strength and unfavorable anchor geometry. Thanks to the high operational flexibility, unmanned aerial vehicle (UAV) could fly close to users to enhance signal strength while maintaining a satisfactory geometry, making it a potential solution to the above challenges. In this article, we propose a UAV-assisted anti-jamming positioning system, in which multiple UAVs first utilize time-difference-of-arrival (TDoA) measurements from ground reference stations and double-response two-way ranging (DR-TWR) measurements from UAV-to-UAV links to perform self-localization as well as clock synchronization, and then act as anchor nodes to provide TDoA positioning service for ground users in the presence of jamming. To evaluate the feasibility and performance of the proposed system, we first derive the Cramer-Rao lower bound (CRLB) of UAV self-localization. Then, the impacts of UAV position uncertainty and synchronization errors caused by jamming on positioning service are modeled, and the theoretical root-mean-square error (RMSE) of user position estimate is further derived. Numerical results demonstrate that the proposed system is a promising alternative to existing positioning systems when their services are disrupted by jamming. The most notable advantage of the proposed system is that it is fully compatible with existing user equipment (UE) and positioning methods.

Recent Advances in Clock Synchronization for Packet-Switched Networks

Abstract: Speech enhancement is a core problem in audio signal processing with commercial applications in devices as diverse as mobile phones, conference call systems, smart assistants, and hearing aids. An essential component in the design of speech enhancement algorithms is acoustic source localization. Speaker localization is also directly applicable to many other audio related tasks, e.g., automated camera steering, teleconferencing systems, and robot audition. From a signal processing perspective, speaker localization is the task of mapping multichannel speech signals to 3-D source coordinates. To obtain viable solutions for this mapping, an accurate description of the source wave propagation captured by the respective acoustic channel is required. In fact, the acoustic channels can be considered as the spatial fingerprints characterizing the positions of each of the sources in a reverberant enclosure. These fingerprints represent complex reflection patterns stemming from the surfaces and objects characterizing the enclosure. Hence, they are Bracha Laufer-Goldshtein, Ronen Talmon and Sharon Gannot (2020), “Data-Driven Multi-Microphone Speaker Localization on Manifolds”, Foundations and Trends © in Signal Processing: Vol. 14, No. 1–2, pp 1–161. DOI: 10.1561/2000000098. Full text available at: http://dx.doi.org/10.1561/2000000098