Showing papers on "CMOS published in 1970"

Complementary metal oxide semiconductor gate protection diode

Abstract: Gate protection is given to a complementary metal oxide semiconductor (CMOS) devices against excessive input voltage transients. An input diode which has a lower breakdown voltage than the gate oxide is attached to the input terminal to protect the gate oxide. The input protect diode is formed by diffusing an N+ region which overlaps both a P tube and an N substrate. The diffusion concentrations between the various regions determine the breakdown voltage of the protection diode. The overlapping relationship of the N+ diffusion over the P- tub and N substrate creates a structure which prevents parasitic NPN action.

CMOS-bipolar monolithic integrated-circuit technology

Abstract: This paper describes a new integrated circuit process in which CMOS and bipolar integrated-circuit technologies have been monolithically mated without compromising the performance characteristics of either the bipolar or the CMOS devices. The approach taken has been the addition of the required steps for fabricating CMOS devices to the basic linear-integrated-circuit process. This approach results in the need for one additional photoresist step over the process used for linear integrated circuits with compensating MOS capacitors. The basic processing steps, including the ion-implantation technique used to form the p-wells for the NMOS devices, are presented and discussed. Typical characteristics of the bipolar and CMOS devices fabricated with this process are shown. An amplifier circuit using this process has been fabricated. PMOS input devices are used along with the bipolar devices that provide the functions of current mirrors and high-gain amplifiers. CMOS devices are used in an inverter output stage.

Integrated-circuit digital logic families IIIߞECL and MOS devices

Abstract: This final installment of a three-part article is devoted to emitter-coupled logic (ECL) devices as well as to metal oxide semiconductor (MOS) logic devices of the p-channel (P-MOS) and complementary (CMOS) types. The concluding portion presents a summary chart comparing the major parameters of the various IC digital families discussed in the three installments, plus a useful check list of available functions.

Complementary metal oxide semiconductor exclusive or gate

Abstract: A complementary metal oxide semiconductor (CMOS) exclusive OR gate is shown having a minimum number of devices for performing the exclusive OR function. The exclusive OR function is performed by utilizing the normal two input signals as logic indicating signals and generating a control signal which is a complement of one of the two logic signals. A different configuration results with the selection of the logic signal from which the control signal is to be generated. The capacitance of the output node or output signal is charged by any one of a plurality of current paths associated with each logic configuration.

Silicon gate CMOS integrated circuits

Abstract: The major advantages offered by silicon-gate CMOS technology have been applied to the fabrication of monolithic integrated circuits for micropower applications. Complementary n- and p-channel enhancement-mode devices fabricated with silicon gate in conjunction with a unique substrate preparation tech, nique have exhibited threshold voltages of 0.5 ± 0.2V. Drain-to-source leakage currents, as well as pot to substrate leakage current, are typically less than 1 nA at 3 V.

Parameter Extraction Scheme For Silicon PressureSensors In Standard CMOS Technology

Abstract: Forming a part of the CAD/CAE attempts to simulate and design microsystems, the process of parameter extraction for a pressure sensor macromodel from layout is presented. The pressure sensor was integrated on a silicon chip by means of a standard CMOS technology (1.0 urn from Atmel-European Silicon Structures) followed by micromechanical structuring of the device. A tool for analysing the physical layout of the sensor is also described. From the results, an electrical model of the sensor was obtained for use in conventional CAD tools.

A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

Abstract: This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64o phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20oC, +120oC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.