Showing papers on "CMOS published in 1971"

High performance, low power CMOS memories using silicon-on-sapphire technology

Abstract: Silicon-on-sapphire (SOS) technology allows the fabrication of complex MOS integrated circuits with high speed performance comparable to that of bipolar circuits but at the expense of only microwatts of quiescent power dissipation. The use of a 1 µm thick single crystal silicon films allows virtual elimination of the parasitic capacitance which seriously degrades the performance of bulk silicon MOS circuits. Complementary MOS/SOS integrated circuits fabricated with self-aligned silicon gate technology and 5 µm channel spacings make 2 nanosecond gate delays and 1 picojoule gate power x delay products possible at 5V operation. In addition to high switching speed and low dynamic power, CMOS/SOS circuits with low leakage currents and therefore low quiescent power can be fabricated. The reverse currents of vertical junction SOS diodes are due to electron-hole generation in the depletion layer and have the voltage dependence predicted by the Sah-Noyce-Shockley theory. Lifetimes on the order of 1 ns have been measured; however, the total junction leakage currents are small (50 pa/mil width at 5 V) due to the extremely small junction areas involved.

Apparatus for driving a light emitting diode of horologic display

Abstract: There is disclosed a logic and driving circuit for a light emitting diode type horologic display in which three diodes are read out at any given time to represent the time of day. Power consumption is kept to a minimum by the use of a two voltage level system with the lower voltage supplying those portions of the circuit working at a high frequency while the higher voltage supplies the display and those portions of the driving circuit operating at a considerably lower frequency. In addition to a crystal frequency standard and a ''''divide-by-two'''' flip-flop countdown circuit which provides a 1 Hz signal to a series of toggle flip-flop counting circuits which function as the seconds, minutes and hours storage elements, there is provided a multiplexer coupled to the outputs of these counting circuits which is strobed with pulses having a combined duration of only a fraction of the sampling cycle. This results in a low duty cycle for the output of the multiplexer and thus for the display itself which conserves on the power necessary to drive the display. Since hour, minute and second information is sequentially sampled by the multiplexing circuit, multiplexing eliminates decoder and driver redundancy. Provision is made in the multiplexing logic for dividing the horological display into quadrants or sectors so as to further reduce the number of driver and decoder elements. As a result there is also provided a quadrant selecting circuit. The sampling pulses for the multiplexing circuit are conveniently derived from the frequency standard countdown circuit. The driving system utilizes complementary metal oxide semiconductor (CMOS) components in which power drain is minimized because these elements draw appreciable power only when switching. A further power consumption advantage is obtained by utilizing NAND gate logic to permit the use of these low power CMOS components. Toggle flip-flops are chosen for the counters because they are available in metal oxide semiconductor form and because the total number of transistors utilized is reduced. The logic described herein is used with a horologic display in which the minutes and seconds are displayed in the single ring of elements with the hours being displayed in another single ring of elements.

The electronic wristwatch: An application for Si-gate CMOS ICs

Abstract: The micropower requirements for a quartz-crystal electronic watch readily lend themselves to Si-gate CMOS technology. The crux of the system, a 1.5-V, 50-nW/kHz, multiple-octave counter which operates up to 1 MHz, will be discussed.

Potential improvements in power-speed performance of digital circuits

Abstract: The characteristics of essentially zero standby power drain, reduced load capacitance, and lower supply voltage of a complementary metal-oxide-semiconductor (CMOS) digital circuit compared with a bipolar transistor circuit offer a potential advantage of 10 to 1000 times in power-speed product.

Transient analysis of modified t.t.l. gate

Abstract: The letter derives expressions for the transient response of the modified t.t.l. NAND/NOR gate using a piecewise linear analysis. The expressions are presented in a form suitable for incorporation into a computer-aided circuit-analysis program based on the macromodelling concept and intended for the analysis of relatively large arrays of integrated-circuit logic gates. Results are compared with experimental observations.

Design, development, fabrication and delivery of register and multiplexer units

Abstract: Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated The CMOS standard cell array technique was selected and implemented Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation One of the chip types, multiplexer register type 1, is fabricated on a 0143 x 0123 inch chip It uses nine standard cell types for a total of 54 standard cells This involves more than 350 transistors and has the functional equivalent of 111 gates The second chip, multiplexer register type 2, is housed on a 012 x 012 inch die It uses 13 standard cell types, for a total of 42 standard cells It contains more than 300 transistors, the functional equivalent of 112 gates All of the hermetically sealed units were initially screened for proper functional operation The static leakage and the dynamic leakage were measured Dynamic measurements were made and recorded At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1 At 5 V these units shifted data at a 66 MHz rate The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C