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Showing papers on "CMOS published in 1973"


Journal ArticleDOI
01 Dec 1973
TL;DR: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail.
Abstract: A novel circuit technique that has been applied to the world's first CMOS-LSI for a desktop calculator is described in detail. The CMOS-LSI includes 3300 elements and has a chip size of about 200 mil square, operates at 6 V supply voltage, and dissipates power of about 1 mW at a clock frequency of 50 kHz.

142 citations


Journal ArticleDOI
TL;DR: In this paper, the parasitic transistors and pnpn paths present on junction-isolated CMOS circuits have been identified and studied quantitatively and several techniques are proposed to eliminate radiation-induced latchup in future CMOS designs.
Abstract: The parasitic transistors and pnpn paths present on junction-isolated CMOS circuits have been identified and studied quantitatively. Active SCR structures exist which can be triggered electrically or by a radiation pulse. Detailed studies of SCR paths have been performed on two circuits, the CD4007A and the CD4041A, to relate geometrical and materials parameters to latch-up sensitivity. Both normal bias conditions and bias optimum for obtaining SCR action are employed. Several techniques are proposed to eliminate radiation-induced latchup in future CMOS designs.

104 citations


Patent
25 Jun 1973
TL;DR: In this paper, a cross-coupled gate with complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input is presented. But the coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over.
Abstract: Bistable digital circuits including cross coupled gates having complementary inputs provided by CMOS threshold circuits coupled to a common digital signal input. Complementary unbalanced transfer characteristics of the threshold circuits provide widely separated high and threshold voltages approaching respective high and low supply potentials. The coupling between gates maintains the bistable digital circuits in a given stable state until the high and low threshold voltages are crossed over in response to a change in logical level at the signal input.

36 citations


Journal ArticleDOI
TL;DR: In this article, the effects of ionization on MOS devices as a function of time after exposure to a radiation source are functions of the radiation source and device bias time profiles, supported by a comprehensive series of experiments.
Abstract: The effects of ionization on MOS devices as a function of time after exposure to a radiation source are functions of the radiation source and device bias time profiles. This paper presents a discussion, supported by a comprehensive series of experiments, of the time dependence of ionization-induced damage to complementary metal oxide semiconductor (CMOS) devices. Two distinct annealing or recovery mechanisms were investigated: (1) room temperature annealing in the absence of radiation, and (2) radiation enhanced room temperature annealing. Experiments were performed using both electron aid ?-ray sources with ionization rates ranging from 103 rads(Si)/sec to greater than 1011 rads(Si)/sec and observation times extending from 1 msec to 105 seconds. The experiments demonstrate that ionization-induced damage to positively biased MOS devices, such as the n-channel devices in CMOS circuits, can be annealed appreciably at room temperature by additional irradiation of the device with zero gate bias. Thus, when operation of CMOS circuitry during or immediately following radiation exposure is of interest, the experimental semipermanent-type radiation damage data typically reported must be carefully evaluated.

35 citations


Patent
Fillmore R1, Huener R1
24 Aug 1973
TL;DR: In this article, a complementary symmetry, metal oxide semiconductor device (COS/MOS) oscillator with a regenerative feedback path from the output to the input terminal of the inverter is presented.
Abstract: A complementary symmetry, metal oxide semiconductor device (COS/MOS) oscillator which includes a COS/MOS inverter and a regenerative feedback path from the output to the input terminal of the inverter. Power consumption is reduced, when current flow through the one device tends to increase, by applying regenerative feedback to an impedance in series with the other device to more quickly drive the other device to cut off, and vice versa. Degeneration across the impedances, when current flow therethrough tends to increase, also is employed to reduce power consumption.

30 citations


Patent
Jr Harry A Kuhn1
27 Sep 1973
TL;DR: The disclosed divider circuit as mentioned in this paper divides the repetition rate of an input signal by an odd integer to provide an output signal, which can be used to generate a small amount of chip area.
Abstract: The disclosed divider circuit divides the repetition rate of an input signal by an odd integer to provide an output signal. The divider includes at least four binary cells and either a NOR and a NAND gate. Each binary cell includes first and second inversely clocked transmission gates and first and second inverters. Selected output terminals of three of the binary cells are connected to the input terminals of the gate and the output terminal of the gate is connected to the input terminal of the fourth binary cell. The resulting circuit configuration lends itself to fabrication by CMOS processes and takes up only a small amount of chip area.

29 citations



Journal ArticleDOI
TL;DR: The radiation sensitivity of commercial and laboratory CMOS processes has been investigated in this paper, where failure levels for CMOS circuits have been related to transistor threshold voltage shifts and typical inverter failure modes.
Abstract: The radiation sensitivity of commercial and laboratory CMOS processes has been investigated. Failure levels for CMOS circuits have been related to transistor threshold voltage shifts and typical inverter failure modes. CMOS inverter characteristics have been measured as a function of the ionizing radiation exposure for devices fabricated by 10 different manufacturers and representing a total of 15 different processes. By selecting certain processes, CMOS circuits can be obtained which will operate after exposure to an ionizing radiation dose greater than 106 rads (Si).

25 citations


Journal ArticleDOI
TL;DR: Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure that is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.
Abstract: Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.

23 citations


Journal ArticleDOI
TL;DR: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts on a common technology base.
Abstract: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.

22 citations


Patent
22 Aug 1973
TL;DR: In this article, a complementary metal oxide semiconductor switch interconnected such that body voltages of both the P channel and N channel MOS devices are limited to one forward diode drop of their source and drain voltages, and results in a uniform threshold voltage and low uniform switch "on" resistance.
Abstract: A complementary metal oxide semiconductor switch interconnected such that body voltages of both the P channel and N channel MOS devices are limited to one forward diode drop of their source and drain voltages, and results in a uniform threshold voltage and low uniform switch "on" resistance.

Patent
12 Feb 1973
TL;DR: A CMOS dynamic division circuit employing only transmission gates and inverters minimizes the number of units required for any particular division, which then minimizes nodal capacitance for limiting power consumption.
Abstract: A CMOS dynamic division circuit employing only transmission gates and inverters minimizes the number of units required for any particular division, which then minimizes nodal capacitance for limiting power consumption. The circuit is particularly adapted for electronic watch circuits.

Patent
Harold Garth Nash1
26 Dec 1973
TL;DR: In this paper, a bipolar transistor is provided on a CMOS semiconductor chip in combination with an emitter follower resistor, A CMOS inverter, an input resistor and a feedback resistor.
Abstract: A bipolar transistor is provided on a CMOS semiconductor chip in combination with an emitter follower resistor, A CMOS inverter, an input resistor and a feedback resistor. The bipolar transistor and the emitter follower resistor are connected to form an emitter follower, which has its input connected to the output of the CMOS inverter. A high resistance feedback resistor is connected between the output of the emitter follower and the input of the CMOS inverter. A high value input resistor is connected between the input conductor of the operational amplifier and the input of the CMOS inverter.

Journal ArticleDOI
TL;DR: It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits.
Abstract: The performance of grounded load complementary MOS circuits has been evaluated. It has been found that a very significant improvement in performance and reduction in circuit-area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits.

Patent
Siegfried K. Wiedmann1
27 Feb 1973
TL;DR: In this article, a semiconductor cell operating on the flip-flop principle and in which the cross-coupled storage transistors and the load transistors are field effect and bipolar transistors, respectively.
Abstract: A semiconductor storage cell operating on the flip flop principle and in which the cross-coupled storage transistors and the load transistors are field effect and bipolar transistors, respectively. The semiconductor cell is a FET storage cell whose active storage transistors are field effect transistors which, in contrast to bipolar transistors, do not have to be isolated against each other, thus occupying a smaller semiconductor area. The bipolar load transistors permit a very low stand-by current on the order of the leakage current to be impressed, which in contrast to FET load elements can be changed to a desirably high operating current during reading. Apart from this, the bipolar transistors in the load branches need not be isolated against each other in this configuration, so that at a low rate of permanent power dissipation, which is roughly comparable to that of CMOS storages, the semiconductor cell area can be further reduced.

Proceedings ArticleDOI
J. Schoeff1
01 Jan 1973
TL;DR: In this paper, an IC which facilitates a two-chip measurement system by performing all of the analog functions of a.01% A/D conversion is discussed, and features include single-supply operation, low power, internal reference and CMOS/TTL compatibility.
Abstract: An IC which facilitates a two-chip measurement system by performing all of the analog functions of a .01% A/D conversion will be discussed. Features include single-supply operation, low power, internal reference and CMOS/TTL compatibility.

Patent
27 Dec 1973
TL;DR: In this paper, a crystal controlled oscillator providing two symmetrical out-of-phase outputs utilizes two silicon gate CMOS (complementary metal oxide silicon) field effect transistor inverter circuits with the frequency determining crystal connected across the inputs to the two inverters.
Abstract: A crystal controlled oscillator providing two symmetrical out-of-phase outputs utilizes two silicon gate CMOS (complementary metal oxide silicon) field-effect transistor inverter circuits with the frequency determining crystal connected across the inputs to the two inverters. The outputs of the two inverters are cross-coupled to the inputs to sustain oscillation, and the circuit provides stable crystal control of both of the output phases with excellent load isolation.

Journal ArticleDOI
TL;DR: A threshold gate circuit is presented which permits a large number of input weights with good noise margins and results of testing an experimental ten input model are given.
Abstract: A threshold gate circuit is presented which permits a large number of input weights with good noise margins. This is done by replacing the usual voltage detector with a current detector. Results of testing an experimental ten input model are given.

Journal ArticleDOI
TL;DR: In this article, an extension of the well-known self-registered gate PMOS technology for fabricating complementary MOS transistors is described, where the doped silane oxides as diffusion sources provide accurate and repeatable control of the n-channel threshold voltage.
Abstract: This paper describes an extension of the well-known self-registered gate PMOS technology for fabricating complementary MOS (CMOS) transistors. Exclusive usage of doped silane oxides as diffusion sources provides accurate and repeatable control of the n-channel-threshold voltage. The use of doped-oxide diffusion sources also makes possible a novel diffusion technique where the n- and p-channel source and drain diffusions can be performed simultaneously with independent control of sheet resistivity. This technique eliminates one high-temperature operation; at the same time, the doped-oxide diffusion sources can be deposited in such a manner as to allow their differing etch rates to provide favorable slopes on the edges of contact windows, a feature that increases yield and reliability. A description of the process is provided along with an electrical characterization of the devices fabricated using this process.