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Showing papers on "CMOS published in 1979"


Journal ArticleDOI
TL;DR: In this article, a voltage source that is proportional to absolute temperature (PTAT) was proposed. But the voltage source was not designed to operate down to 1.3 V with a current drain below 1 /spl mu/A.
Abstract: The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.

163 citations


Proceedings ArticleDOI
25 Jun 1979
TL;DR: In this article, a graph-theoretical algorithm which minimizes the size of an array of transistors is presented, based on a random logic function implemented on the transistors.
Abstract: This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented.

149 citations


Journal ArticleDOI
Bedrich Hosticka1
TL;DR: Techniques for improving the gain of MOS amplifiers are discussed and an experimental single stage amplifier was realized using CMOS transistor arrays which achieved gain of 3200.
Abstract: Techniques for improving the gain of MOS amplifiers are discussed. These techniques depend on technology used. An experimental single stage amplifier was realized using CMOS transistor arrays which achieved gain of 3200.

122 citations


Journal ArticleDOI
TL;DR: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter that may be interconnected in series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates.
Abstract: Standard process CMOS/SOS technology has been applied in the design of a 6 bit parallel 20 MHz A/D converter. Two chips may be interconnected in a series to obtain 7 bit resolution or in parallel to obtain nearly 40 MHz data rates. Design factors and accuracy requirements are reviewed.

121 citations


Patent
26 Dec 1979
TL;DR: In this paper, a calculator with constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups is presented, which enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or selectively connect in combination the first and second switched voltages.
Abstract: A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved Power consumption less than conventional CMOS is obtainable

114 citations


Patent
26 Dec 1979
TL;DR: In this paper, a calculator with constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability, and multiple partition power control of circuit groups is presented.
Abstract: A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal and external RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. In yet another embodiment, the clocked CMOS logic of the system is forced to a designer predefined output logic level in the inactive power down mode. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved. Power consumption less than conventional CMOS is obtainable.

102 citations


Journal ArticleDOI
TL;DR: A simple micropower CMOS bandgap voltage reference is described, which utilizes MOS devices operating in the weak inversion region in conjunction with a process compatible bipolar device.
Abstract: A simple micropower CMOS bandgap voltage reference is described. The reference utilizes MOS devices operating in the weak inversion region in conjunction with a process compatible bipolar device. The voltage reference is insensitive to threshold and mobility variations and is independent of the slope factor which characterizes weak inversion.

73 citations


Journal ArticleDOI
TL;DR: In this paper, a survey of latch-up control methods for VLSI-integrated CMOS is presented, and the extent of their applicability to VLSIs is discussed.
Abstract: The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (~9 ?m p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. This paper will survey latch-up control methods presently employed for weapons and space applications on present (~9 ?m p-well) CMOS and will indicate the extent of their applicability to VLSI designs.

58 citations


Journal ArticleDOI
TL;DR: In this article, three switched-capacitor circuits are described which perform all filtering functions in a PCM voice CODEC, which use novel integrators and/or state-variable sections, which desensitize the overall response against stray capacitance effects.
Abstract: Three switched-capacitor circuits are described which perform all filtering functions in a PCM voice CODEC. They use novel integrators and/or state-variable sections, which desensitize the overall response against stray-capacitance effects. All filters are fully integrated on a CMOS test chip. The basic design considerations and the measured performance are discussed.

52 citations


Journal ArticleDOI
TL;DR: In this paper, the long-term annealing of neutron irradiation induced changes in the parasitic bipolar gains of MOS/LSI integrated circuits is characterized, which fits both isothermal and isochronal AN data.
Abstract: Bulk silicon integrated circuits can exhibit latch-up effects which arise from regenerative switching in the parasitic bipolar transistors inherent in the complex circuit configurations. This is especially true for bulk CMOS integrated circuits in which parasitic vertical NPN and lateral PNP bipolars are connected in an SCR fashion. One method for preventing latch-up is lifetime control utilizing neutron irradiation. This work characterizes the long-term annealing of neutron irradiation induced changes in the parasitic bipolar gains of MOS/LSI integrated circuits. A theoretical model, which fits both isothermal and isochronal annealing data, is used to characterize the annealing. Using this model, a procedure has been established for neutron irradiation of LSI integrated circuits which will guarantee that latch-up will not occur during the normal lifetime of the circuits. A detailed discussion of the procedure employed for neutron irradiation of integrated circuits is given, and the results of this procedure applied to several thousand MSI and LSI circuits are described.

44 citations


Patent
03 Oct 1979
TL;DR: In this paper, an improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor.
Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process, modified to include a P-channel transistor. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. Field oxide is grown after the N-type tank is formed. A polycrystalline silicon layer is deposited and patterned to create gates for both N- and P-channel transistors, then separately masked P- and N-type diffusions or implants form the sources and drains for the two types of transistors.

Journal ArticleDOI
TL;DR: A novel technique based on a special algorithm in which the capacitor array is used as a precision voltage divider is developed and a capacitor array tester consisting of both hardware and software has been built which executes this algorithm.
Abstract: The recent development of integrated circuit capacitor arrays and the growth of their applications have resulted in a need to perform precision testing as an aid to future design improvements. For reasons discussed in this paper, laboratory instruments such as capacitance bridges are not well-suited to this need. In order to test capacitor arrays accurately, a novel technique has been developed. It is based on a special algorithm in which the capacitor array is used as a precision voltage divider. A capacitor array tester consisting of both hardware and software has been built which executes this algorithm. This system has been used to perform measurements upon a large number (thousands) of NMOS and CMOS capacitor arrays. The standard deviation of this tester's measurement error is approximately 0.0009 percent of full scale (0.0088 LSB referenced to 10 bits). In contrast with manual testing with a capacitance bridge (requiring 10 min per array), the tester requires less than 5 s to fully test an array, mark the circuit and move to the next die position.

Proceedings Article
01 Sep 1979
TL;DR: In this article, a voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates, and the voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V.
Abstract: A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.

Patent
02 Jul 1979
TL;DR: In this paper, a CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power, including a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt.
Abstract: A CMOS power on reset circuit is provided which operates with low power supply voltages and yet uses a minimum amount of DC power The circuit includes a threshold detector which provides an output when the power supply voltage exceeds the transistor threshold voltage by approximately half a volt A capacitor is connected to the positive power supply terminal to avoid having a narrow output pulse when the power supply rises at a low rate An output buffer/inverter can be used to provide a better output pulse and to provide a desired output polarity

Journal ArticleDOI
TL;DR: The sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values as discussed by the authors, hence, CMOS is less sensitive than e.g., PMOS.
Abstract: Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against comsic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are, in general agreement with previous spacecraft flight data.

Journal ArticleDOI
TL;DR: In this article, the initial results of a Navy program for the evaluation and design of solid-state electronics to be operated uncooled in aircraft-engine control applications were reported.
Abstract: Extensive characterizations of discrete devices and integrated circuits are reported over the temperature range from room temperature to 250°C and 300°C. These are the initial results of a Navy program for the evaluation and design of solid-state electronics to be operated uncooled in aircraft-engine control applications. Based on these results and results from earlier investigations, discrete semiconductor devices of essentially all generic types function with usable characteristics at junction temperatures up to at least 300°C. First-order device parameter changes result from increased leakage, reduced mobility, and increased resistivity. Both analog and digital integrated circuits were found to exhibit dc as well as useful dynamic characteristics up to temperatures near 250°C. Bipolar circuits with either junction or dielectric isolation degrade due to changes in device operating points and high leakage currents. In analog circuits the temperature capabiity is found to depend critically on the specific circuit design implemented. For a variety of CMOS devices tested a pnpn latchup mechanism between the p-channel transistor and the input protection network limits useful device operation to 260°C. Changes in device and circuit layout are needed to circumvent this failure mode. No fundamental barrier to 300°C functionality of integrated circuits (designed specifically for high-temperature application) was found.

Patent
08 Nov 1979
TL;DR: In this article, a method of forming combination CMOS field effect transistors optionally with a charge transfer device in a single substrate is presented, where different resistivities in the P type wells of the substrate are formed by a combination of masks; a high energy low dosage ion implantation of impurity passes through one mask but not the other.
Abstract: A method of forming combination CMOS field effect transistors optionally with a charge transfer device in a single substrate. Different resistivities in the P type wells of the substrate are formed by a combination of masks; a high energy low dosage ion implantation of impurity passes through one mask but not the other, and a low energy high dosage ion implantation of the impurity is stopped by both masks. A significant number of fabrication steps is thus saved, and the devices so fabricated are threshold and field voltage compatible.

Journal ArticleDOI
TL;DR: In this paper, a fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems, and the mask count is 6 for structure definition plus 2 for the masking of implants.
Abstract: A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

Journal ArticleDOI
TL;DR: Using voltage inverter switches, exact analog sampled-data equivalents of Rs, Ls and Cs, as well as unit elements, can be designed with MOS capacitors and switches, which allows low power switched capacitor filters without operational amplifiers and with a frequency capability approaching the megahertz range.
Abstract: Using voltage inverter switches, exact analog sampled-data equivalents of Rs, Ls and Cs, as well as unit elements, can be designed with MOS capacitors and switches. Due to the underlying bilinear transformation, no limitation other than the Nyquist limit is imposed on the ratio of corner to sampling frequency. For an nth order filter, the number of voltage inverter switches is (n+1)/4 to (n+1)/2. A 3.4 kHz third-order Chebyshev low-pass CMOS circuit is described in detail. It uses only one voltage inverter switch implemented by a switched op amp integrator. The sampling frequency is 24 kHz, the dynamic range exceeds 70 dB and the chip area is 1.2 mm/SUP 2/. A CMOS voltage inverter switch, which has zero DC power and occupies only 0.09 mm/SUP 2/ is presented, whose dynamic range exceeds 85 dB. This allows low power switched capacitor filters without operational amplifiers and with a frequency capability approaching the megahertz range.

Patent
02 Apr 1979
TL;DR: In this paper, a CMOS Schmitt trigger circuit displays a lower trigger point that is one N channel transistor threshold above the negative power supply potential and an upper trigger point, which is one P channel threshold below the positive power supply maximum potential.
Abstract: A CMOS Schmitt trigger circuit displays a lower trigger point that is one N channel transistor threshold above the negative power supply potential and an upper trigger point that is one P channel transistor threshold below the positive power supply potential. Thus, the circuit hysteresis loop is related to supply potential and device threshold values. When the trigger circuit is employed in a relaxation oscillator configuration, the oscillator frequency is independent of power supply voltage and manufacturing variables in the CMOS process that vary transistor threshold values.

Patent
11 Oct 1979
TL;DR: In this paper, an improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects.
Abstract: An improved CMOS device and method of making it are provided which utilize basically the standard N-channel self-aligned silicon gate structure and process (with implants for self-alignment), modified to include P-channel transistors and to allow three levels of interconnects. A P-type substrate is used as the starting material, with an N-type tank formed for the P-channel transistor. The source and drain regions, N+ or P+, are defined prior to the polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

Journal ArticleDOI
01 Oct 1979
TL;DR: A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/ SUP 2/) cells based on 5 /splmu/m design rules.
Abstract: A new CMOS/SOS `buried-contact' process allows fabrication of dense static memory cells. The technology is applied in a 16K RAM with 1150 /spl mu/m/SUP 2/ (1.78 mil/SUP 2/) cells based on 5 /spl mu/m design rules.

Journal ArticleDOI
TL;DR: The concept of switched capacitors, originally introduced to implement integrated active filters can be applied to the realization of pseudo-RC oscillators as well if the power consumption has to be minimized.
Abstract: A CMOS sinusoidal integrated oscillator based on a switched-capacitor third-order phase-shift network is described. Frequency is proportional to that of a clock, but may be controlled by a voltage. Accuracy is a few percent for a power consumption below 0.1 /spl mu/W in the audio range.

Journal ArticleDOI
TL;DR: A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip.
Abstract: A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.

Patent
13 Nov 1979
TL;DR: In this article, a detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detectors on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors.
Abstract: A detection circuit particularly adapted as a smoke detector employs a minimum number of components by a CMOS integrated circuit which receives directly the output of a smoke detector on one of the inputs of an input comparator circuit which provides static input protection and a high input impedance by employing thick oxide layer over the gates of the comparator transistors. The CMOS chip also directly supplies operating current for a mechanical or piezoelectric horn. Further features include a clocked low voltage alarm; a buffer stage to permit the interconnection of a number of different detector circuits in common to a single input/output lead; and a visual LED indicator to indicate that the circuit is operating and to provide a visual indication any time the alarm condition for the circuit has been actuated.

Patent
19 Dec 1979
TL;DR: A reference voltage source implemented in silicon-gate CMOS transistor technology comprises a pair of reference transistors of the same conductivity type, the gates of which are made of polycrystalline silicon and differ from each other by the type of doping.
Abstract: A reference voltage source implemented in silicon-gate CMOS transistor technology comprises a pair of reference transistors of the same conductivity type, the gates of which are made of polycrystalline silicon and differ from each other by the type of doping. The reference voltage can be temperature-compensated by adding an auxiliary compensation voltage source or by establishing a predetermined ratio of current densities in the pair of reference transistors operating in weak inversion.

Patent
25 May 1979
TL;DR: In this paper, a switching circuit controlled by the approach of a body into close proximity to its probe and operative to control the flow of power from an AC source to a load using a silicon control switching device enabled by an oscillator generating narrow gate pulses whenever the oscillator is in turn enabled by a flip-flop.
Abstract: A switching circuit controlled by the approach of a body into close proximity to its probe and operative to control the flow of power from an AC source to a load using a silicon control switching device enabled by an oscillator generating narrow gate pulses whenever the oscillator is in turn enabled by a flip-flop, which disables the oscillator in its first stable state and which enables the oscillator in its second stable state. Ambient electrical signals picked up by the probe are shaped into suitable form for triggering the flip-flop from one to the other of said stable states, and the shaping circuitry and the flip-flop comprise CMOS integrated circuits which are used for the purpose of achieving very low current drain and high sensitivity to an increase in ambient signals picked up at the probe, means being provided to adjust threshold sensitivities of the shaping circuit.

Patent
13 Aug 1979
TL;DR: In this article, the ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs.
Abstract: The ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs. By further addition of a NAND or a NOR gate the circuit can be used in an integrated circuit as option releasing stage without additional terminal for the option signal which has only to be chosen as the middle value of the ternary signal whereas its lower and upper values are the binary signals.

Proceedings ArticleDOI
01 Jan 1979
TL;DR: Low power, standard CMOS/SOS LSI technology, applied to a 6b (expandable to 7b) video speed A/D converter design, will be reported.
Abstract: Low power, standard CMOS/SOS LSI technology, applied to a 6b (expandable to 7b) video speed A/D converter design, will be reported. Applications and potential VLSI digital signal processing systems will be reviewed.

Journal ArticleDOI
TL;DR: The authors describe high-performance CMOS LSIs for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fouriertransform (DFT), and digital phase-locked loop (DPLL), for communication use.
Abstract: The authors describe high-performance CMOS LSIs for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL), for communication use. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time and power delay product.