Showing papers on "CMOS published in 1980"

Dynamic CMOS amplifiers

Abstract: A family of dynamic CMOS amplifiers is presented and discussed. First, the concept of dynamic circuit is introduced. Then two groups of circuits with different biasing principles are shown, and experimental results are presented. The advantages of dynamic amplifiers are low power consumption, high voltage gain, large bandwidth, and low offset voltages.

A high performance low power CMOS channel filter

Abstract: A new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented.

Twin-tub CMOS - A technology for VLSI circuits

Abstract: CMOS technology has been developed through several generations of design rules with an n-type substrate (where p-channel transistors were formed) and with a p-tub implanted and diffused region (where n-channel transistors were formed). In order to enable a separate optimization of both transistors and to utilize the dopant control available with implanted layers, a two-tub approach was adopted. Utilizing lightly doped epi on an n+substrate (for latch-up protection), nitride-masked self-aligned tubs, 1016cm-3surface doping and 600A gate oxides, an 8-mask CMOS process (named 'Twin-Tub") was formulated. The combination of n on n+epi and careful I/O layout renders the circuits latch-up free. Novel aspects of the process, the devices it produces and finally the resultant circuit performance are herein described.

MOS voltage reference based on polysilicon gate work function difference

Abstract: A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.

Address decode system

Abstract: An address decode scheme decodes address lines using a minimum number of electrical conductors and minimum area on the chip. Instead of decoding the true and the complementary signals of each address input using a PLA or static gate, the present decode scheme uses two sets of programmable transistors for respectively detecting zeros and ones on the address lines and for generating selected high and low decode signals in conjunction with precharge, discharge, and control transistors. This invention is equally effective in CMOS, NMOS, or PMOS technologies.

Silicon-gate n-well CMOS process by full ion-implantation technology

Abstract: A silicon-gate n-well CMOS process for an application of digital circuits operated by TTL compatible supply voltage was developed. Full ion-implantation technology, a new photolithography technique, n+-doped polysilicon gate which contain no boron impurities, and thin gate oxide of 65 nm can realize CMOS circuits of 2-µm gate length. Average impurity concentrations measured from substrate bias effect of MOSFET's and junction depth are in good agreement with those expected from impurity profiles calculated by a simple diffusion theory. So, the process design for CMOS circuits operated by any supply voltage is possible, by adjusting threshold voltages. The process can easily be extended to n-MOS/CMOS process (E/D MOS and CMOS on the same chip), if a photomask to fabricate depletion-type n-MOSFET's is provided.

Latch-Up Elimination in Bulk CMOS LSI Circuits

Abstract: Inherent in the structure of bulk CMOS integrated circuits are four-layer parasitic paths that can become activated into a low impedance, high-current state, i.e., latch-up. Activation can be accomplished by photocurrents generated by ionizing radiation or by terminal over-voltage spikes. As loss of functionality or device destruction can result, latch-up is undesirable. This paper describes a method of latchup prevention by the use of n on n+ starting material. A graphical analysis is presented that aids in the understanding of the latch-up mechanism and provides insight into the elimination of that state. Experimental data in support of the model is presented.

Performance of Digital Integrated Circuit Technologies at Very High Temperatures

Abstract: Results of detailed investigations of the performance and reliability of digital bipolar and complementary metal-oxide-semiconductor (CMOS) integrated circuits over the 25-340°C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results from experimental simulations of dielectrically isolated CMOS are also discussed. In general, it was found that commercial Schottky-clamped transistor-transistor logic (TTL) and dielectrically isolated, low power Schottky-clamped TTL functioned to junction temperatures in excess of 325°C. Standard gold-doped TTL functioned only to 250°C, while commercial isolated integrated injection logic (l2L) functioned to the range of 250-275°C. Commercial junction-isolated CMOS, buffered and unbuffered, functioned to the range of 280-310+°C, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340°C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious lifelimiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated circuits at temperatures in excess of 300°C has been found.

Use of silicide to bridge unwanted polycrystalline silicon P-N junction

Abstract: Polysilicon lines are utilized for interconnecting the various elements of CMOS devices. The polysilicon lines are doped with whatever dopant conveniently suits the processing step, to form an undesired PN junction. The junction is electrically short-circuited, preferably by a polysilicided section extending across the junction.

Fabrication of complementary bipolar transistors and CMOS devices with poly gates

Abstract: Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P + and N + emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Abstract: Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.

Voltage reference circuit

Abstract: A voltage reference source is provided which is temperature stable and can be made by standard CMOS processes. The voltage reference can provide an output voltage which is equal to twice the bandgap voltage. The voltage reference circuit uses a differential amplifier which has an output coupled to an additional amplifying stage. Two substrate bipolar transistors are used wherein the emitter current density of one of the transistors is larger than the emitter current density of the other transistor. An additional transistor is inserted between the output of the amplifying stage and the substrate bipolar transistors thereby providing the output voltage of twice the bandgap voltage.

Memory protection arrangement

Abstract: A memory protection arrangement particularly suitable for use with battery backed-up CMOS RAMs The voltage level of power to the CMOS RAMs is referenced to the logic supply to eliminate latch-up and low voltage problems and to relax the tolerances required in power supply circuits In addition, the master chip enable for all CMOS RAMs is latched rather than providing a separate latch for individual chip enable Furthermore, the state of the logic supply is latched at the beginning of each memory cycle to prevent disabling of the CMOS RAMs during a cycle An additional voltage sensor controls the enable of a buffer for each chip enable

Submicrometer polysilicon gate CMOS/SOS technology

Abstract: A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.

Non-volatile semiconductor memory cells

Abstract: Non-volatile bistable semiconductor latches having a pair of cross-coupled branches, each branch having a complementary driver or load and a driver connected in series at a respective node; at least one of the complementary drivers or loads, or drivers, includes a non-volatile IGFET having a variable threshold voltage (e.g. a FATMOS), said latch additionally including one or more buffer transistors (e.g. P-channel IGFETS) connected between one or both nodes and a latch output line. The buffer transistors increase the predictability of the state of the latch during power-on in a non-volatile mode of operation. Preferably the complementary drivers or loads, and the drivers, are constructed in CMOS or N-channel MOS. The buffers can drive a single DATA output line of twin DATA, DATA lines in a push-pull configuration.

Self-aligned all-n+ polysilicon CMOS process

Abstract: Disclosed is a process for forming self-aligned all n + -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n + dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.

CMOS Latch-up protection circuit

Abstract: A protection circuit for bulk-silicon CMOS circuits detects the latch-up of parasitic SCR devices, current starves the CMOS circuit in response to detecting a SCR latch-up condition and reenables normal circuit operation once the latch-up condition has been terminated.

A dense gate matrix layout style for MOS LSI

Abstract: This paper will discuss a layout style - gate matrix - for CMOS VLSI in the polysilicon gate technology. Approach, simplifying and unifying layout procedure by using an orderly structure, a matrix, characterized by rows of polysilicon and columns of diffusion, has been tested in a 20,000- transistor layout.

Method of manufacturing bulk CMOS integrated circuits

Abstract: The method presented may be utilized in manufacturing CMOS integrated circuits either in an isoplanar or in a LOCOS process. The method entails the simultaneous formation of the well region with the oxide isolation regions by a drive-in diffusion which is conducted in a dry oxygen ambient. The utilization of the process insures that compounds of silicon, nitrogen and oxygen will not be present in the bulk silicon where they can effect the quality of gate oxides which are subsequently formed.

An 8Kx8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

Abstract: A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.

Adaptable nonlinear transmission line terminator

Abstract: A nonlinear transmission line terminator terminates a transmission line having an input from any one of a plurality of logic types. Emitter coupled logic (ECL), transistor logic (TTL), Schottky transistor logic (STTL), low power Schottky transistor transistor logic (LSTTL), complementary MOS (CMOS) and the like are accommodated by impressing the voltage representing a "0" of the logic circuitry being accommodated on one reference terminal and the corresponding "1" voltage on another reference terminal. The terminator presents a very high impedance when the input signal from the transmission line is of an amplitude falling within the "0" and "1" voltage range. When the input signal falls outside the voltage range, the impedance of the terminator matches that of the transmission line to reduce line reflections by providing a path for current to flow from the transmission line to the appropriate one of the "1" or "0" reference terminals. The terminator further has constant current circuitry for maintaining the current flow at or below a predetermined level irrespective of the amplitude of the input voltage signal.

CMOS Reset circuit

Abstract: A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.

A synchronous switched capacitor filter [CMOS Si-gate implementation]

Abstract: A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experimental circuit has been implemented in CMOS Si-gate technology with a programmable gain of 20 dB and 40 dB, corresponding to a Q factor of 8.6 and 79, respectively. Experimental results are in good agreement with the theory. Modifications of the basic circuit are proposed to cancel the effects of parasitic capacitances and to reduce the chip area.

Low-voltage single supply CMOS electrically erasable read-only memory

Abstract: A low-voltage single supply CMOS electrically erasable read-only memory (CMOS-EEROM) is described. It combines long-term charge retention and the possibility of being read, written, and erased from a single power supply. Negative write and erase voltages are generated on-chip by voltage multipliers. It is shown that writing by avalanche injection and erasing by Fowler-Nordheim emission, are compatible with the low power output associated with these multipliers. In order to reduce the programming voltages below 40 V, injection oxide thickness is locally reduced by one additional photolithographic step compared to conventional silicon-gate CMOS technology. The influence of this oxide thickness and of polysilicon doping on write and erase characteristics, endurance, and charge retention are analyzed.

Micropower IC

Abstract: Various aspects of the realization of micropower LSI circuits are discussed, from the requirements on CMOS technologies to constraints on systems. Available passive and active devices are reviewed, with emphasis on DC, AC and noise characteristics of transistors at very low currents. Problems and solutions encountered in digital and analog circuits are illustrated with a few examples.

Cmos schmitt-trigger circuit

Abstract: A CMOS Schmitt-trigger circuit for shaping the wave form of an input signal to be applied to logic circuits, such as flip-flops, counters, etc. The CMOS Schmitt-trigger circuit has an input terminal connected to a signal source, and comprises a first CMOS inverter, a second CMOS inverter connected in cascade to the first CMOS inverter, a third CMOS inverter connected in cascade to the second CMOS inverter, and a feedback resistance connected between the output end of the third CMOS inverter and the input end of the second CMOS inverter. The schmitt width of the CMOS Schmitt inverter according to the present invention has less dependency on the impedance of the input signal source than the prior-art devices do.