Showing papers on "CMOS published in 1983"

A precision curvature-compensated CMOS bandgap reference

Abstract: A precision curvature-compensated switched-capacitor bandgap reference is described which uses a standard digital CMOS process and achieves temperature stability significantly lower than has previously been reported for CMOS circuits. The theoretically achievable temperature coefficient approaches 10 ppm//spl deg/C over the commercial temperature range and uses a straightforward room temperature trim procedure. Experimental data from monolithic prototype samples are presented which are consistent with theoretical predictions. The experimental prototype circuit occupies 3500 mil/SUP 2/ and dissipates 12 mW with /spl plusmn/5 V power supplies. The proposed reference is believed to be suited for use in monolithic data acquisition systems with resolutions of 10 to 12 bits.

NORA: a racefree dynamic CMOS technique for pipelined logic structures

Abstract: Describes a new dynamic CMOS technique which is fully racefree, yet has high logic flexibility. The circuits operate racefree from two clocks /spl phi/ and /spl phi/~ regardless of their overlap time. In contrast to the critical clock skew specification in the conventional CMOS pipelined circuits, the proposed technique imposes no restriction to the amount of clock skew. The main building blocks of the NORA technique are dynamic CMOS and C/SUP 2/MOS logic functions. Static CMOS functions can also be employed. Logic composition rules to mix dynamic CMOS, C/SUP 2/MOS, and conventional CMOS will be presented. Different from Domino technique, logic inversion is also provided. This means higher logic flexibility and less transistors for the same function. The effects of charge redistribution, noise margin, and leakage in the dynamic CMOS blocks are also analyzed. Experimental results show the feasibility of the principles discussed.

Fully integrated active RC filters in MOS technology

Abstract: A fully integrated continuous-time low-pass filter has been fabricated with CMOS technology. The device implements an active RC network using integrated capacitors and MOS transistors operated in the nonsaturation region as voltage-controlled resistors. The filter topology is fully balanced for good linearity and for good power supply rejection. The cutoff frequency is voltage adjustable around 3 kHz, allowing compensation for process and temperature variations. For 5-V power supplies a dynamic range of over 94 dB has been achieved.

MOS transistors operated in the lateral bipolar mode and their application in CMOS technology

Abstract: Operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively. It yields a good bipolar transistor that is fully compatible with any bulk CMOS technology. Experimental results show that high /spl beta/-gain can be achieved and that matching and 1/f noise properties are much better than in MOS operation. Examples of experimental circuits in CMOS technology illustrate the major advantages that this device offers. A multiple current mirror achieves higher accuracy, especially at low currents. An operational transconductance amplifier has an equivalent input noise density below 0.1 /spl mu/V//spl radic/Hz for frequencies as low as 1 Hz and a total current of 10 /spl mu/A. A bandgap reference yields a voltage stable within 3 mV from -40 to +80/spl deg/C after digital adjustment at ambient temperature. Other possible applications are suggested.

High-frequency CMOS switched-capacitor filters for communications application

Abstract: Bandpass filters for communications applications are realized using an 80 MHz differential single-stage CMOS operational amplifier and a fully differential identical-resonator elliptic bandpass ladder filter configuration. Experimental results are given for a CMOS sixth-order 260 kHz elliptic bandpass filter with a Q-factor of 40, a clock frequency of 4 MHz, and a power dissipation of 70 mW.

CMOS current comparator circuit

Abstract: A CMOS current comparator circuit design is presented and its simulated performance described. A comparator circuit designed to detect the presence of, for example, 5 ?A realised in a standard polysilicon-gate CMOS process technology exhibits a simulated propagation delay of about 10 ns.

Testing for Bridging Faults (Shorts) in CMOS Circuits

Abstract: The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

On Fault Detection in CMOS Logic Networks

Abstract: This paper considers the problem of detecting faults in CMOS combinational networks. Effects of open and short faults in CMOS networks are analyzed. It is shown that the test sequence must be properly organized if the effects of all open faults are to be observable at the network output terminal. A simple and efficient heuristic method for organizing the test sequence to detect all single faults in a CMOS network is suggested.

A transient analysis of latchup in bulk CMOS

Abstract: This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.

Three-dimensional CMOS IC's Fabricated by using beam recrystallization

Abstract: A three-dimensional (3-D) CMOS integrated circuit with a structure, in which one type of transistor is fabricated directly above a transistor of the opposite type with separate gates and an insulator in between, has successfully been fabricated by using laser beam recrystallization. Seven-stage ring oscillators fabricated in the 3-D structure have a propagation delay of 8.2 ns. In the present experiment, a double-layer of silicon-nitride and phospho-silicate-glass (PSG) film has been used as an intermediate insulating layer between the top and the bottom devices. This CMOS structure and the process technology we have developed here can be the basis for realizing a multilayered 3-D device composed of vertically stacked transistors with separate gates and an insulating layer in between.

Epitaxial layer enhancement of n-well guard rings for CMOS circuits

Abstract: n-well guard rings have long been used for isolating potential electron injectors to avoid latch-up of CMOS circuits. Such guard rings are shown to be orders of magnitude more efficient for CMOS fabricated in an epitaxial layer (epi-CMOS) than for bulk (non-epi) CMOS. The maximum escape probability in epi-CMOS measures 3.9E-06 while for bulk CMOS it is 1.8E-02.

Impact of Scaling on MOS Analog Performance

Abstract: A first-order analysis of the impact of scaling on MOS analog performance under moderate scaling conditions is presented in this paper. Assuming a polysilicon gate ion-implanted MOS technology, quasi-constant voltage (QCV) scaling is shown to be the optimal scaling law, offering the best overall analog performance and resulting in an increase in functional density, gain-bandwidth product with a moderate degradation in gain, and signal-to-noise ratio. The first-order analysis agrees fairly well with computer simulation. A typical case study shows that under moderate scaling conditions, CMOS can generally offer a higher voltage gain when compared to depletion load NMOS and is the preferred technology for scaled analog implementations.

Process for forming complementary integrated circuit devices

Abstract: A process for forming chanstops in complementary transistor integrated circuit devices which involves only a single extra masking step yet permits close control of the doping in the chanstops. The process is advantageously used starting with a twin-tub structure for forming CMOS integrated circuit devices.

A 64Kb full CMOS RAM with divided word line structure

Abstract: An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.

High frequency CMOS switched capacitor filters for communication applications

Abstract: Bandpass filters for communications applications using an 80MHz differential single-stage CMOS opamp and a fully differential idential-resonator elliptic bandpass ladder filter configuration will be reported. Experimental results from a CMOS sixth order 260kHz elliptic bandpass filter with Q of 40, clock frequency of 4MHz and power dissipation of 120mW, will be presented.

A CMOS magnetic field sensor

Abstract: The authors present a novel, fully integrated magnetic field sensor made in the standard, polysilicon-gate CMOS technology. The circuit shows a sensitivity of 1.2 V/T with 10 V supply voltage and 100 /spl mu/A current consumption. The circuit consists of a pair of split-drain MOS transistors in a CMOS-differential amplifier-like configuration.

CMOS on buried nitride—A VLSI SOI technology

Abstract: A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.

DC holding and dynamic triggering characteristics of bulk CMOS latchup

Abstract: Improved models for bulk CMOS latchup holding and triggering characteristics are developed and verified experimentally in this work. The roles of collector and base branch resistances are shown to lead to an accurate model for the minimum voltage to sustain latchup, and to an improved understanding of strong versus weak layouts, respectively. New measurement techniques for model parameters are described and used to test the dc model. Latchup triggering by base region (substrate or well) lateral currents is considered in some detail, It is shown that both threshold current levels and minimum turn-on times exist, below which latchup will not occur. Supporting experimental evidence is presented for all of the models.

CMOS circuit optimization

Abstract: In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint The propagation delay time for a CMOS in erter is calculated for a step function input A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction

Latchup in CMOS Devices from Heavy Ions

Abstract: Complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four layer n-p-n-p structures formed from the parasitic pnp and npn transistors comprise a silicon controlled rectifier (SCR) which, if properly biased, may be triggered "ON" by electrical transients, ionizing radiation or a single heavy ion. This latchup phenomenon might cause loss of functionality or device burnout. For space applications cosmic ray heavy ions are a significant threat and the latchup of a CMOS circuit is a major system concern because of its catastrophic nature. This paper presents the results of testing nineteen different device types from six manufacturers to investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths have been generally identified, and a qualitative rationale for latchup susceptibility and a latchup cross section is given for each device type. The correlation between bit-flip sensitivity and latchup susceptibility is also presented.

Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices

Abstract: N-channel MOS transistors used in nMOS and in CMOS microelectronic circuits have a drain-to-source breakdown characteristic showing a negative resistance region. Activating this mode of operation leads to a drop in source-to-drain voltage and to a large drain current. Snap-back is not a four-layer (SCR, latch-up) phenomenon, but, like latch-up, can be initiated by current injection into the p-well, by avalanching junctions or by exposure to ionizing radiation. The sustaining voltage can be significantly below the drain-substrate avalanche voltage thereby limiting the maximum operating voltage. In this paper we present a qualitative model for snapback--local conductivity modulation occurring in the intrinsic base region of the parasitic bipolar transistor leading to regenerative feedback. Effects of process variations on the snap-back characteristics are presented as are triggering sensitivities to ionizing radiation.

A 16K CMOS PROM with polysilicon fusible links

Abstract: A 16K synchronous CMOS PROM with polysilicon fusible links and a 2K-word by 8-bit organization is described. The memory cell makes use of the vertical bipolar NPN that is inherent in the p-well CMOS process. An advanced polysilicon fuse process is used for the fusible links. The technology incorporates use of an epitaxial layer that eliminates latchup potential at programming voltages. A special verify mode is used to detect marginally blown fuses during programming. The design features a typical access time of 50 ns and 1-/spl mu/A standby current.

Latchup-free Schottky-barrier CMOS

Abstract: A common failure mechanism in bulk CMOS integrated circuits is due to the latchup of the parasitic SCR structure. Using Schottky-barrier junctions for the source and drain of the p-channel transistors eliminates the p-n-p-n structure. A technology utilizing platinum-silicide p-channel source and drain and ion-implanted n-channel source and drain was realized demonstrating latchup resistance without many sacrifices inherent with other methods. Anomalies in the p-MOSFET characteristics are reported and discussed.

Self-aligned stacked CMOS

Abstract: A CMOS device configuration in which a complete CMOS inverter is contained in the space normally required for a single NMOS transistor of equivalent geometry. A first polysilicon layer of normal thickness and N+ doping is used for the N channel gate, and a second polysilicon layer is deposited conformally over the oxide which encapsulates the first polysilicon layer. The second polysilicon layer is thin and doped p-type. The second layer is only lightly doped initially, and is then doped more heavily by a low-energy implantation. The portions of the second poly layer which are adjacent to the sidewalls of the gate level in first poly will be shielded from the heavy implantation, and will therefore provide relatively lightly doped p-type channel regions, to form a pair of PMOS polysilicon transistors addressed by the N+ first poly gate electrode. Preferably the channel doping of these polysilicon transistors is at least 10 17 . Silicide strapping is optionally used on the remainder of the second poly level to improve its conductivity.

Circuit techniques for a VLSI memory

Abstract: This paper describes circuit techniques necessary for dynamic RAMs with high-packing density to implement submicron device technology. An on-chip error checking and correcting technique using bidirectional parity checking is proposed to reduce the soft error rate. In a sense-refresh amplifier, capacitor-coupled presenting is introduced to compensate for threshold imbalance. An on-chip supply voltage conversion is described as a solution for a hot carrier-injection problem. A 256K CMOS dynamic RAM has been designed and fabricated as a test vehicle for these techniques.

Theoretical, practical and analogical limits in ULSI

Abstract: Ultra large scale integration is governed by a hierarchy of limits. The levels of t,his hierarchy can be codified as 1) fundamental, 2) matcrial, 3) device, 4) circuit and 5) system. Fundamental limits are immutable laws of nature; they cannot be changed. Material limits are specific to conlposition but do not change frequently in practice. Silicon has been the keystone material of integrated electronics for the past two decades and this is unlikely to change during the next two. Device limits depend upon both the material properties and configuration of VLSI components. Consequently, these limits are useful in projecting the smallest possible dimensions of structures uch as IGFET’s. Circuit limits are unique because they retain both a complete physical description and a definition of the information processing function of a group of components and interconnections. Moreover, circuit limits describe device performance in a realistic operating environment and not in sterile isolation. Consequently, the circuit level of the hierarchy is the most appropriate one for projecting the smallest allowable dimensions of ULSI structures for specific purposes. The system level of the hierarchy can be expanded into several discrete steps reflecting the logic design, architecture, instruction set, algorithms and application of a particular ULSI configuration. System limits are the most numerous and nebulous set of the hierarchy. However, because opportunities for integration at each of the five hierarchical levels are constrained by the limits of all preceding levels, system limits represent the most profoundly important set. Each level of the hierarchy includes both theoretical and practical limits. For example, at the fundamental level thermal fluctuations impose a theoretical limit on switching energy of several kT tha t is further restricted by practical constraints on cooling temperature. Although theory suggests use of high mobility GaAs or InP materials, for overwhelming practical reasons Si dominates VLSI. Avoidance of drain-to-soarce junction punch-through determines a throretical minimum channol Icllgth for IGFET devices which may never beconlc pract,ical due to manufacturing limitations of microlithographic technology. Practical supply voltage standards may prevent reaching tl1eoretica.l circuit limits on the power-delay product of CMOS technology. Common clock skew illustrates a simple system limit depending on interconnect time delay. The totality of practical limits is described by three parameters which collectively measure the overall rate of progress of VLSI. These three parameters are the minimum feature size, die area and packing eficiency of a VLSI chip. Packing efficiency has previously been described by Moore [l] as “clcverness.” Recognizing tha t relative packing efficiency can be defined as “(the area occupied by a device or circuit following a purely geometric scaling) over (the area occupied following geometric scaling in combination with a modified design)” permits independent estimates of the three parameters. The combined time derivatives of these parameters determine the rate of change of the total number of components per chip, the central measure of progress in VLSI. An intriguing projection of the long term future of VLSI can be developed by comparison of the mature industrial revolution with the modern information revolution. A correspondence between structural materials in the industrial revolution and electronic materials in the information revolution suggests a set of long term “analogical limits” on ULSI. A basis for introducing analogical limits is the observation that technological advances in different fields often have followed similar patterns of development. The objective of this essay is to project the future of ULSI by studying the five levels of theoretical, practical and andogical limits which govern its progress.

A Quaternary Logic Encoder-Decoder Circuit Design Using CMOS,

Abstract: : A binary-to-quaternary encoder and quaternary-to-binary decoder circuit pair is described as designed in a 5-volt CMOS technology. These circuits communicate with logical currents. Using model parameter values for a standard 5-micron polysilicon gate process technology and 10 microamp logical currents, we have simulated propagation delays of about 20 ns from binary encoder input to binary decoder output. With the encoder using scaled-up logical currents and driving a 100 pF load on the decoder input to simulate communication between chips, we observe simulated worst-case delays of about 35ns. (Author)

CMOS Schmitt trigger circuit

Abstract: A CMOS Schmitt trigger which has two series-connected inverters uses both an input and an output signal to provide hysteresis. A pair of series-coupled transistors is coupled between a power supply terminal and a node between the two inverters. One of the transistors has a control electrode for receiving the input signal. The other of the transistors has a control electrode for receiving the output signal.