Showing papers on "CMOS published in 1984"

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

Abstract: A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.

Cascode voltage switch logic: A differential CMOS logic family

Abstract: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described. A CMOS circuit using 10,880 NMOS differential pairs has been developed using this approach.

A self-calibrating 15 bit CMOS A/D converter

Abstract: A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.

Design of linear CMOS transconductance elements

Abstract: Some novel circuit techniques for realizing linear CMOS tranconductance elements are proposed. The circuits discussed have superior linearity and input voltage range compared with the conventional source-coupled differential pair. Design tradeoffs are examined and computer simulation results are used to verify theoretical predictions. The results show close agreement between predicted behavior and simulated performance.

A ratio-independent algorithmic analog-to-digital conversion technique

Abstract: An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Abstract: Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However, the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators, the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition, design guidelines are suggested and test results are presented.

CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications

Abstract: Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.

FABRICS II: A Statistically Based IC Fabrication Process Simulator

Abstract: This paper describes FABRICS II, an IC fabriction process simulator which takes into account the statistical fluctuations inherent in the manufacturing process. FABRICS II is composed of two parts, a fabrication process simulator FAB1, and a semiconductor device simulator FAB2. The simulator produces model parameters of typical semiconductor devices manufactured in various fabrication processes (NMOS, CMOS, or bipolar). Possible applications of FABRICS II include verification and optimization of process and circuit design, yield prediction and maximization prior to IC fabrication, and IC failure analysis. Two examples which illustrate the application of FABRICS II are presented.

FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's

Abstract: Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.

Method of manufacturing CMOS devices

Abstract: A CMOS semiconductor structure having insulation sidewall spacers whose width is selected independently for NMOS and PMOS devices. The width of the spacer is selected to reduce hot electron injection in the N channel device and to insure that the gate and source regions are aligned with or underlap the gate in the P channel device. A narrower spacer is used for the P channel device than for the N channel device which permits the formation of a P channel device having a threshold voltage less than 1 volt.

Method of making field-plate isolated CMOS devices

Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

MOS register for selecting among various data inputs

Abstract: In a high speed latching circuit (C) for selectively receiving one or plural slowly changing input data signals and latching them at high speed, one or plural first CMOS FETs (31, 33, 35, 37) and one or plural second CMOS FETs (32, 34, 36, 38) of p-conductivity type are connected in series respectively to form one or plural series connections (31+32, 33+34, 35+36, 37+38), wherein selection signals are given to the gates of the first CMOS FETs, input data signals are given to the gates of the second CMOS FETs and a flip-flop (30+39+41) is driven by selected one of the series connections.

A Gate Level Model for CMOS Combinational Logic Circuits with Application to Fault Detection

Abstract: A procedure to derive gate level equivalent circuits for CMOS combinational logic circuits is given. The procedure leads to a model containing AND, OR and NOT gates. Specifically it does not require memory elements as does an earlier model and also uses fewer gates. It is shown that tests for classical stuck-at-0 and stuck-at-1 faults in the equivalent circuit can be used to detect line stuck-at, stuck-open and stuck-on faults in the modeled CMOS circuit.

An algorithm for CMOS timing and area optimization

Abstract: Delay-time optimization for integrated circuits is discussed. A design truly optimized for delay time is seldom practical because the silicon area increases very rapidly when the minimum delay time is approached. The author presents an algorithm which facilitates an intelligent compromise between the delay time and the silicon area of a logic chain. A computer software based on this algorithm can interactively assist the designer in the selection of logic pattern, the number of stages, and the sizes of the transistors. Some basic assumptions are made in this algorithm in order to keep the mathematics manageable. Consequently, some random parameters related to layout and interconnection are not addressed. The intended use of this algorithm is to guide the designer to arrive at an approximately optimized design during the logic definition stage and before the layout stage. Later, when the layout is completed, a circuit simulator should be used to fine-tune the design by incorporating these random layout parameters.

Process for producing CMOS structures with Schottky bipolar transistors

Abstract: A process is disclosed for making CMOS transistors in combination with self-aligned fully oxide isolated Schottky clamped bipolar transistors.

Built-in test for CMOS circuits

Abstract: In CMOS technology combinational circuits become sequential in the presence of stuck-open faults. Instead of a single test pattern a sequence of patterns is necessary for each such fault. In this paper two kinds of hardware test generation techniques for built-in testing are described which produce the required sequences. One approach is suitable for sequential CMOS circuits the other for combinational CMOS circuits.

CMOS schmitt triggers

Abstract: Two variants of CMOS Schmitt triggers, consisting of only four enhancement-type MOS transistors, are proposed in the paper. One consists of three NMOS transistors and one PMOS transistor, while the other consists of one NMOS and three PMOS transistors. A Schmitt trigger with three pairs of CMOS transistors is also described. The hysteresis voltage depends on supply voltage and transistor geometry.

CMOS eprom sense amplifier

Abstract: Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the present invention. The sense amplifier tolerates increased variation in the characteristics of programmed or unprogrammed cells and therefore increases the manufacturing yields of the arrays. It additionally achieves fast accessing and sensing of the stored data.

Class AB output circuit with large swing

Abstract: An output stage is disclosed wherein class AB bias is employed. The stage is quiescently biased by means of current mirrors so that the bias is controlled mainly by ratioed geometric elements. The output transistors are biased by means of unity gain common gate drivers that provide the desired level shifting. The output voltage can be swung from from close to the rail potential of the source of the n channel output transistor to close to the rail potential of the source of the p channel transistor. The circuit can drive relatively large load currents and can be fabricated using either CMOS or conventional bipolar integrated circuits.

A CMOS Structure with high latchup holding voltage

Abstract: Latchup free operation is demonstrated in CMOS by attaining holding voltages in excess of V dd (5V). A thin epitaxial layer over a heavily doped substrate together with butted background contact at transistor sources is shown to be an effective structure to control the parasitic bipolar latchup. Experimental results are presented with and without butted contact and with different epi-thicknesses. In addition to the traditionally quoted latchup holding current, measurements of latchup holding voltage are provided allowing a more clearly defined determination of latchup immunity.

A precision CMOS bandgap reference

Abstract: The simple circuit uses naturally occurring vertical n-p-n bipolar transistors as reference diodes. Use is made of p-tub diffusions as temperature-dependent resistors to provide current bias, and an op-amp is used for voltage gain. Only two reference diodes, three p-tube resistors, and one op-amp are necessary to produce a reference with fixed voltage of -1.3 V. An additional op-amp with two p-tub resistors will adjust the output to any desired value. The criteria for temperature compensation are presented and it is shown that the properly compensated circuit can in principle produce thermal drift which is less than 10 p.p.m.//spl deg/C. Process sensitivity analysis shows that in practical applications it is possible to control the output to better than 2%, while keeping thermal drift below 40 p.p.m.//spl deg/C. Test circuits have been designed and fabricated. The output voltage produced was -1.3/spl plusmn/0.025 V with thermal drift less than 7 mV from 0/spl deg/C to 125/spl deg/C. Significant improvements in performance, at modest cost in circuit complexity, can be achieved if the op-amp offset contribution to the output voltage is reduced or eliminated.

A CMOS narrow-band signaling filter with Q reduction

Abstract: A circuit for extracting signaling information from its associated voice channel in frequency-division multiplexing has been integrated in metal gate CMOS technology. It uses a frequency translation technique that effectively enhances the Q of the filter to >100. It contains a programmable prefilter, a programmable modulator, and a highly selective bandpass filter. The frequency translation was accomplished through the use of a balanced modulator, which is well suited to a switched-capacitor realization. Design considerations that must be addressed in choosing an optimum architecture and a method of analyzing the ill effects of aliasing in a sampled data modulator were also presented. The technique described here is applicable to the design of a filter with an effective Q of much greater than 100.

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

Abstract: A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.

Dynamic logic CMOS circuits

Abstract: A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.

Transient Radiation Upset Simulations of CMOS Memory Circuits

Abstract: A computer simulation technique has identified and modeled a dominant mechanism for transient ionizing radiation induced logic upset in certain CMOS integrated circuits. This mechanism, termed 'rail span collapse' here, has accounted for the discrepancy between simulated upsets of these circuits using only local radiation induced photocurrents and the experimentally observed upset dose-rate levels.

Power-supply rejection in differential switched-capacitor filters

Abstract: The principal motivation of using a fully differential configuration is to reduce power supply coupling. For this reason, an analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed. Experimental results obtained from a CMOS integrated circuit realization are also included. The circuit achieves 50 dB of power supply rejection ratio across the passband.

Latchup model for the parasitic p-n-p-n path in bulk CMOS

Abstract: The inherent parasitic bipolar transistors and p-n-p-n paths in monolithic CMOS circuits can be undesirably triggered into the low resistance and high current state, i.e., latchup. To ensure the safe operation for the future scaled CMOS circuits, an accurate latchup model is required for design optimization. A modified lumped resistance model has been developed which is shown to accurately predict the latchup characteristics provided the device parameters are accurately measured and reflect those at the latchup state. The model includes the spreading resistance effect in the substrate by a resistor network and it is shown to be critical in the latch-up characterization. Experimental data that supports this model is presented. The reversed layouts in CMOS circuits have been shown to greatly improve the latchup holding current. The dynamic characterization of latchup, caused by voltage overshoot at the input terminals, has also been characterized. It is shown that a minimum turn-on time for the latchup triggering exists and is governed by the base transit time in the lateral transistor with an enhanced diffusion coefficient from the high injection effect.

Transient drain current and propagation delay in SOI CMOS

Abstract: The transient overshoot in drain current that occurs in thin-film SOI (Si-on-SiO 2 ) MOSFET's because of the floating body in analyzed, and the benefit it can provide to propagation delay (speed) in SOI CMOS digital circuits is assessed. The analysis accounts for the charge coupling between the front and back gates, and hence describes the dependence of the transient drain (saturation) current and propagation delay on the back-gate bias as well as on the switching frequency. Measurements of the transient current in recrystallized SOI MOSFET's and of propagation delay in SOI CMOS inverters and ring oscillators are described and shown to support the theoretical analysis. The current overshoot is especially beneficial in low-voltage circuits, although at high frequencies other floating-body effects can degrade the speed.

A CMOS floating point multiplier

Abstract: A 32-bit CMOS floating-point multiplier is described. The chip can perform 32-bit floating-point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed-point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively; the typical power dissipation is 195 mW at 10,000,000 operations per second. High-speed multiplication techniques, a modified Booth's algorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2-/spl mu/m n-well CMOS technology; it contains about 23000 transistors 5.75/spl times/5.67 mm/SUP 2/ in size.

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

Abstract: A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.