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Showing papers on "CMOS published in 1985"


Book
01 Jan 1985
TL;DR: CMOS Circuit and Logic Design: The Complemenatry CMOS Inverter-DC Characteristics and Design Strategies.
Abstract: Introduction to CMOS Circuits. Introduction. MOS Transistors. MOS Transistor Switches. CMOS Logic. Circuit Representations. CMOS Summary. MOS Transistor Theory. Introduction. MOS Device Design Equation. The Complemenatry CMOS Inverter-DC Characteristics. Alternate CMOS Inverters. The Differential Stage. The Transmission Gate. Bipolar Devices. CMOS Processing Technology. Silicon Semiconductor Technology: An Overview. CMOS Technologies. Layout Design Rules. CAD Issues. Circuit Characterization and Performance Estimation. Introduction. Resistance Estimation. Capacitance Estimation. Inductance. Switching Characteristics. CMOS Gate Transistor Sizing. Power Consumption. Determination of Conductor Size. Charge Sharing. Design Margining. Yield. Scaling of MOS Transistor Dimensions. CMOS Circuit and Logic Design. Introduction. CMOS Logic Structures. Basic Physical Design of Simple Logic Gates. Clocking Strategies. Physical and Electrical Design of Logic Gates. 10 Structures. Structured Design Strategies. Introduction. Design Economics. Design Strategies. Design Methods. CMOS Chip Design Options. Design Capture Tools. Design Verification Tools. CMOS Test Methodolgies. Introduction. Fault Models. Design for Testability. Automatic Test Pattern Generation. Design for Manufacturability. CMOS Subsystem Design. Introduction. Adders and Related Functions. Binary Counters. Multipliers and Filter Structures. Random Access and Serial Memory. Datapaths. FIR and IIR Filters. Finite State Machines. Programmable Logic Arrays. Random Control Logic.

1,207 citations


Journal ArticleDOI
TL;DR: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits.
Abstract: Devices available in digital oriented CMOS processes are reviewed, with emphasis on the various modes of operation of a standard transistor and their respective merits, and on additional specifications required to apply devices in analog circuits. Some basic compatible analog circuit techniques and their related tradeoffs are then surveyed by means of typical examples. The noisy environment due to cohabitation on the chip with digital circuits is briefly evoked.

319 citations


Journal ArticleDOI
TL;DR: The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.
Abstract: Crystal is a timing verification program for digital nMOS and CMOS circuits. Using the circuit extracted from a mask set, the program determines the length of each clock phase and pinpoints the longest paths. Crystal can process circuits with about 40 000 transistors in about 20-30 min of VAX-11/780 CPU time. The program uses a switch-level approach in which the circuit is decomposed into chains of switches called stages. A depth-first search, with pruning, is used to trace out stages and locate the critical paths. Bidirectional pass transistor arrays are handled by having the designer tag such structures with flow control information, which is used by Crystal to avoid endless searches. Delays are computed on a stage-by-stage basis, using a simple resistor-switch model based on rise-time ratios (a measure of how fully turned-on the transistors in the stage are). The delay modeler executes 10 000 times as fast as SPICE, yet produces delay estimates that are typically within 10 percent of SPICE for digital circuits.

246 citations


Journal ArticleDOI
TL;DR: In this paper, a design methodology was developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools.
Abstract: Building on nearly two decades of reported results for MOSFET's fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFET's in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

231 citations


Journal ArticleDOI
TL;DR: A novel technique is presented for performing the analog multiplication in CMOS technology by linearizing the source-coupled circuit and introducing the folded CMOS GSTC.
Abstract: A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.

195 citations


Journal ArticleDOI
A. Yukawa1
TL;DR: In this article, a novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC.
Abstract: A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.

192 citations


Journal ArticleDOI
TL;DR: In this paper, the design of voltage- or current-controllable linear transconductance elements needed for the continuous-time CMOS active filters is explored in detail, and circuit configurations, techniques of achieving linearity, and temperature compensation using the controlling variable are outlined.
Abstract: This paper explores in detail the possible approaches to. the design of voltage- or current-controllable linear transconductance elements needed for the design of continuous-time CMOS active filters. The focus of the paper is on circuit configurations, techniques of achieving linearity, and temperature compensation using the controlling variable. Circuit techniques for obtaining small transductance values are outlined. Simulation results are presented.

184 citations


Journal ArticleDOI
TL;DR: In this paper, an 8-bit subranging converter (ADC) was realized in a 3/spl mu/m silicon gate, double-polysilicon capacitor CMOS process.
Abstract: A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.

152 citations


Proceedings Article
01 Jan 1985
TL;DR: Gate oxide shorts will cause increased IDD and in the majority of cases will degrade logic voltage levels and propagation delay times, but may not affect functionality, so stuck-at and functional models are inadequate for testing gate oxide shorts in CMOS ICs unless they are used in conjunction with IDD measurements.
Abstract: This paper examines the electrical characteristics and testing considerations of gate oxide shorts Gate oxide shorts will cause increased IDD and in the majority of cases will degrade logic voltage levels and propagation delay times, but may not affect functionality Stuck-at and functional models are therefore inadequate for testing gate oxide shorts in CMOS ICs unless they are used in conjunction with IDD measurements

151 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits, and the individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique.
Abstract: The effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits. The individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique. Processing splits and post-irradiation biased anneals are used to vary the ratio of oxide-trapped charge to interface-state charge. It is shown that the effective channel mobility depends to first order on the interface-state charge density. Static power supply current is correlated with the n-channel leakage at zero gate voltage while output drive currents are a function of both threshold voltage and channel mobility. Changes in propagation delay of signals through integrated circuits can be understood when both mobility and threshold voltage are considered as a function of the bias dependent charge buildup. A new transistor switching time figure of merit, t/C, which measures the drain to source drive over a full logic level voltage swing at the drain node, is introduced. This index is then shown to correlate with propagation delay in an IC. Finally, performance changes in an IC are modeled using only the measured buildup of oxide-trapped and interface-state charges from transistors as a function of radiation.

150 citations


Patent
01 Oct 1985
TL;DR: In this article, a pull-up circuit and a pulldown circuit are used to distribute switching current spikes over time in a CMOS output buffer, which provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing.
Abstract: A CMOS output buffer provides high drive current without sacrificing speed and with minimum output signal distortion due to internal chip ground bounce or output signal ringing. The output buffer includes a pull-up circuit and a pull-down circuit which distribute switching current spikes over time. The pull-up circuit includes a P-channel FET and an N-channel FET connected in parallel between an output terminal and supply terminal VDD, with an inverter connected between the gates of the N-channel and P-channel FETs to provide the proper phase for the P-channel FET as well as delaying turn-on of the P-channel FET with respect to turn-on of the N-channel FET. The pull-down circuit includes a pair of N-channel FETs connected in parallel between the output terminal and ground, and a delay resistance connected between their gates so that turn-on of one of the N-channel FETs is delayed with respect to the other.

Journal ArticleDOI
TL;DR: In this paper, a self-aligned titanium silicide process was developed for VLSI applications with sheet resistances of 1.0-2.0 Ω/square.
Abstract: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Journal ArticleDOI
TL;DR: In this article, a triode transconductor fully differential transconductance element for use in continuous-time CMOS integrated filters is proposed, based on a common-source pair of triodemode MOS transistors.
Abstract: A `triode transconductor´ fully differential transconductance element for use in continuous-time CMOS integrated filters is proposed. It is based on a common-source pair of triodemode MOS transistors. Preliminary experimental results from breadboarded transconductors and complete filters show good distortion performance. Several practical advantages are claimed over previous approaches.

Journal ArticleDOI
TL;DR: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented.
Abstract: A new family of ternary logic circuits that uses both depletion and enhancement types of complementary metal-oxide semiconductor (CMOS) transistors is presented. These circuits use two power supplies, each below the transistor's threshold voltages, and do not include resistors. Circuit designs of basic ternary operators (inverters, NAND, NOR) are described. These basic ternary operators can be used as building blocks in the VLSI implementation of three-valued digital systems. An example of the design of a ternary full adder using this family of logic circuits is also presented.

Journal ArticleDOI
TL;DR: In this paper, two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies, which can be effective tool for the design of networks up to five or six variables.
Abstract: Two formal design techniques are presented to realize pass logic networks in NMOS and CMOS technologies. The first technique uses a modified Karnaugh map minimization procedure, which can be effective tool for the design of networks up to five or six variables. For networks involving more than six variables, an algorithmic procedure is developed by modifying the conventional Quine-McCluskey approach. The savings in silicon area depends on the transistor count as well as the interconnect structure. Maximum topograph regularity for an array of pass transistors can be achieved in the intersection of the set of control variables with the set of pass variables in a null set. This allows the pass variables and the control variables to flow at right angles to each other. This requirement may increase the transistor count in the design, hence there is a tradeoff between topological regularity and transistor count. Cells drawn in CMOS and NMOS are compared.

Journal ArticleDOI
TL;DR: Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies.
Abstract: A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Journal ArticleDOI
TL;DR: Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors which are designed to be insensitive to the low beta and alpha current gains of these devices.
Abstract: Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.

Journal ArticleDOI
TL;DR: In this article, the role and effects of both electron and hole injection are discussed, and a model of the mean time to failure for NMOS devices fabricated with two different source-drain diffusions is also presented.
Abstract: The high drain-effect transistor characteristic observed after hot-carrier injection and trapping in the oxide has been found to be due to the uneven trapped-carrier distribution near the drain, which causes the threshold voltage to vary as a function of drain voltage. A discussion of the role and effects of both electron and hole injection is presented. The nonlinear distribution of carriers trapped in the gate oxide is described. One result is that the nonuniform surface band bending causes the subthreshold leakage to be an exponential function of the drain voltage. The combined increase in threshold voltage, subthreshold leakage, and a decrease in subthreshold slope will translate into slower circuit speed and higher standby power dissipation [37] in CMOS circuits. An experimental model of the mean time to failure, for NMOS devices fabricated with two different source-drain diffusions, is also presented. For the first time, the model has been extended to include the channel-length dependence. The model assumes a reliability criterion of less than a 10-mV threshold-voltage shift in 100 000 h of operation. Experimental results and subsequent calculations show that for 350-A gate-oxide devices at 5.0 V operation, 2.5 µm is the minimum electrical channel-length device which can be fabricated using a traditional source-drain process. Conversely, submicrometer electrical channel-length devices can be fabricated using an arsenic-phosphorous "graded" source-drain process, even at 5.5-V operation.

Journal ArticleDOI
K. Matsui1, T. Matsuura1, S. Fukasawa1, Y. Izawa1, Y. Toba1, N. Miyake1, K. Nagasawa1 
01 Dec 1985
TL;DR: In this article, video band switched-capacitor (C) filters, including a two-dimensional filter, have been experimentally fabricated by using 2-/spl mu/m/spl middot/CMOS technology and high-speed/high-precision circuits, an LSI clock rate of 14 MHz, signal swing of 2 V p-p with a single 5-V supply, random noise S/N of 60-70 dB pp/rms at LSI output, and power dissipation of less than 5 mW per amplifier.
Abstract: In order to realize self-contained analog video LSI, video band switched-capacitor (C) filters, including a two-dimensional filter, have been experimentally fabricated By using 2-/spl mu/m/spl middot/CMOS technology and high-speed/high-precision circuits, an LSI clock rate of 14 MHz, signal swing of 2 V p-p with a single 5-V supply, random noise S/N of 60-70 dB p-p/rms at LSI output, and power dissipation of less than 5 mW per amplifier have been achieved Single-stage cascode amplifiers are extensively used to attain video band speed Neutralization is introduced into fully differential filters to improve their frequency response

Proceedings ArticleDOI
S. Mukherjee, T. Chang, R. Pang, M. Knecht, D. Hu 
01 Jan 1985
TL;DR: In this article, the authors describe an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor and its implementation in a 512K CMOS EEPROM memory chip.
Abstract: This paper describes an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor (1), and its implementation in a 512K CMOS EEPROM memory chip. The single transistor EEPROM cell is based on an innovative device concept, and utilizes proven process techniques. The cell is programmed to a high Vt state by channel hot electron injection like an EPROM cell, and erased to a low Vt state by Fowler Nordheim tunneling from the floating gate to source diffusion. With the proper choice of gate dielectric and cell layout the cell is programmed to high threshold with less than 5 volts on the drain and less than 15 volts on the control gate. Erasing is achieved with less than 15 volts on the source diffusion. A 25 square micron cell has been implemented in a 512K EEPROM memory chip with a die size of 4.3 mm. by 7 mm.

Book Chapter
01 Jan 1985
TL;DR: In this paper, the elements of an electronic receptor with many orders of magnitude dynamic range are described, and the key to very sensitive receptors is to use the current gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.
Abstract: The photoreceptors in biological systems give meaningful outputs over about six orders of magnitude of illumination intensity. If we are to build an electronic vision system that is truly useful, it must have a similar dynamic range. The elements of an electronic receptor with many orders of magnitude dynamic range are described below. Experimental devices were fabricated in p-well cMOS bulk technology through the MOSIS foundry; npn phototransistors with collector connected to substrate are a byproduct of this process. The n-type bulk forms the collector, the p-well is the base, and the n+ diffusion the emitter. In a typical process, a large transistor of this sort has a current gain β of more than a thousand. Smaller transistors have lower current gains, but are still respectable. The key to very sensitive receptors is to use the current gain of this very clean bipolar transistor before subjecting the signal to any noise from subsequent amplification stages.

Journal ArticleDOI
TL;DR: In this article, the effects of trapped-hole annealing and electron-hole recombination were used to correlate the responses of transistors irradiated with Co-60 gamma rays or 10 keV X rays.
Abstract: Dose-enhancement effects are monitored with standard CMOS transistors by measuring thresholdvoltage shifts due to oxide-trapped charge and interface states. These results, in conjunction with studies of the effects of trapped-hole annealing and electron-hole recombination, are used to correlate the responses of transistors irradiated with Co-60 gamma rays or 10 keV X rays.

Patent
30 Jul 1985
TL;DR: In this article, a signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.
Abstract: A signal delay device comprises a CMOS gate circuit (12, 14) having an input terminal (13) to which a binary input signal to be delayed is applied, an output terminal (15) from which a delayed signal is derived and power voltage supply terminals to which operation power voltages are applied. The delay time of the CMOS gate circuit depends upon voltage applied to it and, utilizing this phenomenon, voltage control means (16,18) is provided in a power supplying path for the CMOS gate circuit for controlling voltage applied to the CMOS gate circuit. The signal delay device using the CMOS gate circuit is applied to various circuits including an analog signal delay circuit, a jitter absorption circuit and a fixed head type magnetic tape reproducing device.

Journal ArticleDOI
TL;DR: In this article, the authors proposed scaling the NFET chain so that the FET closest to the ground is the largest, with FET size decreasing monotonically from ground to output.
Abstract: The switching delay of a Domino CMOS gate can be reduced by up to 30% by scaling the NFET chain so that th FET closest to the ground is the largest, with FET size decreasing monotonically from ground to output. The technique is most effective when applied to complex gates, such as those found in a carry look-ahead circuit. The same technique has application to other MOS circuits including NMOS circuits.

Journal ArticleDOI
TL;DR: This paper proposes a new logical model for nMOS and CMOS circuits in the form of a multivalued algebra defined on a set of node states that allows for strong interactions between all three terminals of a transistor.
Abstract: This paper proposes a new logical model for nMOS and CMOS circuits. Existing gate-level and switch-level models are limited in their ability to simulate MOS circuit behavior accurately when modeling physical failures. The model proposed in this paper is in the form of a multivalued algebra defined on a set of node states. The state of a node is represented as a pair where "a" specifies the condition of a node and "b" specifies the logic level: There are five conditions and five logic levels. The assignment of node states is done dynamically during the process of logic simulation. The rules of the algebra are used to derive state tables that model the behavior of transistors. Our general model of a transistor allows for strong interactions between all three terminals of a transistor. This enables us to model the effects of physical failures such as a short between the gate and drain of a transistor. A simulation algorithm based on the algebra is discussed, and techniques for simulating physical failures in MOS circuits using the algebra are indicated.

Patent
27 Sep 1985
TL;DR: In this article, an integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS), and highvoltage hV-n-channel transistors and HV-PMOS transistor (HV-NMS transistors).
Abstract: An integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS transistors and LV-PMOS transistors) and high-voltage n-channel and p-channel MOS transistors (HV-NMOS transistors and HV-PMOS transistors). There are formed at the same time first p - regions for the compartments of the LV-NMOS transistors, second p - regions in which only the sources and channels of the HV-NMOS transistors are incorporated, and third p - regions in which only the drains of the HV-PMOS transistors are incorporated.

Journal ArticleDOI
TL;DR: In this article, two types of integrated silicon magnetic-field sensors realized recently in standard CMOS technology, viz. the split-drain MOSFET and the vertical Hall-effect device sensitive to magnetic fields perpendicular and parallel to the chip surface, are presented.
Abstract: We present two-dimensional numerical simulations of two types of integrated silicon magnetic-field sensors realized recently in standard CMOS technology, viz. the split-drain MOSFET and the vertical Hall-effect device sensitive to magnetic fields perpendicular and parallel to the chip surface, respectively. Our results include potential, current, and surface charge distributions as well as sensitivity, linearity, and noise. Improved device geometries are suggested. Both the finite-difference method and a novel Greens function approach are used for solving the differential equations governing the carrier transport in the presence of a magnetic field.

Journal ArticleDOI
01 Oct 1985
TL;DR: In this article, the authors measured subnanosecond gate delays on complex logic gates (e.g. sum functions of a full adder) designed in the differential split-level CMOS circuit technique.
Abstract: Subnanosecond gate delays (0.8 ns) have been measured on complex logic gates (e.g. sum functions of a full adder) designed in the differential split-level CMOS circuit technique. This high speed has been achieved by reducing the logic swing (2.4 V) on interconnect lines between logic gates, by using current controlled cascoded cross-coupled NMOS-PMOS loads, by using combined open NMOS drains as outputs, and by using shorter channel lengths (L/SUB eff/=1 /spl mu/m) for the NMOS devices in the logic trees with reduced maximum drain-source voltages to avoid reliability problems. Extra ion implantation protects these transistors from punchthrough.

Patent
22 Nov 1985
TL;DR: In this article, a CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed, while minimizing the increase in switching speed which accompanies any increase in internal cell impedance.
Abstract: A CMOS SRAM exhibiting a high level of immunity to single event upset errors, such as caused by ionizing radiation, is disclosed. In CMOS SRAM cells with small feature sizes, single event errors result from ion interactions with transistor drains on the side of a cell holding a low voltage. The configuration of the cell presents a high impedance between these low voltage drains and the low voltage gate on the opposite side of the cell, while presenting a high impedance between corresponding components with high voltages. The SRAM cell is protected from single event errors while minimizing the increase in switching speed which accompanies any increase in internal cell impedance.

Journal ArticleDOI
TL;DR: In this paper, the authors present the implementation of the self-aligned TiSi2 process using rapid thermal processing to simultaneously fabricate transistor gates and junctions with a sheet resistance of 1 Ω/sq.
Abstract: This paper reviews recent progress towards integrating the self‐aligned titanium silicide process into VLSI NMOS and CMOS technologies, to simultaneously reduce the gate and junction sheet resistances to below 1 Ω/sq. In addition to reviewing the base line self‐aligned TiSi2 process, the key issues that must be addressed if the process is going to be successfully integrated into a VLSI process flow, without having adverse effects on device parameters, will be discussed. Such issues are how the sheet resistance can be reduced to <1 Ω/sq without bridging between the gate and source/drain regions, the effect of silicide stress on gate oxide integrity, and how both P‐ and N‐type junctions can be silicided without adversely affecting diode or transistor properties. Recent results on the hot electron hardness of silicided devices compared to unsilicided transistors will also be presented. The implementation of the self‐aligned titanium silicide process using rapid thermal processing to simultaneously fabricate transistor gates and junctions with a sheet resistance of 1 Ω/sq will also be described. Using the self‐aligned TiSi2 technology, fully functional VLSI CMOS and NMOS circuits of the 64K static random access memory class of complexity, with 1 μm gates, have been fabricated with yield that is similar to unsilicided parts.