Showing papers on "CMOS published in 1986"

Analog MOS Integrated Circuits for Signal Processing

Abstract: Transformation Methods. MOS Devices as Circuit Elements. MOS Operational Amplifiers. Switched-Capacitor Filters. Nonfiltering Applications of Switched-Capacitor Circuits. Nonideal Effects in Switched-Capacitor Circuits. Systems Considerations and Applications. Index.

Integrated semiconductor magnetic field sensors

Abstract: A magnetic field sensor is an entrance transducer that converts a magnetic field into an electronic signal. Semiconductor magnetic field sensors exploit the galvanomagnetic effects due to the Lorentz force on charge carriers. Integrated semiconductor, notably silicon, magnetic field sensors, are manufactured using integrated circuit technologies. Integrated sensors are being increasingly developed for a variety of applications in view of the advantage offered by the integration of the magnetic field sensitive element together with support and signal processing circuitry on the same semiconductor chip. The ultimate goal is to develop a broad range of inexpensive batch-fabricated high-performance sensors interfaced with the rapidly proliferating microprocessor. This review aims at the recent progress in integrated silicon magnetic devices such as integrated Hall plates, magnetic field-effect transistors, vertical and lateral bipolar magnetotransistors, magnetodiodes, and current-domain magnetometers. The current development of integrated magnetic field sensors based on III-V semiconductors is described as well. Bulk Hall-effect devices are also reviewed and serve to define terms of performance reference. Magnetic device modeling and the incorporation of magnetic devices into an integrated circuit offering in situ amplification and compensation of offset and temperature effects are further topics of this paper. Silicon will continue to be aggressively exploited in a variety of magnetic (and other) sensor applications, complementary to its traditional role as integrated circuit material.

An 80-MHz 8-bit CMOS D/A converter

Abstract: A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.

Accurate simulation of power dissipation in VLSI circuits

Abstract: It becomes increasingly more important to reduce the power dissipation as the number of devices in VLSI increases. Accurate simulation of power dissipation is desirable while circuits are analyzed with circuit simulators such as SPICE. An accurate method is presented for simulating the power dissipation with use of a dependent current source and a parallel RC circuit. The steady-state voltage across the capacitor reads the average power drawn from the supply voltage source. Simulation results are shown for CMOS circuits.

A quad CMOS single-supply op amp with rail-to-rail output swing

Abstract: The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.

A CMOS Four-Quadrant Analog Multiplier

Abstract: A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.

Design procedures for differential cascode voltage switch circuits

Abstract: Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique which has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. Two procedures are presented for constructing DCVS trees to perform random logic functions. The first procedure uses a Karnaugh mapping technique and is a very powerful pictorial method for hand-processing designs involving up to six variables. The second procedure is a tabular method based on the Quine-McCluskey approach and is suitable for functions with more than six variables. Both of these procedures are considerably easier to implement than a recently proposed algebraic technique which relies upon decomposition and factorization of Boolean expressions. Several DCVS circuits that have been synthesized by the Karnaugh map (K-map) and tabular procedures are presented.

Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

Abstract: In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of circuits derived from sum of products and product of sums expressions for a given combinational logic function are investigated to determine the testability of FET stuck-open faults by tests which will remain valid in the presence of arbitrary circuit delays. Necessary and sufficient conditions for the existence of tests that will remain valid in the presence of arbitrary circuit delays are derived. Using these conditions, it is shown that all single FET stuck-open faults, in a specific design using a single CMOs complex gate, are detectable by tests that remain valid in the presence of arbitrary circuit delays. For several other realizations, methods to augment them, to insure detectability of all single FET stuck-open faults by tests that will remain valid in the presence of arbitrary circuit delays are proposed. It is observed that in many of the logic circuits investigated it is also possible to avoid test invalidation due to charge distribution.

Reliability and electrical properties of gate oxide shorts in CMOS ICs

Abstract: This paper examines the reliability of gate oxide shorts in CMOS ICs Gate oxide shorts cause increased quiescent IDD but may not initially affect functionality These shorts can subsequently change due to thermal and electric field stress during operation and cause functional failure Therefore, gate oxide defects can significantly degrade CMOS IC reliability 14 refs

Test Considerations for Gate Oxide Shorts in CMOS ICs

Abstract: Gate oxide shorts are defects that must be detected to produce high-reliability ICs. These problems will continue as devices are scaled down and oxide thicknesses are reduced to the 100-A range. Complete detection of gate oxide shorts and other CMOS failure mechanisms requires measuring the IDD current during the quiescent state after each test vector is applied to the IC. A 100-percent stuck-at fault test set is effective only if each test vector is accompanied by an IDD measurement. This article examines the need for a fast, sensitive method of measuring IDD during each test vector and discusses problems confronting CMOS IC designers, test engineers and test instrumentation designers as they work to meet these demands.

Design Consideration in High Temperature Analog CMOS Integrated Circuits

Abstract: The design of CMOS analog integrated circuits to be operated at elevated junction temperatures is discussed. Considerations which have successfully been implemented in the design of basic analog cells for operation over the 25°-250°C range are emphasized. Simple models arc presented along with the temperature dependencies of key design parameters. These models and high-temperature trends represent sufficient information for first-order hand analysis prior to computeraided design.

CMOS RF circuits for data communications applications

Abstract: The author describes the recent development of two analog CMOS circuits operating at RF frequencies with applications to data communications. One is a four-quadrant analog multiplier which exhibits a 100-MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs of 0.6 and 0.8 V, respectively. The other is a 90/spl deg/ phase shifter which maintains the grain and phase errors of less than 0.5 dB and 3/spl deg/, respectively, for a signal within 40-60-MHz frequency range.

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

Abstract: A design is presented for an 8-bit/spl times/8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-/spl mu/m CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated.

An Integrated Sensor for Electrochemical Measurements

Abstract: A method for the fabrication of a completely integrated solid-state electrochemical sensor which combines a minature liquid junction reference electrode with a CMOS ISFET is presented. The reference electrode is fabricated by preferentially etching silicon to form a porous silicon frit. The CMOS process provides electrical encapsulation of the ISFET. The performance of the reference electrode and CMOS ISFET as an integrated sensor is demonstrated.

A high-frequency CMOS linear transconductance element

Abstract: A simple four-transistor, linear, tunable, high-frequency transconductance element is described. By using a pair of composite n -channel- p -channel devices, the circuit achieves its linearity by current differencing without undue matching requirements. It is shown that linearity and frequency response can be optimized simultaneously by appropriate choice of device dimensions. The performance is verified by SPICE simulations, and an operational transconductance amplifier (OTA) is used as one example for the many applications of the proposed element.

A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts

Abstract: This paper describes a new mixed technology, called Multipower BCD, that, starting from the merging of the VDMOS silicon gate process with the conventional junction isolation process, allows the integration on a single chip of bipolar linear, CMOS logic, and DMOS power functions. The architecture of the process was chosen to optimize the power part, which generally occupies the most chip area. With the DMOS device, many other signal components have been obtained whose electrical and structural characteristics are discussed in relation to some process variables. Many test vehicles have been processed to evaluate the different structures and a first electrical application of the technology is indicated.

Digital CMOS circuit design

Abstract: 1. Introduction.- 1.1. From nMOS to CMOS.- 1.2. CMOS Basic Gates.- 2. MOS Transistor Characteristics.- 2.1. The MOS Transistor.- 2.2. Parasitic Parameters.- 2.3. Small Geometry MOS Transistor.- 2.4. CMOS Transmission Gate.- 2.5. CMOS Inverter.- 2.6. A More Accurate Model for the CMOS Inverter.- 2.7. CMOS Power Dissipation.- 3. Fabrication Processes.- 3.1. The p-well Fabrication Process.- 3.2. The n-well Fabrication Process.- 3.3. LOCMOS Technology.- 3.4. Latchup.- 3.5. The Twin-tub Fabrication Process.- 3.6. The SOS Fabrication Process.- 3.7. Bulk vs. SOI.- 3.8. Design Rules.- 4. Logic Design.- 4.1. Static Logic.- 4.1.1. Complementary Logic.- 4.1.2. nMOS-like Logic.- 4.1.3. Transmission Gate Intensive Logic.- 4.1.4. Cascode Logic.- 4.2. Dynamic Logic.- 4.2.1. Ripple-through Logic.- 4.2.2. P-ELogic.- 4.2.3. Clocked CMOS Logic.- 4.2.4. Domino Logic.- 4.2.5. NORA Logic.- 4.3. Charge Sharing.- 4.4. Bootstrap Logic.- 4.5. Logic Design at the System Level.- 5. Circuit Design.- 5.1. Resistance, Capacitance, and Inductance.- 5.1.1. Interconnect Resistance.- 5.1.2. Interconnect Capacitance.- 5.1.3. Interconnect Inductance.- 5.1.4. Interconnect Discontinuities.- 5.1.5. Coupling Parameters and Interconnect Delay.- 5.1.6. Diffusion Resistance.- 5.1.7. Contact Resistance.- 5.2. Modeling Long Interconnects.- 5.3. The Concept of Equivalent Gate Load.- 5.4. Delay Minimization.- 5.4.1. Inverter Delay and Sizing.- 5.4.2. Inverter Chain Sizing.- 5.4.3. Inverter Chain Sizing with Stray Capacitance.- 5.5. Transistor Sizing in Static Logic.- 5.6. Transistor Sizing in Dynamic Logic.- 6. Design of Basic Circuits.- 6.1. Storage Elements.- 6.2. Full-adder.- 6.3. Programmable Logic Array.- 6.4. Random-access Memory.- 6.4.1. Memory Cell.- 6.4.2. Decoder.- 6.4.3. Sense Amplifier.- 6.5. Parallel Adder.- 6.6. Parallel Multiplier.- 6.6.1. The Design of a Multiplier Based on the Modified Booth Algorithm.- 6.6.2. Basic Building-blocks Inside the Array.- 6.6.3. The Problem of Sign Extension.- 6.6.3.1. The "Sign Propagate" Method.- 6.6.3.2. The "Sign Generate" Method.- 6.6.4. The Implementation of a 24-bit CMOS Booth Multiplier.- 7. Driver and I/O Buffer Design.- 7.1. CMOS Inverter Delay Estimation.- 7.1.1. Fall-time Delay Estimation.- 7.1.1.1. Region 1: n-channel Device in Saturation.- 7.1.1.2. Region 2: n-channel Device in Linear Region.- 7.1.2. Rise-time Delay Estimation.- 7.1.3. Refining the Model.- 7.2. Input Buffer.- 7.3. Output Buffer.- 7.4. Tri-state Output Buffer and I/O Buffer.- 7.5. Output Buffer and Bus Driver Design Optimization.- 7.5.1. Unconstrained Delay Minimization.- 7.5.2. Constrained Delay Minimization.- 7.6. Input Protection.- 7.7. Output Protection.- 7.8. Driving Large On-chip Loads.- Appendix A. Layout.- A. 1. General Considerations on Layout.- A.2. Layout Methodologies for Latchup Avoidance.- A.3. Layout with Structured Methodologies.- A. 4. Power and Ground Routing.- Appendix B. Interconnect Capacitance Computation.- B. 1. Case 1: Coupled Microstrip Structure.- B.2. Case 2: Coupled Stripline Structure.- Appendix C. Figures from Section 5.4.2.- Appendix D. Delay Minimization Based on Eq. (7-3).- Appendix E. Equations Related to Fig. 7-10.- Appendix F. Symbols and Physical Constants.

Operation of bulk CMOS devices at very low temperatures

Abstract: Low-temperature (77K, 4.2K) operation is proposed for bulk CMOS devices to be used in superfast VLSI applications. Symmetrical variation of the parameters of both n-channel and p-channel MOSFETs with respect to the temperature and latch-up immunity makes CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, inverter chains and 16-kb static random-access memories (RAMs) with 2-/spl mu/m gate length were measured. Average propagation delay for an inverter chain has been reduced to 175 ps (77K) and 104 ps (4.2K) from 296 ps at 300K without sacrificing power dissipation. The power-delay product is less 1 fJ, which is the smallest for silicon devices reported to date. The chip select-access time of the RAM has been reduced to 14.3 ns (77K) from 24 ns (300K).

Elimination of process-dependent clock skew in CMOS VLSI

Abstract: Delays of two clock signals propagating along their respective CMOS logic circuit paths can be matched against all processing variations if the sum of the pull-up delays of PFETs along the first signal path is matched to that of the second path, and if the sum of the pull-down delays of NFETs along the first path is matched to that of the second path. This design technique allows generation of a skewless pair of upgoing and downgoing CMOS clocks, and the technique allows the design of CMOS VLSI free from process-induced race conditions. The technique is flexible for light or heavy clock load and for the choice of decoder logic. The technique has a wide application in MOS circuits other than clock decoders.

A novel submicron LDD transistor with inverse-T gate structure

Abstract: A novel submicron LDD transistor is demonstrated in which there is a thin extension of the gate polysilicon under the oxide sidewall-spacer giving the gate's cross section the appearance of an inverted letter T. The new inverse-T LDD (ITLDD) transistor features the self alignments of n-LDD and n+source-drain implants to the inside and outside edge, respectively, of the IT gate structure. Optimum n-LDD length for reducing the electric field in the channel region can be achieved by controlling the width of the oxide sidewall-spacer abutting the ledge of the IT-gate in a similar manner to a conventional LDD transistor. However, the "spacer-induced degradations" existing in a conventional LDD transistor are eliminated as a result of the self-aligned n+-to-gate feature in ITLDD. This allows the use of low n-LDD dose for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicron ITLDD transistor with improved transconductance and reliability has been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.

Optical Clock Distribution To Silicon Chips

Abstract: Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.

A versatile 700-1200-V IC process for analog and switching applications

Abstract: An IC process with a wide range of devices up to 1200 V is described. In addition to low-voltage bipolars and CMOS and 230-V VDMOS it provides 700-V high-side LDMOS, HV-PMOS (EPMOS) and low-voltage circuitry, low-side 1200-V LDMOS and 700-V LIGBT (lateral insulated-gate bipolar transistor), as well as 700-V interconnection. These features have been realized by using a substrate of higher resistance in a 250-300-V IC process and by adaptation in the Resurf structure for lateral DMOS. Application examples for flyback and half-bridge power conversion and as a power-bridge driver are given. >

CMOS output buffer having improved noise characteristics

Abstract: A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another. The steady-state stage is delayed, so that the noise from the initial transition does not appear at the power supply and reference supply nodes of the steady-state stage. The circuit also operates so that the output node can be put into a high-impedance state, allowing for common input/output utilization of the circuit.

Zipper CMOS

Abstract: A circuit structure called zipper CMOS is described. The major components in a zipper CMOS circuit are the zipper driver circuit and the alternative N- and P-dynamic logic blocks. The zipper driver generates four strobe signals that drive all the subsequent dynamic blocks. In this structure, the triggering threshold is controlled by the zipper driver and is less than conventional value of half the drain voltage. This allows zipper CMOS circuits to operate at least twice as fast as static CMOS circuits. The zipper driver also ensures stability of the circuit and prevents charge-sharing problems without any penalty in performance or silicon area utilization.

A 4-Mbit DRAM with trench-transistor cell

Abstract: An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

A symmetric submicron CMOS technology

Abstract: A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi 2 source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi 2 gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi 2 /n+ and CoSi 2 /P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.

Design-performance trade-offs in CMOS-domino logic

Abstract: The authors present a study of the charge-sharing problem and its effect on the performance of CMOS-domino logic. Several solutions to the charge-sharing problem are examined, and the results are verified by simulation. Thus, the charge-sharing problem in CMOS-domino logic was identified and alternate approaches were evaluated.

A 4Mb DRAM with cross point trench transistor cell

Abstract: This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2. Row and static column access times are 170ns and 30ns, respectively.

Charge redistribution and noise margins in domino CMOS logic

Abstract: Domino CMOS gates suffer from an inherent noise margin problem as a result of charge redistribution between parasitic capacitances at internal nodes of the circuit under specific input conditions. This charge redistribution effect can destroy the noise margin and cause glitches at the output of a domino gate. This paper deals with circuit and layout techniques which can help in alleviating the problem. A simple analytical noise margin model for domino gates is discussed. The model is useful to monitor the noise margins of a domino gate while dimensioning the devices in the gate to obtain a specified gate delay. A new technique which allows the design of domino gates with a very large fan-in (typically 20 or more inputs), while maintaining good noise margins and acceptable gate delays, is presented. This technique is useful in, for example, decoder circuits.