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Showing papers on "CMOS published in 1988"


Journal ArticleDOI
TL;DR: The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation and applies these criteria to the design of a modulator that has been integrated in a 3- mu m CMOS technology.
Abstract: The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta ( Sigma Delta ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Sigma 2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3- mu m CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm/sup 2/, and has achieved a measured dynamic range of 89 dB. >

779 citations


ReportDOI
01 Jan 1988
TL;DR: A series of compact CMOS integrated circuits that realize the winner-take-all function using only O(n) of interconnect and a circuit that computes local nonlinear inhibition is modified.
Abstract: We have designed, fabricated, and tested a series of compact CMOS integrated circuits that realize the winner-take-all function. These analog, continuous-time circuits use only O(n) of interconnect to perform this function. We have also modified the winner-take-all circuit, realizing a circuit that computes local nonlinear inhibition.

585 citations


Journal ArticleDOI
TL;DR: In this paper, a fully integrated phase-locked loop (PLL) is used to time-align the hi-Z/low-Z transitions of a CMOS CPU and its floating-point coprocessor.
Abstract: A fully integrated phase-locked loop (PLL) is used to time-align the hi-Z/low-Z transitions of a CMOS CPU and its floating-point coprocessor (FPC), resulting in minimum timing difference (skew) between the two devices at their shared data bus, and decreasing the bus cycle time. The PLL circuit abandons the traditional voltage-controlled oscillator function, instead using a CMOS voltage-controlled delay line to improve noise immunity, ease loop stabilization, and permit dynamically adjustable clock periods. With the PLL enable, measured timing skew between the CPU and FPC is below 1 ns. >

356 citations


Journal ArticleDOI
TL;DR: The authors describe recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain 'cost' functions by mapping onto simple analog and digital resistive networks.
Abstract: The authors describe recent developments in the theory of early vision that led from the formulation of the motion problem as an ill-posed one to its solution by minimizing certain 'cost' functions. These cost or energy functions can be mapped onto simple analog and digital resistive networks. The optical flow is computed by injecting currents into resistive networks and recording the resulting stationary voltage distribution at each node. The authors believe that these networks, which they implemented in complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuits, represent plausible candidates for biological vision systems. >

334 citations


Proceedings ArticleDOI
12 Sep 1988
TL;DR: FXT is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults. >

248 citations


Proceedings Article
01 Jan 1988
TL;DR: FXT as mentioned in this paper is a software tool which implements inductive fault analysis for CMOS circuits and extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence.
Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<>

244 citations


Proceedings ArticleDOI
01 Dec 1988
TL;DR: In this article, a novel transistor with compact structure has been developed for MOS devices, whose gate electrode surrounds the pillar silicon island, reducing the occupied area for all kinds of circuits.
Abstract: A novel transistor with compact structure has been developed for MOS devices This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge >

220 citations


Journal ArticleDOI
TL;DR: A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters, achieving a throughput rate of 1 Msample/s with 12 bits of linearity.
Abstract: A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75- mu m CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm/sup 2/, including all digital logic and output buffers. >

219 citations


Journal ArticleDOI
TL;DR: The postirradiation response of CMOS transistors with 30-60-nm gate oxides is investigated as a function of radiation energy, total dose, dose rate, and annealing time and no 'true' dose-rate effects on MOS device response are observed.
Abstract: The postirradiation response of CMOS transistors with 30-60-nm gate oxides is investigated as a function of radiation energy, total dose, dose rate, and annealing time. Measurements of threshold voltage, oxide-trapped charge, and interface traps are reported for times ranging from 10 ms to 4 months following LINAC, Co-60, Cs-137, and 10-keV X-ray irradiations. Exposure dose rates vary by 11 orders of magnitude: from 0.05 to 6*10/sup 9/ rad(SiO/sub 2/)/s. To within the +or-10% uncertainty in the overall dosimetry, no 'true' dose-rate effects on MOS device response are observed. Interface trap and oxide-trapped charge densities are linear with total dose. Preliminary recommendations are made for lot acceptance testing of hardened CMOS circuits and devices intended for use in space and strategic environments. >

195 citations


Book
01 Jan 1988

175 citations


Proceedings Article
Bruno Murari1
01 Sep 1988
TL;DR: In this paper, it is argued that thanks to the development of new power technologies, the separate paths taken by power semiconductors and small signal ICs are converging onto a single discipline: smart power.
Abstract: It is argued that thanks to the development of new power technologies, the separate paths taken by power semiconductors and small signal ICs are converging onto a single discipline: smart power. Integrating high power and high voltage devices plus control circuits on a single chip, smart power ICs bring substantial reduction in cost and enhanced reliability. Moreover, they render feasible solutions that would have been too costly when realized with conventional components. Several different technological approaches to smart power have been explored, but all such technologies share the same basic concept of merging different stcuctures on the same chip, taking advantage of the similarities in processing techniques. Smart power technologies can be classified in a number of ways, the first of which is the isolation technique used: dielectric, junction or self isolation. A further way to classify smart power processes regards the current flow in the power devices. Another fundamental distinction between smart power processes is the nature of the power elements. Two options are available: bipolar and DMOS. Smart power devices can also be divided into single-chip types and single package types.

Proceedings ArticleDOI
07 Nov 1988
TL;DR: It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open, and that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults.
Abstract: In a typical approach to VLSI testing, open faults are modeled by the transistor-stuck-open fault model or are not explicitly covered at all. It is shown that functional faults caused by opens, i.e. by regions with missing material, cannot be modeled well by a transistor stuck-open. It is also shown that the majority of opens which occur in CMOS static circuits manifest themselves as timing faults. The analysis of the behavior of a CMOS transistor with a floating gate indicates it acts as a weakly 'on' active load, and therefore an open gate cannot be detected by stuck-fault testing but could be detected by monitoring the static current through the power buses. >

Journal ArticleDOI
TL;DR: In this article, a temperature-compensated current reference for CMOS integrated circuits based on a MOSFET as current-defining element is described, which uses no external components nor trimming procedures.
Abstract: A temperature-compensated current reference for CMOS integrated circuits based on a MOSFET as current-defining element, is described. To minimize the mass-production cost, it uses no external components nor trimming procedures. Comparison with classical current references with a resistor as a current-defining element shows a considerable improvement of the relative tolerance on the current. Theoretical expressions are presented and compared with experimental results from an integrated prototype. For devices from the same batch, the standard deviation is measured to be 2.5%, and the temperature dependence is 3% from 0 to 80 degrees C. From theoretical equations, the standard deviation of devices from different batches is expected to be about 15%. >

Journal ArticleDOI
TL;DR: In this paper, a novel process for the fabrication of ion-selective field effect transistors (ISFETs) together with CMOS circuits on the same chip is reported.
Abstract: A novel process for the fabrication of ion-selective field-effect transistors (ISFETs) together with CMOS circuits on the same chip is reported. The process is based on a standard 2- mu m, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFETs are fabricated with floating polysilicon gates, which are exposed to photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si/sub 3/N/sub 4/ acts both as the pH-sensitive insulator for the ISFETs and as a protection layer for the on-chip circuitry buried beneath it. A source-follower circuit is described that provides an output voltage dependent on the threshold-voltage variations of the sensing transistor. >

Journal ArticleDOI
01 Oct 1988
TL;DR: In this article, the authors reviewed the development of the metal-oxide-semiconductor field effect transistor (MOSFET) during the last 60 years, from the 1928 patent disclosures of the field effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon.
Abstract: Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon. MOSFET in 1960. A survey is then made of the milestones of the past 30 years leading to the latest submicron silicon logic CMOS (complementary MOS) and BICMOS (bipolar-junction transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. The status of the submicron lithographic technologies is summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. The use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. >

Journal ArticleDOI
TL;DR: In this article, a VLSI-compatible CMOS comparator for high-speed applications is presented, where voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier.
Abstract: The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2- mu m CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. >

Journal ArticleDOI
TL;DR: In this paper, a continuous-time all-MOS universal filter structure is proposed, which achieves complete MOS nonlinearity cancellation and does not require the use of fully balanced op-amps.
Abstract: A continuous-time all-MOS universal filter structure is proposed. The structure is based on the MOSFET-C design approach. It achieves complete MOS nonlinearity cancellation and does not require the use of fully balanced op-amps. General topological requirements are established that are necessary for the conversion of active-RC prototypes to MOSFET-C counterparts, such that MOS nonlinearity cancellation is achieved. Accordingly, a universal active-RC prototype filter structure, which meets the necessary requirements, is presented and its MOSFET-C version is developed. Nonideal effects that may degrade the performance at high frequency are discussed and ways for improvement are proposed. Results obtained from a test chip have verified the viability of the proposed structures. The chip is an implementation of a MOSFET-C universal filter in a 3.5- mu m CMOS process. The filter is successfully tuned over a wide range of pole frequencies (0 to 100 kHz) using op-amps with a measured gain bandwidth of only 1.2 MHz. >

Patent
04 Jan 1988
TL;DR: In this article, a system for transmitting digital signals over a transmission line including a driver of an inverter employing CMOS FET's and a termination of a CFI employing CFI's is described.
Abstract: A system for transmitting digital signals over a transmission line including a driver of an inverter employing CMOS FET's and a termination of an inverter employing CMOS FET's A sense/control circuit at the termination senses changes in the operating condition of the driver inverter and in response thereto controls the operating condition of the termination inverter Under steady state conditions the termination inverter establishes the appropriate voltage at an output connection coupled thereto without dissipating any power

Journal ArticleDOI
01 Nov 1988
TL;DR: In this article, the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on micro-electronic ICs.
Abstract: Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ICs. >

Journal ArticleDOI
E. Sackinger1, W. Guggenbuhl1
TL;DR: The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed and a simple trimming circuit based on this principle and delivering a differential current is described.
Abstract: The application of floating-gate elements as adjustable components in analog CMOS circuits such as amplifiers is proposed. A simple trimming circuit based on this principle and delivering a differential current is described. Experimental results of a differential difference amplifier (DDA) containing two such circuits are given. After trimming, an offset voltage of 10 mu V and a nonlinearity of 0.1% are achieved. Other analog circuits based on floating-gate elements like adjustable voltage sources and transconductances have been realized. Because they can be electrically reprogrammed, a wide range of applications, for example in neural nets, are possible. >

Journal ArticleDOI
TL;DR: In this article, a 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology, which is half that of the corresponding binary CMOS multiplier.
Abstract: A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported. >

Journal ArticleDOI
TL;DR: A key feature of this design is the inclusion of on-chip sparse read-out circuitry, which allows efficient management of low-occupancy events.
Abstract: A full-custom CMOS integrated circuit for silicon strip detector systems has been designed, fabricated, and tested. The circuit contains 128 parallel data-acquisition channels and considerable peripheral circuitry. Each channel consists of a low-noise, low-power, charge-sensitive amplifier, a multistage autobalanced comparator, an analog multiplexer, nearest-neighbor logic, priority-search logic, and a share of a position-encoding read-only memory. The analog system can substract both detector pedestal and leakage current on a channel-by-channel basis. A key feature of this design is the inclusion of on-chip sparse read-out circuitry, which allows efficient management of low-occupancy events. Designed for use at the Collider Detector Facility (CDF) at Fermilab, the circuit is suitable for large-scale silicon detector systems requiring a large, dense array of fast, low-power electronics. >

Proceedings ArticleDOI
16 May 1988
TL;DR: A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations.
Abstract: A description is given of ILAC (Interactive Layout of Analog CMOS Circuits), a CAD (computer-aided design) tool that automatically generates geometrical layout for analog CMOS leaf cells from netlist information and user-specified constraints on cell bounds and input/output locations. ILAC is the companion tool of IDAC, a design tool that sizes analog CMOS circuits from a library of proven schematics given a set of functional specifications and technological parameters. Unlike existing analog silicon compilers that use some predefined placement for a specific type of circuit, ILAC determines an optimal layout for any circuit and any set of input parameters. >

Journal ArticleDOI
TL;DR: A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3- mu m, CMOS technology.
Abstract: A pipelined, 13-bit, 250-ksample/s (ks/s), 5-V, analog-to-digital (A/D) converter has been designed and fabricated in a 3- mu m, CMOS technology Monotonicity is achieved using a reference-feedforward correction technique instead of (self-) calibration of trimming to minimize the overall cost The prototype converter requires 3400 mil/sup 2/, and consumes 15 mW >

Patent
05 Feb 1988
TL;DR: In this article, a method for scanning information off a processing plane where the information is contained in a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude.
Abstract: There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage. The negative feedback to the inverting input coupled to the column line stabilizes the voltage on the column line to virtual ground thereby eliminating the delay associated with driving the parasitic capacitance of the column line with the very small output current from the processor in an attempt to substantially change the voltage of the column line.

Journal ArticleDOI
TL;DR: In this article, the integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers.
Abstract: Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2- mu m gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1- mu m gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated. >

Proceedings ArticleDOI
27 Jun 1988
TL;DR: The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test.
Abstract: The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable. >

Journal ArticleDOI
TL;DR: The effectiveness of the 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology is established.
Abstract: A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology. The multiplier can perform 32-bit two's-complement multiplication with three-stage SD full adders using a binary-tree addition scheme The effective multiplier size in the chip and the power dissipation are almost half that of the corresponding binary CMOS multiplier. The multiply time is comparable to that of the fastest binary multiplier. These results establish the effectiveness of the technology for future very large scale integration. >

Proceedings ArticleDOI
03 Oct 1988
TL;DR: It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process and the presented design was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution.
Abstract: Built-in current (BIC) testing involves the monitoring of power bus currents in a VLSI circuit, as a means of detecting processing defects in the circuit. The design and performance of a prototype BIC sensor for static CMOS are discussed. It has been demonstrated that a fully-operational BIC sensor can be designed using a standard CMOS process. The presented design met all basic requirements: it was small, it caused only a small degradation of the performance of the monitored module, and it provided sufficient current resolution. The main disadvantage of the described design, however, was a substrate current caused by the structure of the bipolar transistor. >

Journal ArticleDOI
TL;DR: In this article, a dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns.
Abstract: A dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time. >