Showing papers on "CMOS published in 1989"

An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses

Abstract: The use of floating-gate nonvolatile memory technology for analog storage of connection strengths, or weights, has previously been proposed and demonstrated. The authors report the analog storage and multiply characteristics of a new floating-gate synapse and further discuss the architecture of a neural network which uses this synapse cell. In the architecture described 8192 synapses are used to interconnect 64 neurons fully and to connect the 64 neurons to each of 64 inputs. Each synapse in the network multiplies a signed analog voltage by a stored weight and generates a differential current proportional to the product. Differential currents are summed on a pair of bit lines and transferred through a sigmoid function, appearing at the neuron output as an analog voltage. Input and output levels are compatible for ease in cascade-connecting these devices into multilayer networks. The width and height of weight-change pulses are calculated. The synapse cell size is 2009 mu m/sup 2/ using 1- mu m CMOS EEPROM technology. >

A noise-shaping coder topology for 15+ bit converters

Abstract: A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3- mu m CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate. >

ISAAC: a symbolic simulator for analog integrated circuits

Abstract: The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm. >

A self-calibration technique for monolithic high-resolution D/A converters

Abstract: A self-calibration technique based upon charge storage on the gate-source capacitance of CMOS transistors is presented. The technique can produce multiple copies of a reference current. Therefore, it is suitable for the calibration of high-resolution D/A (digital/analog) converters which are based upon equal current sources. As the storage capacitor is internal, no external components are required. A calibrated spare current source is used to allow continuous converter operation. This implies that no special calibration cycles are required. To show the capabilities of the calibration technique, it was implemented in a 16-b D/A converter. Measurement results show a total harmonic distortion of 0.0025% at a power consumption of 20 mW and a minimum supply voltage of 3 V. The design was fabricated in a 1.6- mu m double-metal CMOS process without special options. >

Development and electrical properties of undoped polycrystalline silicon thin-film transistors

Abstract: The conduction mechanism and the origins of the leakage current in undoped channel polycrystalline silicon thin-film transistors fabricated under a variety of processing conditions were investigated. Leakage currents below 1 nA at drain-source voltages of 40 V were achieved in both n-type and p-type devices. The effective channel electron and hole mobilities were 75 and 42 cm/sup 2//V-s, respectively. Measured stage delay times for CMOS ring oscillators as a function of supply voltage agreed well with theoretical calculations. The effective carrier mobility was shown to have a minimum at a gate voltage corresponding to the point at which all traps are filled. Both dark and photoinduced leakage currents were determined to be controlled by generation from the grain boundary traps. The voltage drop across individual gates in multigated structures was investigated as a function of gate voltage. The use of multiple gates at high drain-source potentials was found to decrease both dark and photoinduced leakage currents. >

Trimming analog circuits using floating-gate analog MOS memory

Abstract: A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100 degrees C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV. >

ILAC: an automated layout tool for analog CMOS circuits

Abstract: ILAC (interactive layout of analog CMOS circuits) is a process-independent tool that automatically generates geometrical layout for analog CMOS cells from a circuit description. ILAC handles typical analog layout constraints such as device matching, symmetry, and distance and coupling constraints. ILAC supports user-specified constraints on cell height and input/output pin locations. Together with the design tool IDAC (interactive design for analog circuits), ILAC makes a fully functional analog CMOS cell compiler that automatically produces geometrical layout from functional specifications for a library of circuits including amplifiers, voltage and current references, comparators, oscillators, and A/D (analog-to-digital) converters. >

Operational transconductance amplifier-based nonlinear function syntheses

Abstract: It is shown that the operational transconductance amplifier, as the active element in basic building blocks, can be efficiently used for programmable nonlinear continuous-time function synthesis. Two efficient nonlinear function synthesis approaches are presented. The first approach is a rational approximation, and the second is a piecewise-linear approach. Test circuits have been fabricated using a 3- mu m p-well CMOS process. The flexibility of the designed and tested circuits was confirmed. >

MOS Switched-Capacitor and Continuous-Time Integrated Circuits and Systems: Analysis and Design

Abstract: Contents: Fundamentals of Sampled-Data Systems * MOS Devices for Linear Analog Integrated Circuits * Basic Properties and Systematic Analysis of Switched-Capacitor Networks * Basic Building Blocks of Linear SC Networks * Synthesis and Design of SC Filters * Design of Adaptive and Nonlinear Analog CMOS Circuits: Building Block Approach * CMOS Analog to Digital and Digital to Analog Conversion Systems * Subject Index.

Quiescent power supply current measurement for CMOS IC defect detection

Abstract: Quiescent power supply current (I/sub DDQ/) measurement is a very effective technique for detecting in CMOS integrated circuits (ICs). This technique uniquely detects certain CMOS IC defects such as gate oxide shorts, defective p-n junctions, and parasitic transistor leakage. In addition, I/sub DDQ/ monitoring will detect all stuck-at faults with the advantage of using a node toggling test set that has fewer test vectors than a stuck-at test set. Individual CMOS ICs from three different fabrication sites had a unique pattern or fingerprint of elevated I/sub DDQ/ states for a given test set. When I/sub DDQ/ testing was added to conventional functional test sets, the percentage increase in failures ranged from 60% to 182% for a sample of microprocessor, RAM, and ROM CMOS ICs. >

Metastability behavior of CMOS ASIC flip-flops in theory and test

Abstract: Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules. >

Electrical properties and detection methods for CMOS IC defects

Abstract: CMOS failure modes and mechanisms and the test vector and parametric test requirements for the detection are reviewed. The CMOS stuck-open fault is discussed from a physical viewpoint, with results given from failure analysis of ICs having this failure mode. The results show that among functional, stuck-at, stuck-open, and I/sub DDQ/ test strategies, no single method guarantees detection of all types of CMOS defects. The I/sub DDQ/ test is the most sensitive and comprehensive, but can miss certain open-circuit defects and is a relatively slow measurement technique. The test-vector approach detects fewer of the CMOS defects, but can run at fast clock rates to detect certain open-circuit faults that may not be detectable by the I/sub DDQ/ test. Maximal CMOS IC defect detection involves a mixed-mode strategy of I/sub DDQ/ tests and vector stimulus/response tests. >

BOLD: The Boulder Optimal Logic Design system

Abstract: The BOLD (Boulder-Optimal Logic Design) system is a set of software tools that optimally transform an arbitrary combinational logic description into a standard cell, gate array, or complex CMOS gate technology. The design philosophy and structure of BOLD are summarized, and the various software tools and algorithms that comprise the BOLD system are described. The input to BOLD is either a behavioral circuit description or a Logical Interchange Format (LIF) file. The output is a netlist consisting of gates from a user supplied library or a netlist of CMOS complex gates. The philosophy of BOLD is contrasted with that of other available synthesis programs (most notably MIS and YLE), and the output of each is compared on a small set of examples. >

A 10-bit 5-Msample/s CMOS two-step flash ADC

Abstract: A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

Three dimensional ICs, having four stacked active device layers

Abstract: The four-layer-stacked master slice is proposed as a system application for 3-D ICs. The master slice consists of a programmable logic array for logic circuits, a CMOS gate array for I/O interface buffer circuits, and a CMOS SRAM. Fabrication technologies for the four-layer-stacked 3-D IC are described. Laser beam recrystallization was carried out for the formation of three SOI (silicon-on-insulator) layers in the 3-D IC. Recrystallization without cracks in both SOI and vertical isolation layers was accomplished by adjusting laser annealing conditions. Microprobe Raman spectroscopy data indicated that a tensile stress of (3-6)*10/sup 9/ dyne/cm/sup 2/ was present in each SOI layer. Surface planarization of the vertical isolation layer was carried out with a combination of polystyrene spin coating and dry etching. An initial surface roughness of about 1.7 mu m was successfully reduced to less than 500 A, and the planarized surface did not interfere with either recrystallization or photolithography. NMOSFETs and PMOSFETs, fabricated in the four-layer-stacked 3-D IC, have been successfully operated. >

A CMOS electrically configurable gate array

Abstract: A CMOS electrically configurable gate array that combines the flexibility, efficiency, extendability, and performance of mask-programmed gate arrays with the convenience of user programmability is described. The implementation is facilitated by a novel two-terminal antifuse programmable element and a configurable interconnect technology. The chip has been fabricated using 2- mu m n-well CMOS technology with two-layer metallization. >

A 200-MHz CMOS phase-locked loop with dual phase detectors

Abstract: A high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented. The design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase-frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2- mu m CMOS p-well process was used to fabricate the circuit. The loop can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply. The oscillator is a ring of three inverting amplifiers and draws from an internal supply voltage regulated by an on-chip bandgap reference. This combination serves to reduce the supply and temperature sensitivity is less than 5%/V, and the oscillator temperature variation is 2.2% in the range of 25 to 80 degrees C. The typical oscillator tuning range is 112 to 209 MHz. The multiplying phase detector and phase-frequency detector exhibit input-referred phase offsets of >

Implementing neural architectures using analog VLSI circuits

Abstract: Analog very large-scale integrated (VLSI) technology can be used not only to study and simulate biological systems, but also to emulate them in designing artificial sensory systems. A methodology for building these systems in CMOS VLSI technology has been developed using analog micropower circuit elements that can be hierarchically combined. Using this methodology, experimental VLSI chips of visual and motor subsystems have been designed and fabricated. These chips exhibit behavior similar to that of biological systems, and perform computations useful for artificial sensory systems. >

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation

Abstract: The development is described of a sigma-delta A/D (analog-to-digital) converter Included is a brief overview of sigma-delta conversion The A/D converter achieves an 885-dB dynamic range and a maximum signal-to-noise ratio of 815 dB The harmonic distortion is negligible This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 1024 MHz Transconductance amplifiers having a 160-MHz f/sub t/ were developed for the integrators The circuit is implemented in a 175- mu m 5-V CMOS process The analog circuitry occupies 2 mm/sup 2/ of silicon area and consumes 75 mW of power Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described The design of a sigma-delta development and performance evaluation system is presented This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software >

Dummy transistor compensation of analog MOS switches

Abstract: Theoretical and experimental results of the clock-feedthrough phenomenon (charge injection) in sample-and-hold circuits using minimum features size transistors of a self-aligned 3 mu m CMOS technology are compared. The lumped RC model of the conductive channel is used and verified in different switch configurations with variable input voltages. Special emphasis is placed on the feasibility and limits of charge cancellation techniques using dummy switches. >

A set of four ICs in CMOS technology for a programmable hearing aid

Abstract: A four-chip system developed for a programmable hearing aid is presented. It combines E/sup 2/PROM (electrically erasable programmable read-only memory) memories with a control logic, low-noise preamplifiers, AGC (automatic gain control) amplifiers, SC (switched-capacitor) filters, voltage multipliers, and an output amplifier of the pulse-width type. The implementation of the critical parts is explained. The 3- mu m self-aligned-contacts MOS technology of the Faselec company is used. The system is supplied by a single 1.3-V battery and its typical current consumption is 1.5 mA. The whole system can be connected to a computer. >

A 17 bit oversampling D-A conversion technology using multistage noise shaping

Abstract: A description is given of a highly stable, triple-integration two-stage noise-shaping technique and a precise differential pulse-width modulation (PWM) output method which permits greater accuracy in monolithic audio digital-to-analog (D-to-A) converters (DACs) without trimming. Based on these techniques and using 1.5 mu m CMOS technology, a 17 bit 20 kHz bandwidth DAC LSI chip with digital filters was developed. A signal-to-noise ratio (S/(N+THD)) of 101 dB and a total harmonic distortion (THD) of 0.0007% at full-scale input were obtained. >

CMOS IC stuck-open-fault electrical effects and design considerations

Abstract: The authors evaluate CMOS IC stuck-open-fault electrical effects, including voltage levels, quiescent power supply current (I/sub DDQ/), transient response, and important testing considerations. The transient responses of the defective node voltage and power supply current to the high-impedance state caused by a stuck-open defect were measured to determine if the I/sub DDQ/ measurement technique could detect stuck-open faults. The measured transient response of stuck-open faults shows that this defect acts as a memory fault for normal system and tester clock periods. The data also show that detectable elevated I/sub DDQ/ can occur rapidly for some circuit designs. Elevated I/sub DDQ/ can also occur over many clock cycles as the high-impedance node associated with the stuck-open fault undergoes a drift in its voltage. The I/sub DDQ/ technique is interpreted as significantly enhancing the detection of stuck-open defects, but not guaranteeing their detection. Modifications to the circuit layout to reduce the probability of stuck-open-fault occurrence are presented. >

Linear CMOS transconductance element for VHF filters

Abstract: A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, Vipp=1.8 V), nondominant poles in the gigahertz range and a 40 dB DC gain

A CMOS-integrated 'ISFET-operational amplifier' chemical sensor employing differential sensing

Abstract: The ISFET (ion-sensitive field-effect transistor) pH sensor is first matched with a MOSFET at the differential input stage of a CMOS operational amplifier (called the ISFET-operational amplifier) to cancel out the temperature sensitivity. Then, the output of an ISFET-operational amplifier with a Ta/sub 2/O/sub 5//SiO/sub 2/ gate (58-59 mV/pH) ISFET is differentially amplified against the output of another on-chip ISFET-operational amplifier with a SiO/sub x/N/sub y//Si/sub 3/N/sub 4//SiO/sub 2/ gate ISFET (18-20-mV/pH). An on-chip noble metal counterelectrode serves as the electrical contact to define the electric potential of the electrolyte. No external reference electrode is required. The difference measurement technique achieves (1) common-mode rejection of the solution potential, and (2) relaxation of the requirement that the on-chip reference electrode be ideal. The CMOS-compatible ISFET process is modified from a standard self-aligned polysilicon gate CMOS process with minimal process redesign. The standard CMOS sequence is unaltered until the contact windows are opened. The complete sensor has 40-43-mV/pH pH sensitivity and demonstrates common-mode rejection to ambient light and noise from the electrolyte. >

CMOS power-on reset circuit

Abstract: The output signal of a CMOS power-on reset circuit changes state upon detecting a predetermined threshold of the power supply voltage during the start-up transient. During the power-up of the power supply voltage, the output signal of the power-on reset circuit ramps up with the power supply voltage until the latter reaches a first predetermined level whereat a control signal begins to track the increasing power supply voltage, less two diodes potentials. Upon reaching the turn-on potential of a transistor, the control signal activates an inverter to substantially reduce the output signal signifying that the power supply voltage level is sufficient for the operation of external circuitry. The output signal then disables the current flowing through the power-on reset circuit to save power consumption.

Future trends for TFT integrated circuits on glass substrates

Abstract: The current status and the future trends of thin-film-transistor (TFT) integrated circuits are discussed following a review of their features TFT devices have been applied to liquid-crystal displays and linear image sensors, both of which incorporate internally integrated driver circuits From the viewpoint of TFT advantages, the low-temperature ( >

CMOS digital level shifter circuit

Abstract: The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS

Abstract: A variable-gain amplifier (VGA) with a gain range of 50 dB has been implemented in a standard 3 mu m CMOS process using parasitic lateral and vertical bipolar transistors to form the core of the circuit. The bipolar transistors had been characterized extensively. The VGA has a bandwidth larger than 3 MHz over the whole gain range and operates on a single 5 V power supply. The active area is about 0.8*0.9 mm/sup 2/. >