Showing papers on "CMOS published in 1991"

Architecture and process for integrating DMD with control circuit substrates

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Two novel fully complementary self-biased CMOS differential amplifiers

Abstract: Two CMOS differential amplifiers, one that is intended for applications in which the input common-mode range is relatively limited, the complementary self-biased differential amplifier (CSDA), and one that is intended for applications in which the input common-mode range is bounded only by the supply voltages, the very-wide-common-mode-range differential amplifier (VCDA), are discussed. Both differ from conventional CMOS differential amplifiers in having fully complementary configurations and in being self-biased through negative feedback. The amplifiers have been applied as precision high-speed comparators in commercial VLSI CMOS integrated circuits. >

Current-mode subthreshold MOS circuits for analog VLSI neural systems

Abstract: An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed. >

Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's

Abstract: The speed of VLSI chips is increasingly limited by signal delay in long interconnect lines. A simple analysis shows that major speed improvements are possible when using current-mode rather than conventional voltage-mode signal transporting techniques. The key to this approach is the use of low-resistance current-signal circuits to drastically reduce the impedance level and the voltage swings on long interconnect lines. As an example, a simple four-transistor current-sense amplifier for fast CMOS SRAMs is proposed. The circuit presents a virtual short circuit to the bit lines, thus reducing the sensing delay, which is rendered practically insensitive to the bit-line capacitance. In addition, the virtual short circuit ensures equal bit-line voltages, thus eliminating the need for bit-line equalization during a read access. >

KOAN/ANAGRAM II: new tools for device-level analog placement and routing

Abstract: The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented. >

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

Abstract: A novel silicon-controlled rectifier (SCR) structure for on-chip protection against electrostatic discharge (ESD) stress at output or input pads is presented. The SCR switches to an ON state at a trigger voltage determined by the gate length of an incorporated nMOS-like structure. Thus, the new SCR can be designed to consistently trigger at a voltage low enough to protect nMOS transistors from ESD. The capability of a protection circuit using the new SCR design is experimentally demonstrated. The tunability of the SCR trigger voltage with reference to the nMOS breakdown voltage is exploited to improve the human body model (HBM) ESD failure threshold of an output buffer from 1500 to 5000 V. >

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Abstract: A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS

Abstract: Described is a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3- mu m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s. consumes 100 mW, and occupies 40 kmil/sup 2/ (26 mm/sup 2/), with a single 5-V supply and two-phase nonoverlapping clock. >

A multiple modulator fractional divider

Abstract: Fractional-N frequency synthesis using a phase locked loop (PLL) is considered. Advances in oversampling A/D conversion technology are incorporated into fractional-N synthesis, allowing the spectrum of error energy to be shaped so that fractional synthesis error energy is pushed away from the carrier. Based on this new technology, a CMOS integrated fractional-N divider was successfully developed. A complete fractional-N PLL was constructed utilizing only a CMOS divider, a dual modulus prescaler, a simple loop filter, and a voltage controlled oscillator (VCO). The resulting PLL exhibits no fractional spurs. >

Delay analysis of series-connected MOSFET circuits

Abstract: In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the V/sub DS/ and V/sub GS/ of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2- mu m designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N/sup 2/. The delay dependence on input terminal position for SCMS structures is also described. >

An experimental 1.5-V 64-Mb DRAM

Abstract: Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs. >

Realization of high breakdown voltage (>700 V) in thin SOI devices

Abstract: The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip. >

A 150-MHz Direct Digital Frequency Synthesizer In 1.25/spl mu/m CMOS With -90dBc Spurious Performance

Abstract: A monolithic CMOS direct digital frequency synthesizer (DDFS) is presented which simultaneously achieves high spectral purity and wide bandwidth. Phase noise of the output sine wave is equivalent to or better than that of the 150-MHz reference clock. The synthesizer covers a bandwidth from DC to 75 MHz in steps of 0.035 Hz with a switching speed of 6.7 ns and a tuning latency of 13 clock cycles. An efficient look-up table method for calculating the sine function reduces ROM storage requirements by a factor of 128:1. All circuit designs are fully static and are tolerant to transistor threshold shifts caused by radiation or process variations. The DDFS was fabricated in a 1.25- mu m radiation-hardened double-level metal bulk P-well CMOS process which is tolerant to over 10/sup 6/ rd(Si) of total dose radiation. The die size is 195 mil*195 mil with a device count of 35,000 transistors. Power dissipation is 950 mW at a clock rate of 100 MHz. >

A Contrast Sensitive Silicon Retina with Reciprocal Synapses

Abstract: The goal of perception is to extract invariant properties of the underlying world. By computing contrast at edges, the retina reduces incident light intensities spanning twelve decades to a twentyfold variation. In one stroke, it solves the dynamic range problem and extracts relative reflectivity, bringing us a step closer to the goal. We have built a contrast-sensitive silicon retina that models all major synaptic interactions in the outer-plexiform layer of the vertebrate retina using current-mode CMOS circuits: namely, reciprocal synapses between cones and horizontal cells, which produce the antagonistic center/surround receptive field, and cone and horizontal cell gap junctions, which determine its size. The chip has 90 × 92 pixels on a 6.8 × 6.9mm die in 2µm n-well technology and is fully functional.

A zero-overhead self-timed 160-ns 54-b CMOS divider

Abstract: The authors describe the design of a custom integrated circuit for the arithmetic operation of division. The chip uses self-timing to avoid the need for high-speed clocks and directly concatenates precharged function blocks without latches. Internal stages form a ring that cycles without any external signaling. The self-timed control introduces no serial overhead, making the total chip latency equal just the combinational logic delays of the data elements. The ring's data path uses embedded completion encoding and generates the mantissa of a 54-b (floating-point IEEE double-precision) result. Fabricated in 1.2- mu m CMOS, the ring occupies 7 mm/sup 2/ and generates a quotient and done indication in 45 to 160 ns, depending on the particular data operands. >

Simultaneous switching ground noise calculation for packaged CMOS devices

Abstract: Here, it is assumed that the internal switching current is small compared to the output driver switching current. In the past, it was assumed that simultaneous switching noise created by CMOS outputs was directly proportional to the number of outputs switching simultaneously. Recent studies indicate that CMOS circuits exhibit sublinear behavior (due to the negative feedback influence) of power/ground noise (or bounce) as a function of the number of outputs switching simultaneously. Detailed electrical models, equations, and a trial architecture for calculating the switching noise are included. The results are compared to SPICE simulations and conventional power/ground noise calculations. The behavior of simultaneous switching noise as a function of constant-voltage (CV) device scaling is explained for small-geometry CMOS output drivers. >

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion

Abstract: The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta ( Sigma Delta ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1- mu m CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming. >

High-gain lateral bipolar action in a MOSFET structure

Abstract: A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Design of a 15-MHz CMOS continuous-time filter with on-chip tuning

Abstract: A fifth-order CMOS continuous-time Bessel filter with a tunable 6- to 15-MHz cutoff frequency is described. This fully balanced transconductance-capacitor (G/sub m/-C) leapfrog filter achieves a dynamic range of 55 dB while dissipating 96 mW in a 5-V 0.9- mu m CMOS process. The author reviews the disk drive application and filtering requirements, and explains why the G/sub m/-C continuous-time filtering approach was used. The on-chip master-slave tuning system uses a voltage-controlled oscillator (VCO). Experimental results are presented. >

Accurate CMOS-based current conveyors

Abstract: An integrable circuit technique for implementing both positive and negative second-generation current conveyors (CCII) is described. Since the proposed circuits consist of a differential pair, current sources, and current mirrors, the realization method can result in a fully integrated current conveyor. The realization method is suitable for fabrication in CMOS technology. The performance of the CMOS-based CCIIs is discussed in detail. The basic performances are demonstrated and simulation and experimental results are presented. The DC transfer characteristics for converting resistors are linear over the total dynamic range. >

A 10-b 70-MS/s CMOS D/A converter

Abstract: A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than +or-0.5 LSB. The settling time to +or-0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm*1.87 mm. >

A CMOS field-programmable analog array

Abstract: The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2- mu m CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array. >

"resistive shorts" within cmos gates

Abstract: This paper studies the effects of shorts within CMOS gates Dynamic as well as static gate properties are analyzed as a function of the short’s resistance Increased propagation delay is found to be a common dynamic effect Circuit behavior can change drastically with small variations in a short’s resistance It is found that faults caused by transistor gate-to-source and gate-to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals This pattern dependence due to “resistive shorts” can invalidate tests generated using normal TPG procedures

Test Pattern Generation for Realistic Bridge Faults in CMOS ICs

Abstract: Two approaches have been used to balance the cost of generating effective tests for IC's and the need to increase the quality level of shipped IC's. The first approach favors using high-level fault models to reduce test generation costs, and the second approach favors the use of low-level, technology-specific fault models that lead to high test generation costs, but increased defect coverage in the tested circuits. In this paper we simulate complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck-at test sets. Next, we show how low-level bridge fault models can be incorporated into high-level test generation. Finally, we describe our system for generating effective tests for bridge faults and report on its performance.

Manufacturable local interconnect technology fully compatible with titanium salicide process

Abstract: Local interconnect technology has been widely accepted because of advantages such as increase of packing density and reduction of parasitics. Local interconnect technology of a new structure utilizing TiSi/sub 2/ from the reaction of Ti and polysilicon is described. The technology is fully compatible with the salicide process. Moreover, the processing offers low resistivity interconnection with low junction leakage because of its inherent structure. It is confirmed that the process is manufacturable for 0.5 mu m CMOS. >

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

Abstract: The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

A self-convergence erasing scheme for a simple stacked gate flash EEPROM

Abstract: A novel erasing method for simple stacked gate flash EEPROMs is described. The method makes use of avalanche hot carrier injection after erasure by Fowler-Nordheim tunneling. The threshold voltages converge to a certain 'steady-state' as a result of the injection. The steady-state is caused by a balance between avalanche hot electron injection into the floating gate and avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping. Tight distribution of threshold voltages and stable erasure without over-erased cells are demonstrated by applying cells using 0.6- mu m CMOS technology. In addition, short erase time is realized using the novel erase sequence. >

A CNN chip for connected component detection

Abstract: The first working chips that implement a cellular neural network (CNN) are reported. They have been integrated in a CMOS 2- mu m technology, and are intended for connected component detection processing applications. The operation is made in continuous time using analog circuitry. The design, fabrication, and testing of these chips are presented. >

Performance comparison between optoelectronic and VLSI multistage interconnection networks

Abstract: The performance characteristics of optoelectronic and VLSI multistage interconnection networks are compared The bases of the comparison include speed, bandwidth, power consumption, and footprint area The communication network used in the comparison is a synchronous packet-switched multistage interconnection network built from 2*2 bit-serial switching elements CMOS technology was used in the VLSI implementation, and it is assumed that the entire network resides on a single chip Regular free-space optical interconnects are used in the optoelectronic implementation The results show that for large networks optoelectronics offers higher speed and lower area than VLSI Based on the assumed technology parameters, optoelectronics outperforms VLSI in bandwidth for network sizes above 256 >

CMOS low noise amplifier for microstrip readout Design and results

Abstract: A low noise preamplifier and shaper chip has been designed and built in 1.5 μm CMOS technology to be used for readout of Si microstrip detectors. The chip is optimized with respect to noise. Measurements on the performance of the prototype chip are presented. A noise performance of ENC = 160 e − + 12 e − /pF has been achieved.