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Showing papers on "CMOS published in 1993"


Journal ArticleDOI
TL;DR: In this paper, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. But the authors did not consider the effect of the layout geometry of the substrate.
Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

603 citations


Journal Article
TL;DR: In this article, the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate were observed. And the authors showed that in such cases the substrate noise is highly dependent on layout geometry.
Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

567 citations


Journal ArticleDOI
TL;DR: In this paper, large spiral inductors encased in oxide over silicon are shown to operate beyond the UHF band when the capacitance and loss resistance are greatly reduced by selective removal of the underlying substrate.
Abstract: Large spiral inductors encased in oxide over silicon are shown to operate beyond the UHF band when the capacitance and loss resistance are greatly reduced by selective removal of the underlying substrate. Using a 100-nH inductor whose self-resonance lies at 3 GHz, a balanced tuned amplifier with a gain of 14 dB centered at 770 MHz has been implemented in a standard digital 2- mu m CMOS IC process. The core amplifier noise figure is 6 dB, and the power dissipation is 7 mW for a 3-V supply. >

551 citations


Journal ArticleDOI
TL;DR: In this paper, the basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed, and the accuracy of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated.
Abstract: The basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measurement. >

242 citations


Journal ArticleDOI
01 Nov 1993
TL;DR: A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path and the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU.
Abstract: Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

221 citations


Journal ArticleDOI
Ralph C. Merkle1
TL;DR: In this paper, two methods of using switches to implement reversible computations are discussed, one is basically an extension to "pass logic" which has been previously used with both nMOS and CMOS transmission gates to achieve low energy dissipation.
Abstract: Two methods of using switches to implement reversible computations are discussed. The first method has an energy dissipation which is proportional to the square of the error in the voltage, while the second method has an energy dissipation which can in principle be reduced indefinitely by slowing the speed of computation. The first method is basically an extension to 'pass logic' which has been previously used with both nMOS (hot clock nMOS) and CMOS transmission gates to achieve low energy dissipation. The second method is a novel thermodynamically reversible logic system based on CCD-like operations which switches charge packets in a reversible fashion to achieve low energy dissipation.

196 citations


Journal ArticleDOI
TL;DR: In this paper, a unified, comprehensive approach to the design of continuous-time and discrete-time cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented.
Abstract: A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

192 citations


Proceedings ArticleDOI
07 Nov 1993
TL;DR: A method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit is given.
Abstract: Switching activity is the primary cause of power dissipation in CMOS combinational and sequential circuits. We give a method of estimating power in pipelined sequential CMOS circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. We present a retiming method that targets the power dissipation of a sequential circuit.

188 citations


Proceedings ArticleDOI
06 Apr 1993
TL;DR: The Carafe software package is discussed, which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology.
Abstract: Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults in CMOS circuits. As a result, tests based on traditional fault models may not detect all the faults that occur in the circuit. This paper discusses the Carafe software package which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology. >

188 citations


Proceedings ArticleDOI
17 Oct 1993
TL;DR: It is shown that at certain much-lower-than-normal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function.
Abstract: In this paper we propose a very-low-voltage (VLV) testing technique for CMOS logic ICs. Voltage dependence of CMOS logic circuit operation in the presence of resistive shorts and hot carrier damage is studied. It is shown that at certain much-lower-than-normal power supply voltage, weak CMOS logic ICs due to the presence of these flaws can be forced to malfunction while truly good ICs continue to function. Very-low-voltage testing also detects pattern dependent faults caused by resistive shorts. Because of its simplicity and because there is no overhead associated with it, very-low-voltage testing can easily be applied to chips and circuit boards as a production test, field test, or failure diagnosis technique. >

178 citations


Proceedings ArticleDOI
01 Jul 1993
TL;DR: This paper generates a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum and performs a power efficient technology mapping that finds an optimal power-delay trade-off value for given timing constraints.
Abstract: In this paper, we address the problem of minimizing the average power dissipation during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. Our power-efficient decomposition procedure is optimal for dynamic CMOS circuits with uncorrelated input signals and produces very good results for static CMOS. In the second step, we perform a power efficient technology mapping that finds an optimal power-delay trade-off value (subject to the unknown load problem) for given timing constraints. We obtain an average of 21% improvement in power at the expense of 12.6% increase in area and without any degradation in performance on a number of benchmarks.

Journal ArticleDOI
TL;DR: It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters, and a graphical technique called the floating-gate potential diagram has been developed to facilitate logic design employing this transistor.
Abstract: Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor ( nu MOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage nu MOS inverters. One of the most striking features of nu MOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified. >

Journal ArticleDOI
19 May 1993
TL;DR: In this paper, a switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of sub-threshold current with threshold-voltage scaling.
Abstract: A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSI's operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSI's will be possible even at room temperature and above. >

Journal ArticleDOI
TL;DR: A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented and a key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology.
Abstract: A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >

Proceedings ArticleDOI
17 Oct 1993
TL;DR: A general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation.
Abstract: In order to simulate the effects of bridging faults correctly it is necessary to take into account the fact that not all gate inputs have the same logic threshold. This paper presents a general technique which can be used to determine if a particular structure of transistors gives rise to a bridge voltage which is higher or lower than a given threshold, in most cases without requiring circuit simulation. If desired, the technique can also be used to predict actual voltages, which agree well with SPICE simulations. The approach is substantially faster than previous approaches for accurately simulating bridging faults. >

Proceedings Article
01 Sep 1993
TL;DR: In this article, a linear, closed loop CMOS architecture is demonstrated for the mixing of RF waveforms to baseband as sampled-data signals, and the measured third-order intercept lies at +27 dBm of input power.
Abstract: A highly linear, closed loop CMOS architecture is demonstrated for the mixing of RF waveforms to baseband as sampled-data signals. In converting a 915 MHz RF waveform to a 20 MHz spread spectrum baseband signal, the measured third-order intercept lies at +27 dBm of input power. As the 1-?m CMOS prototype dissipates only 12 mW from a 5V supply, and is capable of operation at 3V, it is expected to be of use in advanced handheld wireless receivers.

Journal ArticleDOI
01 Mar 1993
TL;DR: In this article, the authors presented design considerations for high-frequency CMOS continuous-time current-mode filters with differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance.
Abstract: Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 mu m n-well CMOS process achieved a -3 dB cutoff frequency (f/sub 0/) of 42 MHz; f/sub 0/ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 mu A. Using a single 5 V power supply with a nominal reference current of 100 mu A, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm/sup 2//pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 mu m n-well CMOS process to verify the implementation of finite transmission zeros. >

Proceedings ArticleDOI
07 Nov 1993
TL;DR: A fast and memory efficient power estimation technique for CMOS circuits which estimates the power consumed due to the glitches based on the notion of tagged transition waveforms and obtains an order of magnitude speed up over an exact method.
Abstract: In CMOS circuits, glitches account for a sizeable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for CMOS circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition waveforms. In particular, we approximate the correlation between transition waveforms for two signal lines by the correlation between the steady state values of these lines. We obtain an order of magnitude speed up over an exact method with an average error of only 1%.


Proceedings ArticleDOI
05 Dec 1993
TL;DR: A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported, and achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements.
Abstract: A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 /spl mu/m p-well CMOS process, and consists of a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community. >

Journal ArticleDOI
01 Dec 1993
TL;DR: Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed, which result in very low power dissipation at a low power-supply voltage at the conversion frequency.
Abstract: This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than +or-0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8- mu m CMOS technology and occupies an area of 2.6*2.5 mm/sup 2/. >

Journal ArticleDOI
TL;DR: In this article, the design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented.
Abstract: The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2- mu m CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks. >

Journal ArticleDOI
TL;DR: An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility as discussed by the authors.
Abstract: An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility. The 2500*2500*3.5 mu m/sup 3/ microphone has a piezoelectric ZnO layer on a supporting low-pressure chemical-vapor-deposited (LPCVD), silicon-rich, silicon nitride layer. The optimum residual-stress-compensation scheme for maximizing microphone sensitivity produces a slightly buckled microphone diaphragm. A model for the sensitivity dependence of device operation to residual stress is confirmed by applying external strain. The packaged microphone has a resonant frequency of 18 kHz, a quality factor Q approximately=40, and an unamplified sensitivity of 0.92 mV/Pa. Differential amplifiers provide 49 dB gain with 13 mu V A-weighted noise at the input. >

Journal ArticleDOI
Henry Baltes1
TL;DR: In this paper, the authors focused on sensor prototypes realized by industrial CMOS IC technology with post-processing micromachining, including thermally excited acoustic resonators, thermoelectric gas flow, infrared, and power sensors.
Abstract: Sensor design and fabrication using industrial IC technologies has the advantages of batch fabrication and on-chip interface circuitry. Sensors made by CMOS or bipolar IC technology have been demonstrated for magnetic, temperature and radiation measurands. Certain thermal, mechanical and chemical sensors can be realized by combining IC technologies with additional, compatible processing. We distinguish the methods of multiple project wafers, single project wafers, post-processing IC chips or wafers, and IC fabrication merged with sensor processing performed before, after, and in-between the regular IC processing steps. This paper is focused on sensor prototypes realized by industrial CMOS IC technology with post-processing micromachining. Examples include thermally excited acoustic resonators, thermoelectric gas flow, infrared, and power sensors, and a thermal conductivity sensor.

Book
30 Nov 1993
TL;DR: In this article, the authors propose an approach to calculate simultaneous switching noise (SSN) in CMOS devices, based on power distribution inductance model and signal conductors over a perforated reference plane.
Abstract: List of Figures. List of Tables. 1. Introduction. 2. Packages/Scaled CMOS Devices. 3. Methods of Calculating Simultaneous Switching Noise (SSN). 4. Power Distribution Inductance Modeling. 5. Signal Conductors over a Perforated Reference Plane. 6. Dynamic Noise Immunity, and Skewing/Damping SSN Waveform. 7. Application Specific Output Drivers to Reduce SSN. 8. SSN Simulator Architecture. 9. Signal Conductors over a Noisy Reference Plane. 10. Conclusions. 11. Discussion and Future Work. Appendices. References. Index.

Journal ArticleDOI
TL;DR: In this paper, a nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise, which is fabricated in a double-metal, single-poly 1.6μm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realize piecewise linear characteristics in the current-mode domain.
Abstract: A nonlinear switched-current circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, single-poly 1.6μm CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to ∼30% of the clock frequency, for a clock frequency of 500kHz.

Journal ArticleDOI
TL;DR: With controlled slew rate output drivers, more than 50% improvement was found in the input receiver noise immunity compared to conventional drivers, while the speed and sink/source capabilities are preserved.
Abstract: Application specific CMOS circuit design techniques to reduce simultaneous switching noise (SSN-also known as Delta-I noise or ground bounce) were analyzed. Detailed investigation on the CMOS output driver switching current components was performed. The limitations in using current controlled (CC) CMOS output drivers in high-speed (>30 MHz) design applications are explained. Application specific, high-speed, controlled slew rate (CSR) CMOS output drivers were studied and designed. For a given device channel length, once the predriver and driver device sizes are fixed, the performance (speed, switching noise, sink/source capabilities) is determined. With controlled slew rate output drivers, more than 50% improvement was found in the input receiver noise immunity (measure of maximum tolerable SSN) compared to conventional drivers, while the speed and sink/source capabilities are preserved. This effective SSN reduction improvement is achieved with only a small increase in output driver silicon area. The CSR output driver uses distributed and weighted switching driver segments to control the output driver's slew rate for a given load-capacitance. These CSR CMOS output drivers were compared with standard CMOS output drivers, showing significant reduction in effective switching noise pulse width. >

Journal ArticleDOI
TL;DR: In this article, the physical interactions of ions with MOS gate oxides-charge generation, recombination, transport, and trapping were examined, and it was concluded that hard errors from single ions are to be expected, and should not be considered surprising.
Abstract: Hard errors from single heavy ions have been reported in advanced commercial CMOS memories. The authors examine the physical interactions of ions with MOS gate oxides-charge generation, recombination, transport, and trapping. They also consider device and circuit characteristics. They conclude that hard errors from single ions are to be expected, and should not be considered surprising. >

Journal ArticleDOI
TL;DR: In this paper, a folded source-coupled logic (FSCL) is proposed to reduce power, delay, and switching noise by using current steering techniques in fully-differential FSCL circuits to maintain a constant power supply current.
Abstract: CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing ( Delta V/sub L/ approximately=0.2 V/sub dd/) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2- mu m CMOS process, and simulated results with a standard 1- mu m process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies. >

Journal ArticleDOI
Dejan Mijuskovic1, M. Bayer1, T. Chomicz1, N. Garg1, F. James1, Philip W. Mcentarfer1, J. Porter1 
09 May 1993
TL;DR: In this paper, a family of standard cells for phase-locked loop (PLL) applications is presented, which are processed using a 1.5 /spl mu/m, n-well, double-polysilicon, double layer metal CMOS process.
Abstract: A family of standard cells for phase-locked loop (PLL) applications is presented. The applications are processed using a 1.5 /spl mu/m, n-well, double-polysilicon, double-layer metal CMOS process. Applications include frequency synthesis for computer clock generation, disk drives, and pixel clock generators for computer monitors, with maximum frequencies up to 80 MHz. The synthesizers require no external components since the loop filter and oscillator are on chip with the phase frequency detector and the charge pump. Special voltage and current reference cells are discussed. Analysis of noise sources in the PLL demonstrates the need for reducing the phase noise of the system. A low phase noise is achieved through supply rejection techniques and by placing the oscillator in a high-gain feedback loop to minimize its noise contributions. Laboratory measurements of completed silicon show synthesizers with exceptionally linear gain, as well as transient responses and phase noise similar to predicted results. >