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Showing papers on "CMOS published in 1995"


Journal ArticleDOI
TL;DR: In this article, a multithreshold-voltage CMOS (MTCMOS) based low-power digital circuit with 0.1-V power supply high-speed low power digital circuit technology was proposed, which has brought about logic gate characteristics of a 1.7ns propagation delay time and 0.3/spl mu/W/MHz/gate power dissipation with a standard load.
Abstract: 1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

1,338 citations


Book
30 Jun 1995
TL;DR: The Hierarchy of Limits of Power J.D. Stratakos, et al., and Low Power Programmable Computation coauthored with M.B. Srivastava, provide a review of the main approaches to Voltage Scaling Approaches.
Abstract: 1. Introduction. 2. Hierarchy of Limits of Power J.D. Meindl. 3. Sources of Power Consumption. 4. Voltage Scaling Approaches. 5. DC Power Supply Design in Portable Systems coauthored with A.J. Stratakos, et al. 6. Adiabatic Switching L. Svensson. 7. Minimizing Switched Capacitance. 8. Computer Aided Design Tools. 9. A Portable Multimedia Terminal. 10. Low Power Programmable Computation coauthored with M.B. Srivastava. 11. Conclusions. Subject Index.

1,024 citations


Journal ArticleDOI
01 Apr 1995
TL;DR: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design and has been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video.
Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

1,023 citations


Journal ArticleDOI
TL;DR: In this article, the bus-invert method of coding the I/O was proposed to decrease the bus activity and thus decrease the peak power dissipation by 50% and the average power disipation by up to 25%.
Abstract: Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power. >

1,011 citations


Book
01 Aug 1995
TL;DR: In this article, the authors provide rigorous treatment of basic design concepts with detailed examples for CMOS digital integrated circuits, including basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low power design techniques, design for manufacturability and design for testability.
Abstract: CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, interconnect effects, dynamic circuits, memory circuits, BiCMOS circuits, I/O circuits, VLSI design methodologies, low-power design techniques, design for manufacturability and design for testability. This book provides rigorous treatment of basic design concepts with detailed examples. It typically addresses both the computer-aided analysis issues and the design issues for most of the circuit examples. Numerous SPICE simulation results are also provided for illustration of basic concepts. Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals of CMOS VLSI design, which is the driving force behind the development of advanced computer hardware. Table of contents 1 Introduction 2 Fabrication of MOSFETS 3 MOS Transistor 4 Modeling of MOS Transistors Using SPICE 5 MOS Inverters: Static Characteristics 6 MOS Inverters: Switching Characteristics and Interconnect Effects 7 Combinational MOS Logic Circuits 8 Sequential MOS Logic Circuits 9 Dynamic Logic Circuits 10 Semiconductor Memories 11 Low-Power CMOS Logic Circuits 12 BiCMOS Logic Circuits 13 Chip Input and Output (I/O) Circuits 14 Design for Manufacturability 15 Design for Testability

888 citations


Journal ArticleDOI
15 Feb 1995
TL;DR: A 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology is described.
Abstract: While the performance of flash memory exceeds hard disk drives in almost every category, the cost of flash memory must come down in order to gain wider acceptance in mass storage applications. This paper describes a 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology. Die size is reduced by eliminating high voltage operation on the bitlines through a self boosted program inhibit voltage generation scheme. Incremental-step-pulse programming results in a 2.3 MB/s program data rate as well as improved process variation tolerance. Interleaved data paths and a boosted wordline results in a 25 ns burst cycle time and a 24 MB/s read data rate. Maximum operating current is less than 8 mA.

720 citations


Journal ArticleDOI
TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Abstract: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >

623 citations


Proceedings Article
01 Jan 1995
TL;DR: In this article, the authors describe a 10 b, 20 µm pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation.
Abstract: ―This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB. Differential input range is ± 1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR.

577 citations


Journal ArticleDOI
TL;DR: In this paper, an analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented, which achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz without requiring any external component or any tuning or trimming.
Abstract: An analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products.

489 citations


Journal ArticleDOI
01 Apr 1995
TL;DR: In this article, a guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past.
Abstract: A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 /spl mu/m channel length at 2.5 V down to sub-0.1 /spl mu/m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7/spl times/ and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 /spl mu/m regime as compared with today's high performance 0.6 /spl mu/m devices at 5 V. However, the power density rises by a factor of 4/spl times/ for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3/spl times/ savings in power compared to the bulk case at the same speed. >

351 citations


Book
01 Jan 1995
TL;DR: This paper presents a methodology for designing low-Voltage Low-Power VLSI CMOS Circuit Design that addresses the challenge of integrating low-voltage components into a coherent system.
Abstract: Preface. 1. Low-Power VLSI Design: An Overview. 2. Low-Voltage Process Technology. 3. Low-Voltage Device Modeling. 4. Low-Voltage Low-Power VLSI CMOS Circuit Design. 5. Low-Voltage VLSI BiCMOS Circuit Design. 6. Low-Power CMOS Random Access Memory Circuits. 7. VLSI CMOS Subsystem Design. 8. Low-Power VLSI Design Methodology. References. Index.

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal.
Abstract: We demonstrate integration of GaAs-AlGaAs multiple quantum well modulators to silicon CMOS circuitry via flip-chip solder-bonding followed by substrate removal. We obtain 95% device yield for 32/spl times/32 arrays of devices with 15 micron solder pads. We show operation of a simple circuit composed of a modulator and a CMOS transistor. >

Journal ArticleDOI
TL;DR: In this article, the authors describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic.
Abstract: With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 /spl mu/m CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry. >

Journal ArticleDOI
K. Itoh1, K. Sasaki, Y. Nakagome1
01 Apr 1995
TL;DR: In this article, a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs, is discussed, and the authors also show that the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks is indispensable in the future.
Abstract: Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and dc current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAMs and SRAMs. In DRAMs, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the last decade for a fixed memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V/sub DD/ precharging and on-chip voltage down converting scheme. In SRAMs, partial activation of a multi-divided word line drastically reduces the dc current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit, an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the dc current. It is also shown that to design ultralow voltage DRAMs and SRAMs, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future. >

Journal ArticleDOI
TL;DR: In this article, a nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed, and it has been confirmed that a nickel film sputtered onto n/sup ± and p/sup +/- single-silicon and polysilicon substrates is uniformly converted into NiSi, without agglomeration, by lowtemperature (400-600/spl deg/C) rapid thermal annealing.
Abstract: A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFET's was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFET's also operated at higher speed. >

Journal ArticleDOI
TL;DR: In this article, the implementation of two high-frequency building blocks for low-phase-noise 1.8 GHz PLL in a standard 0.7/spl mu/m CMOS process is discussed.
Abstract: The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-/spl mu/m CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW.

Journal ArticleDOI
G.A. Sai-Halasz1
01 Jan 1995
TL;DR: In this article, a first order cycle time model performance trends and limits for both bipolar and CMOS processors are projected based on a first-order cycle-time model, and the performance limits of bipolar and room temperature CMOS uniprocessors are shown.
Abstract: Based on a first order cycle time model performance trends and limits are projected for both bipolar and CMOS processors. The key in identifying trends is the understanding of the pivotal factors at any given stage of technology progression. One such parameter is the physical area of the processor. In coming technologies there will be opposite demands placed on the system's area stemming from a need to reduce the proportion of interconnection capacitance and to send signals across the processor. Contrary to the usual perception, delays resulting from wiring capacitance decrease if processor area increases, while the minimization of signal travel times favors reducing area. The system size tradeoff in the case of bipolar processors is primarily determined by power density, while CMOS processor sizes are determined by wirability requirements. To achieve the full potential of CMOS, interconnections will have to be carefully planned. The performance limits of bipolar and room temperature CMOS uniprocessors are shown to be very similar. The highest performance technology on the horizon is liquid nitrogen temperature CMOS. Alternate technologies, based on III-V compound devices, or more exotic quantum structures, are not expected to play a role in future general-purpose high-end systems. >

Journal ArticleDOI
TL;DR: In this paper, the authors describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels, which maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range.
Abstract: We describe an all CMOS variable gain amplifier (VGA) suitable for use in disk drive read channels. The VGA maintains a 3 dB bandwidth greater than 85 MHz throughout its gain range. This ensures good phase linearity for data transfer rates of up to 50 Mb/s. The VGA provides a 25 db gain variation along an ideal exponential gain to control voltage curve and 30 dB of gain control if ideal exponential characteristics is not absolutely necessary. The VGA achieves the necessary exponential gain to control voltage characteristics intrinsically using only MOS transistors as a single unit to reduce power and area consumption. Overall power consumption is less than 10 mW for the VGA circuit excluding the off-chip buffer circuits. >

Journal Article
TL;DR: In this paper, a frequency-synthesizing, all-digital phase-locked loop (ADPLL) is integrated with a 0.5 μm CMOS microprocessor.
Abstract: A frequency-synthesizing, all-digital phase-locked loop (ADPLL) is fully integrated with a 0.5 μm CMOS microprocessor. The ADPLL has a 50-cycle phase lock, has a gain mechanism independent of process, voltage, and temperature, and is immune to input jitter. A digitally-controlled oscillator (DCO) forms the core of the ADPLL and operates from 50 to 550 MHz, running at 4× the reference clock frequency. The DCO has 16 b of binarily weighted control and achieves LSB resolution under 500 fs

Journal ArticleDOI
TL;DR: This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology.
Abstract: Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW. >

Journal ArticleDOI
TL;DR: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology and a new 4-2 compressor and a carry lookahead adder (CLA) have been developed to enhance the speed performance.
Abstract: A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

Journal ArticleDOI
C.H. Stapper, R.J. Rosner1
TL;DR: In this article, the authors proposed a yield management approach based on defect density learning to determine the contamination levels for clean rooms and process equipment, which allows for a systematic allocation of resources.
Abstract: Integrated circuit manufacturing yields are not necessarily a function of chip area. Accurate yield analysis shows how the yield depends on circuit design and layout. By determining the probabilities of failure and critical areas for different defect types, it is possible to control and manage the yield of integrated circuits. This includes the manufacture of DRAM's, SRAM's, CMOS logic, ASIC's, and CMOS and biCMOS microprocessors. Examples explain the method of meeting yield objectives by setting targets for yield components. In addition, the yield management approach allows for a systematic allocation of resources. Required defect-density learning determines the contamination levels for clean rooms and process equipment. >

Journal ArticleDOI
TL;DR: In this paper, a CMOS mixer topology for use in highly integrated downconversion receivers is presented, which is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch.
Abstract: A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 /spl mu/m CMOS process. It takes up 1 mm/sup 2/ of total chip area and its power consumption is 1.3 mW from a single 5 V power supply. >

Journal ArticleDOI
TL;DR: A low cost, high reliability accelerometer microsystem designed for crash sensing in automotive airbag electronic control units is presented in this article, where the sensitive part is a surface micromachined capacitive interdigitated structure realized from a SIMOX SOI substrate.
Abstract: A low cost, high reliability accelerometer microsystem designed for crash sensing in automotive airbag electronic control units is presented. The proposed microsystem offers high level output, on-line self-test function, small size (3.5 mm × 3.5 mm × 1.15 mm), and high design flexibility thanks to a two-chip construction. The sensitive part is a surface micromachined capacitive interdigitated structure realized from a SIMOX SOI substrate. The accelerometer operates in a closed loop mode using electrostatic feedback with conditioning circuitry realized in a 2 μm CMOS process. A high performance readout circuit using switched capacitors has been developed. Behavioural simulation results show a bandwidth of 630 Hz at ±50 g with 5 V power supply. The fabrication process includes the realization of a free-standing seismic mass by means of reactive ion etching and sacrificial oxide etching, the mechanical protection of the sensing element with a thin silicon cap bonded onto the structured SOI wafer, and eventually the electrical connection with the ASIC by flip-chip bonding. Preliminary results are very encouraging: dynamic actuation of the sensing elements is optically tested, with a yield of 70% at a prototype level. Excellent shock resistance and low internal stress are observed.

Proceedings Article
J.J.F. Rijns1
01 Sep 1995
TL;DR: In this article, the authors describe the principle and design of a CMOS variable-gain amplifier for high-frequency applications, which is based on a linear voltage-to-current conversion by means of a digitally controlled conversion impedance.
Abstract: This paper describes the principle and design of a CMOS variable-gain amplifier for high-frequency applications. The operation of the differential circuit is based on a linear voltage-to-current conversion by means of a digitally controlled conversion impedance. Experimental results of the circuit show total harmonic distortion figures better than ?60 dB and a gain accuracy of 0.05 dB over the ?2 to + 12 dB gain range.

Journal ArticleDOI
Bram Nauta1, A.G.W. Venes1
TL;DR: In this article, a folding and interpolating technique was used to increase the analog bandwidth of the A/D converter by using a transresistance amplifier at the outputs of the folding amplifiers and the comparators need no offset compensation.
Abstract: A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm/sup 2/ in 0.8 /spl mu/m CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW.

Proceedings ArticleDOI
10 Dec 1995
TL;DR: Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors that permit realization of an electronic camera-on-a-chip.
Abstract: Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On-chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip.

Journal ArticleDOI
TL;DR: This work describes a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit and shows that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits.
Abstract: Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies. >

Journal ArticleDOI
15 Feb 1995
TL;DR: The PLL design reported in this paper has a fully differential structure that is immune to substrate and supply noise, and the architecture is unique because resistors are not needed for PLL loop stabilization.
Abstract: Phase-locked loops (PLL) are widely used for clock-phase synchronization, frequency synthesis and clock distribution It is highly desirable that the standard digital CMOS process be used in the PLL design because process modifications increase product cost Other desirable features include insensitivity to noise and a fully integrated design The PLL design reported in this paper has all the above features A standard digital CMOS process is used to produce a fully differential structure that is immune to substrate and supply noise The PLL function includes multiplication of frequency and synchronization of input and output clock phases The architecture is unique because resistors are not needed for PLL loop stabilization

Journal ArticleDOI
TL;DR: In this paper, the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits is presented, which enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuit to proceed independently of the placement and the bonding of surface normal optical modulators to the circuit.
Abstract: We accomplish the integration of GaAs-AlGaAs multiple quantum well modulators directly on top of active silicon CMOS circuits. This enables optoelectronic VLSI circuits to be achieved and also allows the design and optimization of the CMOS circuits to proceed independently of the placement and the bonding of surface-normal optical modulators to the circuit. Using this technique, we demonstrate operation of a 0.8 micron CMOS transimpedance receiver-transmitter circuit at 375 Mb/s. >