Showing papers on "CMOS published in 1996"

Digital integrated circuits: a design perspective

Abstract: (NOTE: Each chapter begins with an Introduction and concludes with a Summary, To Probe Further, and Exercises and Design Problems.) I. THE FABRICS. 1. Introduction. A Historical Perspective. Issues in Digital Integrated Circuit Design. Quality Metrics of a Digital Design. 2. The Manufacturing Process. The CMOS Manufacturing Process. Design Rules-The Contract between Designer and Process Engineer. Packaging Integrated Circuits. Perspective-Trends in Process Technology. 3. The Devices. The Diode. The MOS(FET) Transistor. A Word on Process Variations. Perspective: Technology Scaling. 4. The Wire. A First Glance. Interconnect Parameters-Capitance, Resistance, and Inductance. Electrical Wire Models. SPICE Wire Models. Perspective: A Look into the Future. II. A CIRCUIT PERSPECTIVE. 5. The CMOS Inverter. The Static CMOS Inverter-An Intuitive Perspective. Evaluating the Robustness of the CMOS Inverter: The Static Behavior. Performance of CMOS Inverter: The Dynamic Behavior. Power, Energy, and Energy-Delay. Perspective: Technology Scaling and Its Impact on the Inverter Metrics. 6. Designing Combinational Logic Gates in CMOS. Static CMOS Design. Dynamic CMOS Design. How to Choose a Logic Style? Perspective: Gate Design in the Ultra Deep-Submicron Era. 7. Designing Sequential Logic Circuits. Timing Metrics for Sequential Circuits. Classification of Memory Elements. Static Latches and Registers. Dynamic Latches and Registers. Pulse Registers. Sense-Amplifier Based Registers. Pipelining: An Approach to Optimize Sequential Circuits. Non-Bistable Sequential Circuits. Perspective: Choosing a Clocking Strategy. III. A SYSTEM PERSPECTIVE. 8. Implementation Strategies for Digital ICS. From Custom to Semicustom and Structured-Array Design Approaches. Custom Circuit Design. Cell-Based Design Methodology. Array-Based Implementation Approaches. Perspective-The Implementation Platform of the Future. 9. Coping with Interconnect. Capacitive Parasitics. Resistive Parasitics. Inductive Parasitics. Advanced Interconnect Techniques. Perspective: Networks-on-a-Chip. 10. Timing Issues in Digital Circuits. Timing Classification of Digital Systems. Synchronous Design-An In-Depth Perspective. Self-Timed Circuit Design. Synchronizers and Arbiters. Clock Synthesis and Synchronization Using a Phased-Locked Loop. Future Directions and Perspectives. 11. Designing Arithmetic Building Blocks. Datapaths in Digital Processor Architectures. The Adder. The Multiplier. The Shifter. Other Arithmetic Operators. Power and Spped Trade-Offs in Datapath Structures. Perspective: Design as a Trade-off. 12. Designing Memory and Array Structures. The Memory Core. Memory Peripheral Circuitry. Memory Reliability and Yield. Power Dissipation in Memories. Case Studies in Memory Design. Perspective: Semiconductor Memory Trends and Evolutions. Problem Solutions. Index.

Upset hardened memory design for submicron CMOS technology

Abstract: A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Abstract: A 4 mm/sup 2/, two-dimensional (2-D) 8/spl times/8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-/spl mu/m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V/sub DD/-V/sub th/ design space is also studied.

CMOS differential difference current conveyors and their applications

Abstract: The authors present a new versatile circuit building block called a differential difference current conveyor (DDCC). An IC technique for implementing the DDCC is also presented. The DDCC-based frequency-selective circuits and nonlinear building blocks such as multiplier, squarer and square rooter are developed. Experimental results are given to demonstrate the feasibility of the proposed techniques, and they show that DDCC-based circuits offer a competitive design choice to CCII-based and DDA-based circuits.

A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver

Abstract: An integrated low-noise amplifier and downconversion mixer operating at 1 GHz has been fabricated for the first time in 1 /spl mu/m CMOS. The overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, the IIP3 is +8 dBm, and the circuit takes 9 mA from a 3 V supply. Circuit design methods which exploit the features of CMOS well suited to these functions are in large part responsible for this performance. The front-end is also characterized in several other ways relevant to direct-conversion receivers.

Surface micromachined accelerometers

Abstract: Surface micromachining has enabled the cofabrication of thin-film micromechanical structures and CMOS or bipolar/MOS integrated circuits. Using linear, single-axis accelerometers as a motivating example, this paper discusses the fundamental mechanical as well as the electronic noise floors for representative capacitive position-sensing interface circuits. Operation in vacuum lowers the Brownian noise of a polysilicon accelerometer to below 1 /spl mu/g//spl radic/(Hz). For improved sensor performance, the position of the microstructure should be controlled using electrostatic force-feedback. Both analog and digital closed-loop accelerometers are described and contrasted, with the latter using high-frequency voltage pulses to apply force quanta to the microstructure and achieve a very linear response.

Micropower CMOS temperature sensor with digital output

Abstract: A CMOS smart temperature sensor with digital output is presented It consumes only 7 /spl mu/W To achieve this extremely low-power consumption, the system is equipped with a facility that switches off the supply power after each sample The circuit uses substrate bipolars as a temperature sensor Conversion to the digital domain is done by a sigma-delta converter which makes the circuit highly insensitive to digital interference The complete system is realized in a standard CMOS process and measures only 15 mm/sup 2/ In the temperature range from -40 to +120/spl deg/C, the inaccuracy is /spl plusmn/1/spl deg/C after calibration at two temperatures The circuit operates at supply voltages down to 22 V

Technology and device scaling considerations for CMOS imagers

Abstract: This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from "standard" CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while "standard" CMOS technologies may provide adequate imaging performance at the 2-1 /spl mu/m generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 /spl mu/m technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined.

Top-down pass-transistor logic design

Abstract: The pass-transistor based cell library and synthesis tool are constructed, for the first time, to clarify the potential of top-down pass-transistor logic. The entire scheme is called LEAP (Lean Integration with Pass-Transistors). The feature of a pass-transistor based cell is its multiplexer function and the open-drain structure. This cell has the flexibility of transistor level circuit design and compatibility with conventional cell based design. An extremely simple cell library with only seven cells combined with a synthesis tool called "circuit inventor" is compared with the conventional CMOS library that has over 60 cells combined with the state-of-the-art logic synthesis. The results show that the area, delay, and power dissipation are improved by LEAP and that the value-cost ratio is improved by a factor of three. This demonstrates that LEAP has the potential to achieve a quantum leap in value of LSI's while reducing the cost. Key issues which have to be cleared before pass transistor logic is used as the generic logic scheme replacing CMOS are also discussed.

Laminated high-aspect-ratio microstructures in a conventional CMOS process

Abstract: Electrostatically actuated microstructures with high-aspect-ratio laminated-beam suspensions have been fabricated using conventional CMOS processing followed by a sequence of maskless dry-etching steps. Laminated structures are etched out of the CMOS silicon oxide, silicon nitride, and aluminum layers. The key to the process is use of the CMOS metallization as an etch-resistant mask to define the microstructures. A minimum beam width and gap of 1.2 /spl mu/m and maximum beam thickness of 4.8 /spl mu/m are fabricated in a 0.8 /spl mu/m 3-metal CMOS process available through MOSIS. Structural features will scale in size as the CMOS technology improves. An effective Young's modulus of 63 GPa is extracted from resonant frequency measurements. Cantilevered structures slightly curl up with a radius of curvature of about 4.2 mm. Multi-conductor electrostatic micromechanisms, such as self-actuating springs and nested comb-drive lateral resonators, are successfully produced. Self-actuating springs are self-aligned multi-conductor electrostatic microactuators that are insensitive to curl. The resonance amplitude is 1 /spl mu/m for an 107 /spl mu/m-wide/spl times/109 /spl mu/m-long spring with an applied 11 V ac signal. Finite-element simulation using the extracted value for Young's modulus predicts the resonant frequency of the springs to within 6% of the measured values.

Circuit techniques for CMOS low-power high-performance multipliers

Abstract: In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.

256/spl times/256 CMOS active pixel sensor camera-on-a-chip

Abstract: A CMOS imaging sensor is described that uses active pixel sensor (APS) technology and permits the integration of the detector array with on-chip timing, control, and signal chain electronics. This sensor technology has been used to implement a CMOS APS camera-on-a-chip. The camera-on-a-chip features a 256/spl times/256 APS sensor integrated on a CMOS chip with the timing and control circuits, and signal-conditioning to enable random-access, low power (/spl sim/5 mW) operation, and low read noise (13 e/sup -/ rms). The chip features simple power supplies, fast readout rates, and a digital interface for commanding the sensor, as well as for programming the window-of-interest readout and exposure times. Excellent imaging has been demonstrated with the APS camera-on-a-chip, and the measured performance indicates that this technology will be competitive with charge-coupled devices (CCD's) in many applications.

Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap

Abstract: Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology.

A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 /spl mu/m CMOS

Abstract: A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 /spl mu/m CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply.

A 117-mm/sup 2/ 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications

Abstract: For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-/spl mu/m CMOS technology, resulting in a 117 mm/sup 2/ die size and a 1.1 /spl mu/m/sup 2/ effective cell size.

Integrated circuit cell architecture and routing scheme

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Translinear circuits in subthreshold MOS

Abstract: In this paper we provide an overview of translinear circuit design using MOS transistors operating in subthreshold region. We contrast the bipolar and MOS subthreshold characteristics and extend the translinear principle to the subthreshold MOS ohmic region through a drain/source current decomposition. A front/back-gate current decomposition is adopted; this facilitates the analysis of translinear loops, including multiple input floating gate MOS transistors. Circuit examples drawn from working systems designed and fabricated in standard digital CMOS oriented process are used as vehicles to illustrate key design considerations, systematic analysis procedures, and limitations imposed by the structure and physics of MOS transistors. Finally, we present the design of an analog VLSI “translinear system” with over 590,000 transistors in subthreshold CMOS. This performs phototransduction, amplification, edge enhancement and local gain control at the pixel level.

VHF CMOS integrated active inductor

Abstract: The implementation of an RF CMOS active inductor is described. The circuit is based on a recently proposed CMOS GIC. The inductor loss is reduced by applying gain enhancement techniques based on cascoding. The proposed new inductors exhibit lower loss, high self-resonance frequency and wider inductive region. An RLC bandpass filter response is realised to verify the performance of the simulated inductor.

CMOS low-power analog circuit design

Abstract: This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.

Performance computation for precharacterized CMOS gates with RC loads

Abstract: For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure. The delay and power are calculated with errors on the same order as those for the original empirical equations. Moreover, a linear equivalent gate model is generated which accurately captures the delays at the interconnect fan-out nodes.

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

Abstract: An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm/sup 2/ in 0.5-/spl mu/m standard digital CMOS technology.

A 2.5 V 12 b 5 MSample/s pipelined CMOS ADC

Abstract: A set of power minimization techniques is proposed for pipelined ADC's. These techniques include commutating feedback-capacitors, sharing of the op-amp between the adjacent stages of the pipeline, reusing the first stage of the op-amp as comparator pre-amp, and exploiting parasitic capacitors for common-mode feedback. This set of low-power design techniques is incorporated in an experimental chip fabricated in a 1.2-/spl mu/m, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, the chip dissipates 33 mW of power from a 2.5-V analog supply while achieving a maximum differential nonlinearity (DNL) of -0.78 and +0.63 least-significant bits (LSB) with a peak signal-to-noise ratio (SNR) of 67.6 dB.

Pixel structure, image sensor using such pixel, structure and corresponding peripheric circuitry

Abstract: A pixel structure for CMOS imaging applications, the pixel structure including a photosensitive element, a load transistor in series with the photosensitive element, a first reading transistor, coupled to the photosensitive element and to the load transistor, for reading out signals acquired in the photosensitive element and converting the signals to a voltage drop across the load transistor. The gate length of at least the load transistor is increased by at least 10% compared to a gate length of transistors manufactured according to layout rules imposed by a CMOS manufacturing process, thereby increasing the light sensitivity of the pixel structure.

CMOS low-distortion high-frequency variable-gain amplifier

Abstract: The overall system performance of mixed-signal CMOS IC's is largely determined by the dynamic performance of the analog front-ends. System features are, in contrast, mainly set by the digital architecture. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, the analog-to-digital converter (ADC) has to be preceded by a variable-gain amplifier (VGA) and a differential circuit topology for the complete front-end to be adopted. Since most of present-day applications are based on single-sided signal source definitions, the differential-input VGA must be able to perform a single-to-differential signal conversion. This paper describes the principle and design of a differential CMOS low-distortion variable-gain amplifier for high-frequency (video) applications. Experimental results of the circuit show total harmonic distortion figures better than -60 dB and a gain accuracy of 0.05 dB over the -2 to +12 dB gain range for single-sided input signals.

Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks

Abstract: In digital circuits, a transistor connected to a particular circuit node does not always load that node by a gate capacitance proportional to C/sub ox/WL if the transistors connected to its source are turned off. Such an observation, illustrated in this paper by a detailed analysis of the Yuan-Svensson D-flip-flop (D-FF) can be used to advantage both in sizing the transistors and in developing better configurations. A glitch-free, general purpose, and faster D-FF is presented here which has complementary outputs and runs at frequencies from tens of hertz to a couple of gigahertz for a 1-/spl mu/m CMOS technology. Measured maximum clock frequency of a divide-by-16 circuit is 2.65 GHz at 5 V supply, whereas that of a dual-modulus frequency prescaler, dividing by 64/65, goes up to 1.6 GHz at 5 V.

Infrared focal plane array incorporating silicon IC process compatible bolometer

Abstract: A 128/spl times/128 element bolometer infrared image sensor using thin film titanium is proposed. The device is a monolithically integrated structure with a titanium bolometer detector located over a CMOS circuit that reads out the bolometer's signals. By employing a metallic material like titanium and refining the CMOS readout circuit, it is possible to minimize 1/f noise. It is demonstrated that the use of low 1/f noise material will help increase bias current and improve the S/N ratio. Since the fabrication process is silicon-process compatible, costs can be kept low.

Data driven signal processing: an approach for energy efficient computing

Abstract: The computational switching activity of digital CMOS circuits can be dynamically minimized by designing algorithms that exploit signal statistics. This results in processors that have time-varying power requirements and perform computation on demand. An approach is presented to minimize the energy dissipation per data sample in variable-load DSP systems by adaptively minimizing the power supply voltage for each sample using a variable switching speed processor. In general, using buffering and filtering, the computation can be spread over multiple samples averaging the workload and lowering energy further. It is also shown that four levels of voltage quantization combined with dithering is sufficient to closely emulate arbitrary voltage levels.

Novel clamp circuits for IC power supply protection

Abstract: Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate complementary metal-oxide semiconductor (CMOS) and used for power supply electrostatic discharge (ESD) clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

A GHz MOS adaptive pipeline technique using MOS current-mode logic

Abstract: This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

CMOS imaging device with integrated flash memory image correction circuitry

Abstract: A CMOS image sensing device includes, on one integrated circuit, a sensor array (12) and compensation circuitry (14) for adjusting signals output from the sensor array (12) to compensate for output signal variations, such as variations caused by voltage, temperature or process variations. The integrated circuit also includes logic circuitry (18) for performing image processing operations on signals output from the sensor array (12). The sensor array (12) is illuminated by a flat light source and variations among the magnitude of analog output signals from the elements are detected and corresponding compensation values are calculated and stored in the compensation circuitry (14). Thereafter, analog signals output from the sensor array (12) are adjusted in accordance with the compensation values.