Showing papers on "CMOS published in 1997"

A 1.5-V, 1.5-GHz CMOS low noise amplifier

Abstract: A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-/spl mu/m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices.

CMOS image sensors: electronic camera-on-a-chip

Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

Low-power logic styles: CMOS versus pass-transistor logic

Abstract: Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

CMOS scaling into the nanometer regime

Abstract: Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

Supply and threshold voltage scaling for low power CMOS

Abstract: This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields.

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

Abstract: In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

CMOS active pixel image sensors for highly integrated imaging systems

Abstract: A family of CMOS-based active pixel image sensors (APSs) that are inherently compatible with the integration of on-chip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2-/spl mu/m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and transistor-transistor logic (TTL) compatible control signals. Methods of on-chip suppression of fixed pattern noise to less than 0.1% saturation are demonstrated. The baseline design achieved a pixel size of 40 /spl mu/m/spl times/40 /spl mu/m with 26% fill-factor. Array sizes of 28/spl times/28 elements and 128/spl times/128 elements have been fabricated and characterized. Typical output conversion gain is 3.7 /spl mu/V/e/sup -/ for the p-well devices and 6.5 /spl mu/V/e/sup -/ for the n-well devices. Input referred read noise of 28 e/sup -/ rms corresponding to a dynamic range of 76 dB was achieved. Characterization of various photogate pixel designs and a photodiode design is reported. Photoresponse variations for different pixel designs are discussed.

Novel CMOS differential voltage current conveyor and its applications

Abstract: Novel CMOS realisations of a differential voltage current conveyor (DVCC) are described. These circuits are powerful building blocks, especially for applications demanding differential or floating inputs like impedance converter circuits and current mode instrumentation amplifiers. Applications suitable for VLSI are then considered by using the DVCC to realise a MOS transconductor and a continuous-time current mode MOSFET-C filter. PSpice simulations indicate the excellent performance of the proposed DVCC and of its circuit applications.

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

Abstract: A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-/spl mu/m CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH /spl Sigma/-/spl Delta/ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard.

CMOS current reference without resistance

Abstract: A micropower current reference in the range of 1 to 100 nA is built with CMOS transistors only, featuring low sensitivity with respect to technology and temperature. Supply voltage can be as low as 1.2 V. This autonomous circuit is simple and occupies a surface area of 0.06 mm/sup 2/.

A gate-level leakage power reduction method for ultra-low-power CMOS circuits

Abstract: In order to reduce the power dissipation of CMOS products, semiconductor manufacturers are reducing the power supply voltage. This requires that the transistor threshold voltages be reduced as well to maintain adequate performance and noise margins. However, this increases the subthreshold leakage current of p and n MOSFETs, which starts to offset the power savings obtained from power supply reduction. This problem will worsen in future generations of technology, as threshold voltages are reduced further. In order to overcome this, we propose a design technique that can be used during logic design in order to reduce the leakage current and power. We target designs where parts of the circuit are put in "standby" mode when not in use, which is becoming a common approach for low power design. The proposed design changes consist of minimal overhead circuitry that puts the circuit into a "low leakage standby state", whenever it goes into standby, and allows it to return to its original state when it is reactivated. We give an efficient algorithm for computing a good low leakage power state. We demonstrate this method on the ISCAS-89 benchmark suite and show leakage power reductions of up to 54% for some circuits.

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits

Abstract: This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSI's) for battery-driven portable equipment. The "balloon" circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-/spl mu/m CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices.

New single-clock CMOS latches and flipflops with improved speed and power savings

Abstract: New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.

Wide intrascene dynamic range CMOS APS using dual sampling

Abstract: A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64/spl times/64 element prototype sensor with dual output architecture was fabricated using a 1.2 /spl mu/m n-well CMOS process with 20.4 /spl mu/m pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding.

Intrinsic MOSFET parameter fluctuations due to random dopant placement

Abstract: Intrinsic fluctuations in threshold voltage, subthreshold swing, saturation drain current and subthreshold leakage of ultrasmall-geometry MOSFETs due to random placement of dopant atoms in the channel are examined using novel physical models and a Monte Carlo simulator. These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future. In particular, using the device technology and the level of integration projections of the National Technology Roadmap for Semiconductors for the next 15 years, standard and maximum deviations of threshold voltage, drive current, subthreshold swing and subthreshold leakage are shown to escalate to 40 and 600 mV, 10 and 100%, 2 and 20 mV/dec, and 10 and 10/sup 8/%, respectively, in the 0.07 /spl mu/m, 0.9 V complementary metal-oxide-semiconductor (CMOS) technology generation with 1.3-64 billion transistors on a chip in 2010. While these deviations can be reduced to some degree by selecting optimal values of channel width, the associated penalties in dynamic and static power, and in packing density demand improved MOSFET structures aimed at minimizing parameter deviations.

A 1.8-V digital-audio sigma-delta modulator in 0.8-/spl mu/m CMOS

Abstract: Oversampling techniques based on sigma-delta (/spl Sigma//spl Delta/) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in low-voltage environment. This paper examines the design and implementation of a CMOS /spl Sigma//spl Delta/ modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8-/spl mu/m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm/sup 2/, and dissipates 2.5 mW from a 1.8-V supply.

Transistor sizing issues and tool for multi-threshold CMOS technology

Abstract: Multi-threshold CMOS is an increasingly popular circuitapproach that enables high performance and low power operation.However, no methodologies have been developed to size the highV{t} sleep transistor in an intelligent manner that trades off area andperformance. In fact, many attempts at sizing the sleep transistorwithout close consideration of input vector patterns or internalstructures can lead to large overestimates or large underestimatesin sleep transistor sizing. This paper describes some of the issuesinvolved in sizing transistors for MTCMOS and also introduces avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing.

Low-voltage low-power CMOS current conveyors

Abstract: New CMOS rail to rail second generation current conveyor circuits are proposed. First a class A current conveyor circuit which operates from a single supply of 1.5 V with a rail to rail voltage swing capability is given. The circuit is then modified to work as a class AB while maintaining the rail to rail swing capability. The class AB circuit works from supply voltages down to +1.1 V with standby current of 56 /spl mu/A. These new current conveyor realizations are insensitive to the threshold voltage variation caused by the body effect, which minimizes the layout area and makes both circuits a valuable addition to the analog VLSI libraries. PSpice simulation confirms the attractive properties of the proposed circuits.

A 12 mW wide dynamic range CMOS front end for a portable GPS receiver

Abstract: This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-/spl mu/m (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer has a voltage conversion gain of -3.6 dB and a third-order intermodulation intercept point (IP3) of 10 dBm, input referred. The combination draws 12 mW from a 1.5-V supply.

Intrinsic leakage in low power deep submicron CMOS ICs

Abstract: The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform I/sub DDQ/ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V/sub DD/). These device properties are applied to a test application that combines I/sub DDQ/ and F/sub MAX/ to establish a 2-parameter limit for distinguishing intrinsic and extrinsic (defect) leakages in microprocessors with high background I/sub DDQ/ leakage.

Pass-transistor adiabatic logic using single power-clock supply

Abstract: We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.

Analog and mixed-signal benchmark circuits-first release

Abstract: The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR

Abstract: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-/spl mu/m CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal.

An integrated analog/digital random noise source

Abstract: An integrated noise source (INS) has been fabricated in a standard 1.2 /spl mu/m digital CMOS technology. Wideband white noise is generated from the amplified thermal noise of large resistors, which in turn is coupled into a comparator to generate a random digital bit stream. The INS generates 100 mV rms of analog output noise over a bandwidth of 3.2 MHz and operates from a single 5 V power supply with a quiescent current of 7.4 mA. The circuit has an area of 2.92 mm/sup 2/. Potential applications of the INS include data encryption, mathematical simulation, and circuit test and measurement.

Low noise amplifier for passive pixel CMOS imager

Abstract: A CMOS imaging system provides low noise read out and amplification for an array of passive pixels, each of which comprises a photodetector, an access MOSFET, and a second MOSFET that functions as a signal overflow shunt and a means for electrically injecting a test signal. The read out circuit for each column of pixels includes a high gain, wide bandwidth, CMOS differential amplifier, a reset switch and selectable feedback capacitors, selectable load capacitors, correlated double sampling and sample-and-hold circuits, an optional pipelining circuit, and an offset cancellation circuit connected to an output bus to suppress the input offset nonuniformity of the amplifier. For full process compatibility with standard silicided submicron CMOS and to maximize yield and minimize die cost, each photodiode may comprise the lightly doped source of its access MOSFET. Circuit complexity is restricted to the column buffers, which exploit signal processing capability inherent in CMOS. Advantages include high fabrication yield, broadband spectral response from near-UV to near-IR, low read noise at HDTV data rates, large charge-handling capacity, variable sensitivity with simple controls, and reduced power consumption.

Low-power encodings for global communication in CMOS VLSI

Abstract: Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling.

Efficiency improvement in charge pump circuits

Abstract: Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatically vary the switching frequency of a dual charge pump circuit according to the loading. The switching frequency is designed to be 25 kHz with 12 mA loading on both inverting and noninverting outputs. The switching frequency is automatically reduced when loading is lighter to improve the power efficiency. The frequency tuning range of this circuit is designed to be from 100 Hz to 25 kHz. A start-up circuit is included to ensure proper pumping action and avoid latch-up during power-up. A slow turn-on, fast turn-off driving scheme is used in the clock buffer to reduce power dissipation. The new dual charge pump circuit was fabricated in a 3-/spl mu/m p-well double-poly single-metal CMOS technology with breakdown voltage of 18 V, the die size is 4.7/spl times/4.5 mm/sup 2/. For comparison, a charge pump circuit with conventional level shifter and clock buffer was also fabricated. The measured results show that the new charge pump has two advantages: (1) the power dissipation of the charge pump is improved by a factor of 32 at no load and by 2% at rated loading of 500 /spl Omega/ and (2) the breakdown voltage requirement is reduced from 19.2 to 17 V.

A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

Abstract: A high performance 020 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects 015 /spl mu/m transistors (L/sub gate/=015/spl plusmn/004 /spl mu/m) are optimized for 18 V operation to provide high performance with low power-delay products and excellent reliability Copper has been integrated into the back-end to provide low resistance interconnects Critical layer pitches for the technology are summarized and enable fabrication of 76 /spl mu/m/sup 2/ 6T SRAM cells

Low voltage performance of a microwave CMOS Gilbert cell mixer

Abstract: This paper demonstrates the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8-/spl mu/m CMOS process and operating as both a down-converter and an up-converter. As a down-converter with an RF input of 1.9 GHz, the mixer has a single sideband noise figure as low as 7.8 dB and achieved down-conversion gain for supply voltages as low as 1.8 V. As an up-converter, the mixer demonstrates 10 dB of conversion gain at an RF frequency of 2.4 GHz with an applied local oscillator (LO) power of -7 dBm and LO-RF/LO-IF isolation of at least 30 dB. Up-conversion gain was achieved over a 5-GHz bandwidth and at supply voltages as low as 1.5 V. The mixer presented demonstrates the lowest single side band noise figure for a CMOS doubly balanced down-converting mixer and the highest frequency of operation for a mixer fabricated in CMOS technology to date.

The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

Abstract: The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-/spl mu/m CMOS technology.