Showing papers on "CMOS published in 1999"

Design of Analog CMOS Integrated Circuits

Abstract: The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies. Table of contents 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging

Design challenges of technology scaling

Abstract: Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%; 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50% of power (at a 43% increase in frequency). These are not ad hoc goals; rather, they follow scaling theory. This article looks closely at past trends in technology scaling and how well microprocessor technology and products have met these goals. It also projects the challenges that lie ahead if these trends continue. This analysis uses data from various Intel microprocessors; however, this study is equally applicable to other types of logic designs. Is process technology meeting the goals predicted by scaling theory? An analysis of microprocessor performance, transistor density, and power trends through successive technology generations helps identify potential limiters of scaling, performance, and integration.

Design issues in CMOS differential LC oscillators

Abstract: An analysis of phase noise in differential cross-coupled inductance-capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measurements over a large range of tail currents and supply voltages. A 1.8 GHz LC oscillator with a phase noise of -121 dBc/Hz at 600 kHz is demonstrated, dissipating 6 mW of power using on-chip spiral inductors.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

Abstract: A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

Logical Effort: Designing Fast CMOS Circuits

Abstract: 1 The Method of Logical Effort 2 Design Examples 3 Deriving the Method of Logical Effort 4 Calculating the Logical Effort of Gates 5 Calibrating the Model 6 Asymmetric Logic Gates 7 Unequal Rising and Falling Delays 8 Circuit Families 9 Forks of Amplifiers 10 Branches and Interconnect 11 Wide Structures 12 Conclusions A Cast of Characters B Reference process parameters C Logical Effort Tools D Solutions

A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics

Abstract: This paper describes a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS. The accelerometer measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input. The half-bridge is connected to a fully differential position-sense interface, the output of which is used for one-bit force feedback. By enclosing the proof mass in a one-bit feedback loop, simultaneous force balancing and analog-to-digital conversion are achieved. On-chip digital offset-trim electronics enable compensation of random offset in the electronic interface. Analytical performance calculations are shown to accurately model device behaviour. The fabricated single-chip accelerometer measures 4/spl times/4 mm/sup 2/, draws 27 mA from a 5-V supply, and has a dynamic range of 84, 81, and 70 dB along the x-, y-, and z-axes, respectively.

An integrated CMOS micromechanical resonator high-Q oscillator

Abstract: A completely monolithic high-Q oscillator, fabricated via a combined CMOS plus surface micromachining technology, is described, for which the oscillation frequency is controlled by a polysilicon micromechanical resonator with the intent of achieving high stability. The operation and performance of micromechanical resonators are modeled, with emphasis on circuit and noise modeling of multiport resonators. A series resonant oscillator design is discussed that utilizes a unique, gain-controllable transresistance sustaining amplifier. We show that in the absence of an automatic level control loop, the closed-loop, steady-state oscillation amplitude of this oscillator depends strongly upon the dc-bias voltage applied to the capacitively driven and sensed /spl mu/resonator. Although the high-Q of the micromechanical resonator does contribute to improved oscillator stability, its limited power-handling ability outweighs the Q benefits and prevents this oscillator from achieving the high short-term stability normally expected of high-Q oscillators.

Nanoscale CMOS

Abstract: This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Ion-sensitive field-effect transistors fabricated in a commercial cmos technology

Abstract: The fabrication of pH-sensitive ISFET devices in an unmodified two-metal commercial CMOS technology (1.0 m from Atmel-ES2) is reported. The ISFET devices have a gate structure compatible with the CMOS process, with an electrically floating electrode consisting on polysilicon plus the two metals. The passivation oxynitride layer acts as the pH-sensitive material in contact with the liquid solution. The devices have shown good operating characteristics, with a 47 mV/pH response. The use of a commercial CMOS process allows the straightforward integration of signal-processing circuitry. An ISFET amplifier circuit has been integrated with the ISFET sensors.

Design of high-performance CMOS charge pumps in phase-locked loops

Abstract: Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects

Abstract: We discuss design issues related to the extensive use of Enclosed Layout Transistors (ELT's) and guard rings in deep submicron CMOS technologies in order to improve radiation tolerance of ASIC's designed for the LHC experiments (the Large Hadron Collider at present under construction at CERN). We present novel aspects related to the use of ELT's: noise measured before and after irradiation up to 100 Mrad (SiO/sub 2/), a model to calculate the W/L ratio and matching properties of these devices. Some conclusions concerning the density and the speed of IC's conceived with this design approach are finally drawn.

A 640/spl times/512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC

Abstract: Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640/spl times/512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to-digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640/spl times/512 sensor is implemented in 0.35-/spl mu/m CMOS technology and achieves 10.5/spl times/10.5 /spl mu/m pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed pattern noise are presented. A scene with measured dynamic range exceeding 10000:1 is sampled nine times to obtain an image with dynamic range of 65536:1. Limits on achievable dynamic range using multiple sampling are presented.

A study of oscillator jitter due to supply and substrate noise

Abstract: This paper investigates the timing jitter of single-ended and differential CMOS ring oscillators due to supply and substrate noise. We calculate the jitter resulting from supply and substrate noise, show that the concept of frequency modulation can be applied, and derive relationships that express different types of jitter in terms of the sensitivity of the oscillation frequency to the supply or substrate voltage. Using examples based on measured results, we show that thermal jitter is typically negligible compared to supply- and substrate-induced jitter in high-speed digital systems. We also discuss the dependence of the jitter of differential CMOS ring oscillators on transistor gate width, power consumption, and the number of stages.

A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications

Abstract: This paper presents a 1-W, class-E power amplifier that is implemented in a 0.35-/spl mu/m CMOS technology and suitable for operations up to 2 GHz. The concept of mode locking is used in the design, in which the amplifier acts as an oscillator whose output is forced to run at the input frequency. A compact off-chip microstrip balun is also proposed for output differential-to-single-ended conversion. At 2-V supply and at 1.98 GHz, the power amplifier achieves 48% power-added efficiency (41% combined with the balun).

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Abstract: Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

Abstract: In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS

Abstract: This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-/spl mu/m CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset.

A portable digital DLL for high-speed CMOS interface circuits

Abstract: A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-/spl mu/m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm/sup 2/.

A new RTD-FET logic family

Abstract: We describe a new family of clocked logic gates based on the resonant-tunneling diode (RTD). Pairs of RTDs form storage latches, and these are connected by networks consisting of field-effect transistors (FETs), saturated resistors, and RTDs. The design, operation, and expected performance of both a shift register and a matched filter using this logic are discussed. Simulations show that the RTD circuits can achieve higher performance in terms of speed and power in many signal processing applications. Compared to circuits using III-V FETs alone, the RTD circuits are expected to run nearly twice as fast at the same power or at the same speed with reduced power. Compared to circuits using Lincoln Laboratory's fully depleted silicon-on-insulator CMOS, implementation using state-of-the-art RTDs should operate five times faster when both technologies follow the CMOS design rules.

CMOS imager with storage capacitor

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

An 8-bit 150-MHz CMOS A/D converter

Abstract: This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-/spl mu/m CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2/spl times/1.5 mm/sup 2/.

CMOS technology characterization for analog and RF design

Abstract: The design of analog and radio-frequency (RF) circuits in CMOS technology becomes increasingly more difficult as device modeling faces new challenges in deep submicrometer processes and emerging circuit applications. The sophisticated set of characteristics used to represent today's "digital" technologies often proves inadequate for analog and RF design, mandating many additional measurements and iterations to arrive at an acceptable solution. This paper describes a set of characterization vehicles that can be employed to quantify the analog behaviour of active and passive devices in CMOS processes, in particular, properties that are not modeled accurately by SPICE parameters. Test structures and circuits are introduced for measuring speed, noise, linearity, loss, matching, and dc characteristics.

Method for fabricating singe crystal materials over CMOS devices

Abstract: An aspect of the present invention is a method for making a functional active device (photodetector, laser, LED, optical modulator, optical switch, field effect transistor, MOSFET, MODFET, high electron mobility transistor, heterojunction bipolar transistor, resonant tunneling device, Esaki tunneling device etc.) disposed over a complementary metal oxide semiconductor (CMOS) device, having the steps; (a) forming an ultrathin compliant layer direct bonded to an oxide layer over said-CMOS device; (b) growing an epitaxial layer on said ultra-thin compliant layer (c) forming a functional active device in said epitaxial layer grown on said epitaxial layer that is grown on said ultrathin compliant layer; and (c) interconnecting said functional active device and said CMOS device, wherein said CMOS device is configured as either a readout circuit or a control circuit for said photodetector.

Models and algorithms for bounds on leakage in CMOS circuits

Abstract: Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability

Abstract: A general-purpose phase-locked loop (PLL) with programmable bit rates is presented demonstrating that large frequency tuning range, large power supply range, and low jitter can be achieved simultaneously. The clock recovery architecture uses phase selection for automatic initial frequency capture. The large period jitter of conventional phase selection is eliminated through feedback phase selection. Digital control sequencing of the feedback enables accurate phase interpolation without the traditional need of analog circuitry. Circuit techniques enabling low Vdd operation of a PLL with differential delay stages are presented. Measurements show a PLL frequency range of 1-200 MHz at Vdd=1.2 V linearly increasing to 2-1600 MHz at Vdd=2.5 V, achieved in a standard process technology without low threshold voltage devices. Correct operation has been verified down to Vdd=0.9 V, but the lower limit of differential operation with improved supply-noise rejection is estimated to be 1.1 V.

Introduction to CMOS OP-AMPs and Comparators

Abstract: MOS Devices as Circuit Elements. Basic Analog CMOS Subcircuits. CMOS Operational Amplifier. Comparators. Digital-to-Analog Converters. Analog-to-Digital Converters. Practical Considerations and Design Examples. Index.

Ultra-low power digital subthreshold logic circuits

Abstract: Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end (the focus of this paper), and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in the subthreshold region. We analyze both CMOS and Pseudo-NMOS logic families operating in the subthreshold region. We compare the results with CMOS in the normal strong inversion region and with other known low-power logic, namely, energy recovery logic. Our results show an energy per switching reduction of two orders of magnitude for an 8/spl times/8 carry save array multiplier when it is operated in the subthreshold region.

High density submicron magnetoresistive random access memory (invited)

Abstract: Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal–oxide–semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

Low-power bandgap references featuring DTMOSTs

Abstract: This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 /spl mu/W; the die area is 0.063 mm/sup 2/ in a standard digital 0.35-/spl mu/m CMOS process. The second bandgap reference circuit aims at high accuracy operation (/spl sigma/=0.3%) without trimming. It consumes approximately 5 /spl mu/W from a 1.8-V supply voltage and occupies 0.06 mm/sup 2/ in a standard 0.35-/spl mu/m CMOS process.

A 2-GHz wide-band direct conversion receiver for WCDMA applications

Abstract: A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-/spl mu/m BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-/spl mu/m CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply.