Showing papers on "CMOS published in 2000"

Gated-V/sub dd/: a circuit technique to reduce leakage in deep-submicron cache memories

Abstract: Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applications. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instruction caches. We propose, gated-V/sub dd/, a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V/sub dd/ together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line

Abstract: This paper describes a CMOS time-to-digital converter (TDC) integrated circuit utilizing tapped delay lines. A technique that allows the achievement of high resolution with low dead-time is presented, The technique is based on a Vernier delay line (VDL) used in conjunction with an asynchronous read-out circuitry. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. A test circuit fabricated in a standard 0.7-/spl mu/m digital CMOS process is presented. The TDC contains 128 delay stages and achieves 30-ps resolution, stabilized by the DLL, with the accuracy exceeding /spl plusmn/1 LSB. Test results show that even higher resolutions can be achieved using the VDL method, and resolutions down to 5 ps are demonstrated to be obtainable.

Impact of CMOS technology scaling on the atmospheric neutron soft error rate

Abstract: We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L/sub G/. A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear. If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.

Investigation of candidate VRM topologies for future microprocessors

Abstract: By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented.

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Low power CMOS VLSI circuit design

Abstract: Low--Power CMOS VLSI Design. Physics of Power Dissipation in CMOS FET Devices. Power Estimation. Synthesis for Low Power. Design and Test of Low--Voltage CMOS Circuits. Low--Power Static Ram Architectures. Low--Energy Computing Using Energy Recovery Techniques. Software Design for Low Power. Index.

Dual-threshold voltage techniques for low-power digital circuits

Abstract: Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

A noise-based IC random number generator for applications in cryptography

Abstract: The design of a mixed-signal random number generator (RNG) integrated circuit (IC) suitable for integration with hardware cryptographic systems is presented. Certain applications in cryptography require the use of a truly RNG, a device which produces unpredictable and unbiased digital signals derived from a fundamental noise mechanism. For IC-based cryptographic systems, an RNG must harness randomness from a low-power noise signal yet remain insensitive to deterministic influences such as crosstalk, power supply noise, and clock signal coupling through the substrate. An RNG IC utilizing established analog IC design techniques was designed and fabricated in a 2-/spl mu/m CMOS technology. Sequences generated by the experimental system repeatedly passed many standard randomness tests for bit rates up to 1.4 MHz. No changes in randomness performance were observed as the system was exposed to power supply noise and substrate signal coupling. The system occupies a total chip area of 1.5 mm/sup 2/ and dissipates 3.9 mW of power.

Bandwidth extension in CMOS with optimized on-chip inductors

Abstract: We present a technique for enhancing the bandwidth of gigahertz broad-band circuitry by using optimized on-chip spiral inductors as shunt-peaking elements. The series resistance of the on-chip inductor is incorporated as part of the load resistance to permit a large inductance to be realized with minimum area and capacitance. Simple, accurate inductance expressions are used in a lumped circuit inductor model to allow the passive and active components in the circuit to be simultaneously optimized. A quick and efficient global optimization method, based on geometric programming, is discussed. The bandwidth extension technique is applied in the implementation of a 2.125-Gbaud preamplifier that employs a common-gate input stage followed by a cascoded common-source stage. On-chip shunt peaking is introduced at the dominant pole to improve the overall system performance, including a 40% increase in the transimpedance. This implementation achieves a 1.6-k/spl Omega/ transimpedance and a 0.6-/spl mu/A input-referred current noise, while operating with a photodiode capacitance of 0.6 pF. A fully differential topology ensures good substrate and supply noise immunity. The amplifier, implemented in a triple-metal, single-poly, 14-GHz f/sub Tmax/, 0.5-/spl mu/m CMOS process, dissipates 225 mW, of which 110 mW is consumed by the 50-/spl Omega/ output driver stage. The optimized on-chip inductors consume only 15% of the total area of 0.6 mm/sup 2/.

A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology

Abstract: A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 /spl mu/m bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider.

CMOS transconductance amplifiers, architectures and active filters: a tutorial

Abstract: An updated version of a 1985 tutorial paper on active filters using operational transconductance amplifiers (OTAs) is presented. The integrated circuit issues involved in active filters (using CMOS transconductance amplifiers) and the progress in this field in the last 15 years is addressed. CMOS transconductance amplifiers, nonlinearised and linearised, as well as frequency limitations and dynamic range considerations are reviewed. OTA-C filter architectures, current-mode filters, and other potential applications of transconductance amplifiers are discussed.

An analytical solution to a double-gate MOSFET with undoped body

Abstract: A one-dimensional (1-D) analytical solution is derived for an undoped (or lightly-doped) double-gate MOSFET by incorporating only the mobile charge term in Poisson's equation. The solution gives closed forms of band bending and volume inversion as a function of silicon thickness and gate voltage. A threshold criterion is derived which serves to quantify the gate work function requirements for a double-gate CMOS.

CMOS Data Converters for Communications

Abstract: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

A 5-GHz CMOS wireless LAN receiver front end

Abstract: This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-/spl mu/m CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm.

A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC

Abstract: A low-power 10-bit converter that can sample input frequencies above 100 MHz is presented. The converter consumes 55 mW when sampling at f/sub s/=40 MHz from a 3-V supply, which also includes a bandgap and a reference circuit (70 mW if including digital drivers with a 10-pF load). It exhibits higher than 9.5 effective number of bits for an input frequency at Nyquist (f/sub in/=f/sub s//2=20 MHz). The differential and integral nonlinearity of the converter are within /spl plusmn/0.3 and /spl plusmn/0.75 LSB, respectively, when sampling at 40 MHz, and improve to a 12-bit accuracy level for lower sampling rates. The overall performance is achieved using a pipelined architecture without a dedicated sample/hold amplifier circuit at the input. The converter is implemented in double-poly, triple-metal 0.35-/spl mu/m CMOS technology and occupies an area of 2.6 mm/sup 2/.

Low-power area-efficient high-speed I/O circuit techniques

Abstract: We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.

A logarithmic response CMOS image sensor with on-chip calibration

Abstract: CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525/spl times/525 pixels measuring 7.5 /spl mu/m/spl times/10 /spl mu/m, and is fabricated in a 0.5-/spl mu/m CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range.

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current

Abstract: A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level.

A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications

Abstract: One approach to implementation of low-phase-noise integrated fixed-frequency local oscillators (LOs) for use as the RF LO in a blockdown-convert receiver architecture for PCS wireless communications down-converts the entire RF band to a lower frequency using a fixed-frequency LO. This allows new approaches to the implementation of low-phase-noise oscillators with low-Q components. The technique uses a DLL-based frequency multiplier to synthesize a RF LO whose phase noise is closely related to that of the reference crystal and not dependent on the phase noise of a VCO. An experimental prototype generates a 900 MHz signal and is designed to meet the requirements of the IS-137 standard. The device achieves a phase noise of -123dBc/Hz at a 60 kHz offset frequency with 39 mA overall current consumption from a 3.3 V supply. This prototype was fabricated in 0.35 /spl mu/m double-poly five-metal CMOS.

Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layer

Abstract: A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region. Removal of unwanted regions of metal, and of in situ polysilicon, result in the definition of a metal gate structure, on the high k gate insulator layer, in the NMOS region, and in the definition of a metal—in situ doped polysilicon gate structure, on the high k gate insulator layer, in the PMOS region, with both gate structures embedded in openings in the composite insulator layer, previously formed via removal of the silicon nitride dummy gate structures.

Charge pump with perfect current matching characteristics in phase-locked loops

Abstract: Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLL output signals. In particular, it reduces the locking range in wide range PLLs with a dual loop scheme. A new charge pump circuit with perfect current matching characteristics is proposed. By using an error amplifier and reference current sources, one can achieve a charge pump with good current matching characteristics. It shows nearly perfect current matching characteristics over the whole VCO input range, and the amount of the reference spur is <-75 dBc in the PLL output signal. The charge pump circuit is implemented in a 0.25 /spl mu/m CMOS process.

Intermodulation distortion in current-commutating CMOS mixers

Abstract: The nonlinearity behavior of CMOS current-switching mixers is investigated. By treating the mixer as a periodically-time-varying weakly nonlinear circuit, we study the distortion-causing mechanisms and we predict the mixer distortion performance. Normalized graphs are provided from which the designer can readily estimate the mixer nonlinearity for particular process and design parameters. A simple CMOS transistor model appropriate for our calculations, which also takes into account deviation from the square law is adopted. The significance of a physical transistor model for reliable distortion simulation is demonstrated. The prediction of our analysis is compared with simulation results and with experimental data.

Active capacitor multiplier in Miller-compensated circuits

Abstract: A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-/spl mu/m BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 /spl Omega/, and load capacitors ranging from 1.5 nF to 20 /spl mu/E The total quiescent current flowing through the regulator was less than 30 /spl mu/A during zero load-current conditions.

BSIM4 gate leakage model including source-drain partition

Abstract: Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

Abstract: The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

A 3 GHz, 32 dB CMOS limiting amplifier for SONET OC-48 receivers

Abstract: An optical receiver front-end for SONET OC-48 (2.5 Gb/s) is shown. The limiting amplifier (LA) receives a small-non-return to zero (NRZ) voltage signal (e.g., 8 mV/sub pp/) from the transimpedance amplifier (TIA) and amplifies it to a level (e.g. 250 mV/sub pp/) sufficient for the reliable operation of the clock and data recovery circuit. The noise contribution of the LA must be small compared to that of the TIA so that the overall bit error rate and sensitivity are not affected adversely. Currently, commercial 2.5 Gb/s SONET systems are composed of several discrete chips implemented in GaAs and more recently silicon bipolar technology. The future trend, however, is to integrate most of the front-end together with the digital framer on a single CMOS chip. Furthermore, the integration of multiple 2.5 Gb/s channels on a single CMOS chip is desirable for wavelength division multiplexing (WDM) application. CMOS amplifiers for optical receivers and related applications with bandwidths up to 2.1 GHz are recently reported. This CMOS limiting amplifier with improved bandwidth (3 GHz) and noise figure (16 dB) is suitable for 2.5 Gb/s SONET receivers. Power dissipation is 53 mW and the chip is fabricated in a standard 2.5 V, 0.25 /spl mu/m CMOS technology. This result is achieved with: (i) Inverse scaling to increase gain-bandwidth and reduce power dissipation while keeping noise and offset voltage low and (ii) active inductors to increase gain-bandwidth and improve gain stability. The active area of the amplifier is 0.03 mm/sup 2/, less than 10% that of a comparable design with spiral inductors.

A 2 V CMOS cellular transceiver front-end

Abstract: This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply

Abstract: The design and experimental evaluation of a clocked adiabatic logic (GAL) is described in this paper. CAL is a dual-rail logic that operates from a single-phase AC power-clock supply. This new low-energy logic makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution. CAL can also be operated from a DC power supply in a nonenergy-recovery mode compatible with standard CMOS logic. In the adiabatic mode, the power-clock supply waveform is generated using an on-chip switching transistor and a small external inductor between the chip and a low-voltage DC supply. Circuit operation and performance are evaluated using a chain of inverters realized in a 1.2 /spl mu/m CMOS technology. Experimental results show that energy savings are achieved at clock frequencies up to about 40 MHz as compared to the nonadiabatic mode. Since CAL can operate both in adiabatic and nonadiabatic modes, power management strategies may be based upon switching between modes when necessary.

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Abstract: Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

A novel high-performance CMOS 1-bit full-adder cell

Abstract: A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates, pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved.