Showing papers on "CMOS published in 2001"

High-κ gate dielectrics: Current status and materials properties considerations

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Device scaling limits of Si MOSFETs and their application dependencies

Abstract: This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Vibration-to-electric energy conversion

Abstract: A system is proposed to convert ambient mechanical vibration into electrical energy for use in powering autonomous low power electronic systems. The energy is transduced through the use of a variable capacitor. Using microelectromechanical systems (MEMS) technology, such a device has been designed for the system. A low-power controller IC has been fabricated in a 0.6-/spl mu/m CMOS process and has been tested and measured for losses. Based on the tests, the system is expected to produce 8 /spl mu/W of usable power. In addition to the fabricated programmable controller, an ultra low-power delay locked loop (DLL)-based system capable of autonomously achieving a steady-state lock to the vibration frequency is described.

The impact of intrinsic device fluctuations on CMOS SRAM cell stability

Abstract: Reductions in CMOS SRAM cell static noise margin (SNM) due to intrinsic threshold voltage fluctuations in uniformly doped minimum-geometry cell MOSFETs are investigated for the first time using compact physical and stochastic models. Six sigma deviations in SNM due to intrinsic fluctuations alone are projected to exceed the nominal SMM for sub-100-nm CMOS technology generations. These large deviations pose severe barriers to scaling of supply voltage, channel length, and transistor count for conventional 6T SRAM-dominated CMOS ASICs and microprocessors.

CMOS mixers and polyphase filters for large image rejection

Abstract: This paper presents an in-depth treatment of mixers and polyphase filters, and how they are used in rejecting the image in transmitters and receivers. A powerful phasor-based analysis is used to explain all common image-reject topologies and their limitations, and it is shown how this can replace complex trigonometric equations commonly found in the literature. Practical problems in design and layout that limit the performance of image-reject upconversion and downconversion mixers are identified, and solutions are presented or limits explained. This understanding is put to work in a low-IF CMOS wideband, low-IF downconversion circuit, which repeatedly rejects the image by 60 dB over the wide band of 3.5 to 20 MHz without trimming or calibration.

Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits

Abstract: Mutual compensation of mobility and threshold voltage temperature variations may result in a zero temperature coefficient bias point of a MOS transistor. The conditions under which this effect occurs, and stability of this bias point are investigated. Possible applications of this effect include voltage reference circuits and temperature sensors with linear dependence of voltage versus temperature. The theory is verified experimentally investigating the temperature behavior of a simple voltage reference circuit realized in 0.35 /spl mu/m CMOS process.

CMOS active pixel sensor type imaging system on a chip

Abstract: Single substrate device is formed to have an image acquistition device and a controller. The controller on the substrate controls the system operation.

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

Abstract: This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

Sub-50 nm P-channel FinFET

Abstract: High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I/sub dsat/ of 820 /spl mu/A//spl mu/m at V/sub ds/=V/sub gs/=1.2 V and T/sub ox/=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm.

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Abstract: A highly integrated 175-GHz 035-/spl mu/m CMOS transmitter is described The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 13/spl deg/ rms phase error when modulating a DCS-1800 GMSK signal The prototype consumed 151 mA from a 3-V supply A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance

A monolithic active pixel sensor for charged particle tracking and imaging using standard VLSI CMOS technology

Abstract: A novel Monolithic Active Pixel Sensor (MAPS) for charged particle tracking made in a standard CMOS technology is proposed. The sensor is a photodiode, which is readily available in a CMOS technology. The diode has a special structure, which allows the high detection efficiency required for tracking applications. The partially depleted thin epitaxial silicon layer is used as a sensitive detector volume. Semiconductor device simulation, using either ToSCA based or 3-D ISE-TCAD software packages shows that the charge collection is efficient, reasonably fast (order of 100 ns), and the charge spreading limited to a few pixels only. A first prototype has been designed, fabricated and tested. It is made of four arrays each containing 64×64 pixels, with a readout pitch of 20 μm in both directions. The device is fabricated using standard submicron 0.6 μm CMOS process, which features twin-tub implanted in a p-type epitaxial layer, a characteristic common to many modern CMOS VLSI processes. Extensive tests made with soft X-ray source ( 55 Fe) and minimum ionising particles (15 GeV/ c pions) fully demonstrate the predicted performances, with the individual pixel noise (ENC) below 20 electrons and the Signal-to-Noise ratio for both 5.9 keV X-rays and Minimum Ionising Particles (MIP) of the order of 30. This novel device opens new perspectives in high-precision vertex detectors in Particle Physics experiments, as well as in other application, like low-energy beta particle imaging, visible light single photon imaging (using the Hybrid Photon Detector approach) and high-precision slow neutron imaging.

A 10000 frames/s CMOS digital pixel sensor

Abstract: A 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4/spl times/9.4 /spl mu/m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 /spl mu/V/e/sup -/. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

Abstract: In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

Design and results from the APV25, a deep sub-micron CMOS front-end chip for the CMS tracker

Abstract: The APV25 is a 128-channel analogue pipeline chip for the readout of silicon microstrip detectors in the CMS tracker at the LHC. Each channel comprises a low noise amplifier, a 192-cell analogue pipeline and a deconvolution readout circuit. Output data are transmitted on a single differential current output via an analogue multiplexer. The chip is fabricated in a standard 0.25 μm CMOS process to take advantage of the radiation tolerance, lower noise and power, and high circuit density. Experimental characterisation of this circuit shows full functionality and good performance both in pre- and post-irradiation (20 Mrad) conditions. The measured noise is significantly reduced compared to earlier APV versions. A description of the design and results from measurements prior to irradiation are presented.

Stacked inductors and transformers in CMOS technology

Abstract: A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values of 5 to 266 nH and self-resonance frequencies of 11.2 to 0.5 GHz. Closed-form expressions predicting the self-resonance frequency with less than 5% error have also been developed. Stacked transformers are also introduced that achieve voltage gains of 1.8 to 3 at multigigahertz frequencies. The structures have been fabricated in standard digital CMOS technologies with four and five metal layers.

Sub-20 nm CMOS FinFET technologies

Abstract: A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000). Two different patterning approaches-e-beam lithography and spacer lithography-are developed. Selective Ge by LPCVD is utilized to fabricate raised S/D structures which minimize parasitic series resistance and improve drive current.

Very low-voltage digital-audio /spl Delta//spl Sigma/ modulator with 88-dB dynamic range using local switch bootstrapping

Abstract: A 1-V 1-mW 14-bit /spl Delta//spl Sigma/ modulator in a standard CMOS 0.35-/spl mu/m technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz.

Rotary traveling-wave oscillator arrays: a new clock technology

Abstract: Rotary traveling-wave oscillators (RTWOs) represent a new transmission-line approach to gigahertz-rate clock generation. Using the inherently stable LC characteristics of on-chip VLSI interconnect, the clock distribution network becomes a low-impedance distributed oscillator. The RTWO operates by creating a rotating traveling wave within a closed-loop differential transmission line. Distributed CMOS inverters serve as both transmission-line amplifiers and latches to power the oscillation and ensure rotational lock. Load capacitance is absorbed into the transmission-line constants whereby energy is recirculated giving an adiabatic quality. Unusually for an LC oscillator, multiphase (360/spl deg/) square waves are produced directly. RTWO structures are compact and can be wired together to form rotary oscillator arrays (ROAs) to distribute a phase-locked clock over a large chip. The principle is scalable to very high clock frequencies. Issues related to interconnect and field coupling dominate the design process for RTWOs. Taking precautions to avoid unwanted signal couplings, the rise and fall times of 20 ps, suggested by simulation, may be realized at low power consumption. Experimental results of the 0.25-/spl mu/m CMOS test chip with 950-MHz and 3.4-GHz rings are presented, indicating 5,5-ps jitter and 34-dB power supply rejection ratio (PSRR). Design errors in the test chip precluded meaningful rise and fall time measurements.

A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input

Abstract: This paper describes the design of a 14-b 75-Msample/s pipeline analog-to-digital converter (ADC) implemented in a 0.35-/spl mu/m double-poly triple-metal CMOS process. The ADC uses a 4-b first stage to relax capacitor-matching requirements, buffered bootstrapping to reduce signal-dependent charge injection, and a flip-around track-and-hold amplifier with wide common-mode compliance to reduce noise and power consumption. It achieves 14-b accuracy without calibration or dithering. Typical differential nonlinearity is 0.6 LSB, and integral nonlinearity is 2 LSB. The ADC also achieves 73-dB signal-to-noise ratio, and 85-dB spurious-free dynamic range over the first Nyquist band. The 7.8-mm/sup 2/ ADC operates with a 2.7- to 3.6-V supply, and dissipates 340 mW at 3 V.

Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement

Abstract: We have developed a new technique, called "local mechanical-stress control" (LMC), to enhance CMOS current drivability It utilizes high mechanical stress produced by a SiN layer and Ge-ion implantation to selectively relax the stress of the layer The drive currents of both n- and p-MOSFETs can be improved by controlling the stress of the SiN layer selectively The effects of LMC become more significant as devices become smaller, and the drive current is estimated to increase by more than 20% in future 70-nm CMOS technology

Low-voltage low-power CMOS full adder

Abstract: Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.

RF-CMOS performance trends

Abstract: The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

Abstract: A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-/spl mu/m CMOS technology in an area of 1.1/spl times/0.9 mm/sup 2/, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28/spl times/10/sup -6/, with random data input of length 2/sup 23/-1. The power dissipation is 72 mW from a 2.5-V supply.

Robust subthreshold logic for ultra-low power operation

Abstract: Digital subthreshold logic circuits can be used for applications in the ultra-low power end of the design spectrum, where performance is of secondary importance. In this paper, we propose two different subthreshold logic families: 1) variable threshold voltage subthreshold CMOS (VT-Sub-CMOS) and 2) subthreshold dynamic threshold voltage MOS (Sub-DTMOS) logic. Both logic families have comparable power consumption as regular subthreshold CMOS logic (which is up to six orders of magnitude lower than that of normal strong inversion circuit) with superior robustness and tolerance to process and temperature variations than that of regular subthreshold CMOS logic.

CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs

Abstract: A CMOS inverter having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and a pMOSFET and an nMOSFET, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides an integrated circuit having a heterostructure including a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and a p transistor and an n transistor formed in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Abstract: Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is for switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchirectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit level approach to reducing leakage energy in instruction caches (i-caches). At the architectural level, we propose the Dynamically Resizable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-V/sub dd/, a mechanism that effectively turns of the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robust exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64K DRI i-cache reduces on average both the leakage energy-delay product and cache size 62%, with less than 4% impact on execution time.

Carbon nanotube field-effect inverters

Abstract: This letter presents p-type metal–oxide–semiconductor (PMOS) and complementary metal–oxide–semiconductor (CMOS) inverters based on single-walled carbon nanotube field-effect transistors. The device structures consist of carbon nanotubes grown via a chemical-vapor deposition method and contacted by two metallic source/drain electrodes. Electrical properties of both p-type (without doping) and n-type nanotube transistors with potassium doping have been measured. By utilizing a resistor as the load for a p-type nanotube field-effect transistor, a PMOS inverter is demonstrated. Furthermore, by connecting a p-type nanotube transistor and an n-type nanotube transistor, a CMOS inverter is demonstrated. Both types of inverters exhibit nice transfer characteristics at room temperature. Our work represents one step forward toward integrated circuits based on nanoelectronic devices.

Multi-layered gate for a CMOS imager

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

A 2.4 GHz CMOS transceiver for Bluetooth

Abstract: A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset.

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Abstract: Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical double-gate (DG) CMOS, utilizing n/sup +/ and p/sup +/ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons, only one of which is its previously noted threshold-voltage control. The most noteworthy result is that asymmetrical DG MOSFETs, optimally designed with only one predominant channel, yield comparable, and even higher drive currents at low supply voltages. The simulations further give good physical insight pertaining to the design of DG devices with channel lengths of 50 nm and less.