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Showing papers on "CMOS published in 2004"


Journal Article
TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Abstract: 53 ■ IEEE CIRCUITS & DEVICES MAGAZINE ■ NOVEMBER/DECEMBER 2005 THE DESIGN OF CMOS RADIOFREQUENCY INTEGRATED CIRCUITS, 2ND ED By Thomas Lee, Cambridge University Press, 2003. All-CMOS radio transceivers and system-on-a-chip are rapidly making inroads into a wireless market that, for years, was dominated by bipolar solutions. On wireless LAN and Bluethooth, RF CMOS is especially dominant, and it is becoming also in GSM cellular and GPS receivers. Hence, books that cover this widespread domain respond to a real need. The first edition of this book, published on 1998, was a pioneering textbook on the field of RF CMOS design. This second edition is a very interesting and upgraded version that includes new material and revised topics. In particular, it now includes a chapter on the fundamentals of wireless systems. The chapter on IC components is greatly expanded and now follows that on passive RLC components. The chapter on MOS devices has been updated since it includes the understanding of the model for the shorth-channel MOS and considers and discusses the scaling trends and its impact on the next several years. It has also expanded the topic of power amplifiers; indeed, it now also covers techniques for linearization and efficiency enhancement. Low-noise amplifiers, oscillators, and phase noise are now expanded and treated with more detail. Moreover, the chapter on transceiver architectures now includes much more detail, especially on direct-conversion architecture. Finally, additional commentary on practical details on simulations, floorplanning, and packaging has been added. The first edition of this book widely covered all the main arguments needed in the CMOS design context and provided a bridge between system and circuit issues. This second edition, which is upgraded and improved, is really useful, both in the industry and academia, for the new generation of RF engineers. Indeed, it is suited for students taking courses on RF design and is a valuable reference for practicing engineers. Of course, the arguments treated in the textbook lead up to low-frequency analog design IC topics. Hence, readers have to be intimately familiar with that subject. The book is divided into 20 chapters: 1) A Nonlinear History of Radio 2) Overview of Wireless Principles 3) Passive RLC Networks 4) Characteristics of Passive IC Components 5) A Review of MOS Device Physics; 6) Distributed Systems 7) The Smith Chart and S-Parameters 8) Bandwidth Estimation Techniques 9) High-Frequency Amplifier Design 10) Voltage References and Biasing 11) Noise 12) LNA Design 13) Mixers 14) Feedback Amplifiers 15) RF Power Amplifiers 16) Phase Locked Loop 17) Oscillators and Synthesizers 18) Phase Noise 19) Architectures 20) RF Circuits Through the Ages. Moreover, it contains over 100 circuit diagrams and many homework problems. Gaetano Palumbo

3,949 citations


Journal ArticleDOI
TL;DR: In this article, a feed-forward noise-canceling technique is proposed to cancel the noise and distortion contributions of the matching device, which allows for designing wide-band impedance-matching amplifiers with noise figure (NF) well below 3 dB.
Abstract: Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

749 citations


Journal ArticleDOI
TL;DR: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter using a 0.18-/spl mu/m CMOS process achieves a power gain of 9.3 dB with an input match of -10 dB over the band.
Abstract: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

714 citations


Proceedings ArticleDOI
13 Dec 2004
TL;DR: In this article, a simple binary transition metal oxide (TMO) resistive random access memory (RRAM) was integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties were reported for the first time.
Abstract: Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.

672 citations


Journal ArticleDOI
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.
Abstract: Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

561 citations


Journal ArticleDOI
TL;DR: In this article, four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology are reviewed and analyzed: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-consistency with SNIM (PCSNIM) techniques.
Abstract: This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.

542 citations


Journal ArticleDOI
T. Karnik1, P. Hazucha1
TL;DR: This paper presents radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits, and discusses the impact of SEUs on system reliability.
Abstract: Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

531 citations


Proceedings ArticleDOI
27 Jun 2004
TL;DR: A CMOS-based time-of-flight depth sensor based on a special CMOS pixel structure that can extract phase information from the received light pulses that offers significant advantages, including superior accuracy, high frame rate, cost effectiveness and a drastic reduction in processing required to construct the depth maps.
Abstract: This paper describes a CMOS-based time-of-flight depth sensor and presents some experimental data while addressing various issues arising from its use. Our system is a single-chip solution based on a special CMOS pixel structure that can extract phase information from the received light pulses. The sensor chip integrates a 64x64 pixel array with a high-speed clock generator and ADC. A unique advantage of the chip is that it can be manufactured with an ordinary CMOS process. Compared with other types of depth sensors reported in the literature, our solution offers significant advantages, including superior accuracy, high frame rate, cost effectiveness and a drastic reduction in processing required to construct the depth maps. We explain the factors that determine the resolution of our system, discuss various problems that a time-of-flight depth sensor might face, and propose practical solutions.

528 citations


Journal ArticleDOI
TL;DR: A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this article, where the measured absolute error between the sensed signal and the inductor current is less than 4%.
Abstract: A monolithic current-mode CMOS DC-DC converter with integrated power switches and a novel on-chip current sensor for feedback control is presented in this paper. With the proposed accurate on-chip current sensor, the sensed inductor current, combined with the internal ramp signal, can be used for current-mode DC-DC converter feedback control. In addition, no external components and no extra I/O pins are needed for the current-mode controller. The DC-DC converter has been fabricated with a standard 0.6-/spl mu/m CMOS process. The measured absolute error between the sensed signal and the inductor current is less than 4%. Experimental results show that this converter with on-chip current sensor can operate from 300 kHz to 1 MHz with supply voltage from 3 to 5.2 V, which is suitable for single-cell lithium-ion battery supply applications. The output ripple voltage is about 20 mV with a 10-/spl mu/F off-chip capacitor and 4.7-/spl mu/H off-chip inductor. The power efficiency is over 80% for load current from 50 to 450 mA.

513 citations


Journal ArticleDOI
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Abstract: The metal oxide semiconductor field effect transistor (MOSFET) is scaling to a “tunneling epoch”, in which multiple leakage current induced by different tunneling effects exist. The complementary Si-based tunneling transistors are presented in this paper. The working principle of this device is investigated in detail. It is found that the band-to-band tunneling current is be controlled by the gate-to-source voltage. Due to the reverse biased p-i-n diode structure, an ultra-low leakage current is achieved. The sub-threshold swing of TFET is not limited by kt/q, which is the physical limit of the MOSFET. Using the CMOS compatible processes, the complementary TFETs (CTFET) are fabricated on one wafer. From a circuit point of view, the compatibility between TFET and MOSFET enables the transfer of CMOS circuits to CTFET circuits.

428 citations


Journal ArticleDOI
TL;DR: For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.
Abstract: Double-gate devices will enable the continuation of CMOS scaling after conventional scaling has stalled. DGCMOS/FinFET technology offers a tactical solution to the gate dielectric barrier and a strategic path for silicon scaling to the point where only atomic fluctuations halt further progress. The conventional nature of the processes required to fabricate these structures has enabled rapid experimental progress in just a few years. Fully integrated CMOS circuits have been demonstrated in a 180 nm foundry-compatible process, and methods for mapping conventional, planar CMOS product designs to FinFET have been developed. For both low-power and high-performance applications, DGCMOS-FinFET offers a most promising direction for continued progress in VLSI.

Journal ArticleDOI
06 Jun 2004
TL;DR: In this paper, a modified derivative-superposition (DS) method was proposed to increase the maximum IIP3 at RF frequencies, which was used in a 0.25mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple access receivers.
Abstract: Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

Journal ArticleDOI
TL;DR: Simulation results show that the 4- 2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.
Abstract: This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

Journal ArticleDOI
13 Sep 2004
TL;DR: In this paper, a very low power interface IC used in implantable pacemaker systems is presented, which contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control.
Abstract: Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

Journal ArticleDOI
TL;DR: System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.
Abstract: With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, the cost of the 60 GHz electronics, implemented in the compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution has the potential to drastically reduce costs enough to hit consumer price points. System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.

Journal ArticleDOI
TL;DR: In this paper, the production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies.
Abstract: The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Journal ArticleDOI
Tae Wook Kim1, Bonkee Kim, Kwyro Lee1
TL;DR: In this article, a high-level linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported.
Abstract: Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

Journal ArticleDOI
TL;DR: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators, which features wide locking ranges, a very low input capacitance, and highest frequency capability.
Abstract: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

Journal ArticleDOI
TL;DR: Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
Abstract: The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, nMOS and pMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only a 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Experimental results on the sequential circuits in the MCNC91 benchmark suit show that, by using the proposed method, it is possible to reduce the leakage by an average of 25% with practically no delay penalty.

Journal ArticleDOI
TL;DR: In this paper, the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply.
Abstract: This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-/spl mu/m 1M/2P N-epi BiCMOS, and the AMI 1.5-/spl mu/m 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm/sup 2/ in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range.

Proceedings ArticleDOI
15 Jun 2004
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Abstract: A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

Journal ArticleDOI
TL;DR: In this paper, the first 24 GHz CMOS front-end in a 0.18/spl mu/m process was reported, which consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz.
Abstract: This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.

Journal ArticleDOI
13 Sep 2004
TL;DR: In this paper, a reconfigurable LSI employing a nonvolatile nanometer-scale switch, called NanoBridge, is proposed, and its basic operations are demonstrated, and operational tests with them have confirmed the switch's potential for use in programmable logic arrays.
Abstract: A reconfigurable LSI employing a nonvolatile nanometer-scale switch, NanoBridge, is proposed, and its basic operations are demonstrated. The switch, composed of solid electrolyte copper sulfide, has a <30-nm contact diameter and <100-/spl Omega/ on-resistance. Because of its small size, it can be used to create extremely dense field-programmable logic arrays. A 4 /spl times/ 4 crossbar switch and a 2-input look-up-table circuit are fabricated with 0.18-/spl mu/m CMOS technology, and operational tests with them have confirmed the switch's potential for use in programmable logic arrays. A 1-kb nonvolatile memory is also presented, and its potential for use as a low-voltage memory device is demonstrated.

Proceedings ArticleDOI
13 Sep 2004
TL;DR: A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported, which achieves a power gain of 9.3 dB with an input match of 9 mW.
Abstract: A UWB 3.1 to 10.6 GHz LNA employing an input three-section band-pass Chebyshev filter is reported. Fabricated in a 0.18 /spl mu/m CMOS process, -10 dB over the band, a NF of 4 dB, and an IIP3 of -6.7 dBm while consuming the IC achieves a power gain of 9.3 dB with an input match of 9 mW.

Journal ArticleDOI
TL;DR: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described.
Abstract: A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-/spl mu/m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm/sup 2/ and dissipates 98 mW.

Proceedings ArticleDOI
13 Sep 2004
TL;DR: Logic and memory design techniques allowing subthreshold operation are developed and demonstrated and the fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.
Abstract: Minimizing energy requires scaling supply voltages below device thresholds. Logic and memory design techniques allowing subthreshold operation are developed and demonstrated. The fabricated 1024-point FFT processor operates down to 180mV using a standard 0.18/spl mu/m CMOS logic process while using 155nJ/FFT at the optimal operating point.

Patent
30 Aug 2004
TL;DR: In this paper, structural, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are described. Butts are separated from the channel region by a gate insulator.
Abstract: Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate includes a ternary metallic conductor formed by atomic layer deposition.

Journal ArticleDOI
TL;DR: In this article, a regenerative divide topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances, achieving a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.
Abstract: An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

Journal ArticleDOI
TL;DR: In this paper, a large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation.
Abstract: A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

Journal ArticleDOI
TL;DR: In this article, an improved micro-scale thermoelectric generator (μ-TEG) is proposed based on polysilicon surface micromachining and is designed to convert waste heat into electrical power.
Abstract: As the power consumption of a large number of microelectronic devices has been continuously reduced in recent years, power supply units of a few microwatts have become sufficient for their operation. Our improved micro-scale thermoelectric generator (μ-TEG) is based on polysilicon surface micromachining and is designed to convert waste heat into electrical power. Since this device is compatible with standard CMOS fabrication processes, it can be easily integrated on chip level and matches the needs for low-cost and small-size systems. As thermoelectric materials, both, pure poly-Si and poly-Si 70% Ge 30% have been investigated. Emphasis was placed on a thermally optimized design and the reduction of the total electrical resistance of the generator. As a result of these improvements, a voltage of 5 V and an electrical power output of 1 μW for a matched consumer is achieved with generators of 1 cm 2 in size at a temperature drop of about 5 K.