Showing papers on "CMOS published in 2007"

Measuring the Gap Between FPGAs and ASICs

Abstract: This paper presents experimental measurements of the differences between a 90-nm CMOS field programmable gate array (FPGA) and 90-nm CMOS standard-cell application-specific integrated circuits (ASICs) in terms of logic density, circuit speed, and power consumption for core logic. We are motivated to make these measurements to enable system designers to make better informed choices between these two media and to give insight to FPGA makers on the deficiencies to attack and, thereby, improve FPGAs. We describe the methodology by which the measurements were obtained and show that, for circuits containing only look-up table-based logic and flip-flops, the ratio of silicon area required to implement them in FPGAs and ASICs is on average 35. Modern FPGAs also contain "hard" blocks such as multiplier/accumulators and block memories. We find that these blocks reduce this average area gap significantly to as little as 18 for our benchmarks, and we estimate that extensive use of these hard blocks could potentially lower the gap to below five. The ratio of critical-path delay, from FPGA to ASIC, is roughly three to four with less influence from block memory and hard multipliers. The dynamic power consumption ratio is approximately 14 times and, with hard blocks, this gap generally becomes smaller

FinFETs and Other Multi-Gate Transistors

Abstract: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS

Abstract: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz. The 15-F04 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking

Abstract: This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance.

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

Abstract: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

Full On-Chip CMOS Low-Dropout Voltage Regulator

Abstract: This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (AC) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-mum CMOS technology, consuming only 65 muA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures.

High performance, waveguide integrated Ge photodetectors

Abstract: Photonic systems based on complementary metal oxide semiconductor (CMOS) technology require the integration of passive and active photonic devices. The integration of waveguides and photodetector is one of the most important technologies. We report a Ge p-i-n photodetector that is monolithically integrated with silicon oxynitride and silicon nitride waveguides. All processes and materials are CMOS compatible and can be implemented in the current integrated circuit process technology. The small size of the devices results in low absolute dark current. The waveguide-coupled Ge devices show high efficiency (~90%) over a wide range of wavelengths well beyond the direct band gap of Ge, resulting in a responsivity of 1.08 A/W for 1550 nm light. The device speed of 7.2 GHz at 1V reverse bias is strongly affected by the capacitance of the probe pads. The high-performance of the devices at low voltage (≤ 1V) facilitates the integration with CMOS circuits.

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Abstract: Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic design methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor fT/fMAX of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth >13 GHz, a P 1dB of +6.4 dBm with 7% PAE and a saturated output power of +9.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13-mum CMOS technologies. It features 14.6 dB gain, an IIP 3 of -6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring 0.35times0.43 mm2 and 0.35times0.40 mm2, respectively

Spin-based logic in semiconductors for reconfigurable large-scale circuits

Abstract: Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors, spin injection into semiconductors from ferromagnetic metals and discoveries of new physical phenomena involving electron spin. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward-spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a 'spin computer'. As the shrinking of conventional complementary metal-oxide-semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.

A Broadband Noise-Canceling CMOS LNA for 3.1–10.6-GHz UWB Receivers

Abstract: An ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-mum CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 mW from a 1.8-V supply and occupies an area of only 0.59 mm2

A 60 $\mu$ W 60 nV/ $\surd$ Hz Readout Front-End for Portable Biopotential Acquisition Systems

Abstract: There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

Abstract: A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

Nano/CMOS architectures using a field-programmable nanowire interconnect

Abstract: A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 × to 25 ×), reduced power, slightly lower clock speeds, and high defect tolerance—an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires.

Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology

Abstract: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Abstract: Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC

Abstract: A 500-MS/s 5-bit ADC for UWB applications has been fabricated in a 65-nm CMOS technology using no analog-specific processing options. The time-interleaved successive approximation register (SAR) architecture has been chosen due to its simplicity versus flash and its amenability to scaled technologies versus pipelined, which relies on operational amplifiers. Six time-interleaved channels are used, sharing a single clock operating at the composite sampling rate. Each channel has a split capacitor array that reduces switching energy, increases speed, and has similar INL and decreased DNL, as compared to a conventional binary-weighted array. A variable delay line adjusts the instant of latch strobing to reduce preamplifier currents. The ADC achieves Nyquist performance, with an SNDR of 27.8 and 26.1 dB for 3.3and 239 MHz inputs, respectively. The total active area is 0.9mm2, and the ADC consumes 6 mW from a 1.2-V supply

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Abstract: Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 X higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 X 132 mum2test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 mus measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

Low-Power CMOS Rectifier Design for RFID Applications

Abstract: We investigate theoretical and practical aspects of the design of far-field RF power extraction systems consisting of antennas, impedance matching networks and rectifiers. Fundamental physical relationships that link the operating bandwidth and range are related to technology dependent quantities like threshold voltage and parasitic capacitances. This allows us to design efficient planar antennas, coupled resonator impedance matching networks and low-power rectifiers in standard CMOS technologies (0.5-mum and 0.18-mum) and accurately predict their performance. Experimental results from a prototype power extraction system that operates around 950 MHz and integrates these components together are presented. Our measured RF power-up threshold (in 0.18-mum, at 1 muW load) was 6 muWplusmn10%, closely matching the predicted value of 5.2 muW.

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35- $\mu{\hbox {m}}$ Technology

Abstract: A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

Abstract: We have successfully integrated a 2-stack 8times8 array 1D- lR (one diode-one resistor) structure with 0.5 mumtimes0.5 mum cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiOx/n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8times8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZOx diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3 V.

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

Abstract: This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.

An Energy-Efficient OOK Transceiver for Wireless Sensor Networks

Abstract: A 1-Mb/s 916.5-MHz on-off keying (OOK) transceiver for short-range wireless sensor networks has been designed in a 0.18-mum CMOS process. The receiver has an envelope detection based architecture with a highly scalable RF front-end. Untuned RF circuits are leveraged and optimized in the receiver to achieve superior energy efficiency compared to tuned RF circuits. The receiver power consumption scales from 0.5 mW to 2.6 mW, with an associated sensitivity of -37 dBm to -65 dBm at a BER of 10 -3. The transmitter consumes 3.8 mW to 9.1 mW with output power from -11.4 dBm to -2.2 dBm. The receiver achieves a startup time of 2.5 mus, allowing for efficient duty cycling

Smart CMOS Image Sensors and Applications

Abstract: Introduction A general overview Brief history of CMOS image sensors Brief history of smart CMOS image sensors Organization of the book Fundamentals of CMOS Image Sensors Introduction Fundamental of photo detection Photo detectors for smart CMOS image sensors Accumulation mode in PD Basic pixel structures Sensor peripherals Basic sensor characteristics Color Pixel sharing Comparison between pixel architecture Comparison with CCDs Smart Functions and Materials Introduction Pixel structure Analog operation Pulse modulation Digital processing Materials other than Silicon Structures other than standard CMOS technologies Smart Imaging Introduction Low light imaging High speed Wide dynamic range Demodulation 3D range finder Target tracking Dedicated arrangement of pixel and optics Applications Introduction Information and communication applications Biotechnology applications Medical applications Appendix A: Tables of Constants Appendix B: Illuminance Appendix C: Human Eye and CMOS Image Sensors Appendix D: Fundamental Characteristics of MOS Capacitor Appendix E: Fundamental Characteristics of MOSFET Appendix F: Optical Format and Resolution References Index

A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS

Abstract: A fully dynamic SAR ADC is proposed that uses passive charge-sharing and an asynchronous controller to achieve low power consumption. No active circuits are needed for high-speed operation and all static power is removed, offering power consumption proportional to sampling frequency from 50MS/s down to 0. The prototype implementation in 90nm digital CMOS achieves 7.8 ENOB, 49dB SNDR at 20MS/s consuming 290 muW. This results in a FOM of 65fJ/conversion-step.

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging

Abstract: Temperature, voltage, and current sensors monitor the operation of a TCP/IP offload accelerator engine fabricated in 90nm CMOS, and a control unit dynamically changes frequency, voltage, and body bias for optimum performance and energy efficiency. Fast response to droops and temperature changes is enabled by a multi-PLL clocking unit and on-chip body bias. Adaptive techniques are also used to compensate performance degradation due to device aging, reducing the aging guardband.

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers

Abstract: Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10-13 while consuming 133 mW from a 1.6-V supply.

Low-Frequency Noise in Advanced MOS Devices

Abstract: Low-Frequency Noise in Advanced CMOS Devices begins with an introduction to noise, describing the fundamental noise sources and basic circuit analysis. The characterization of low-frequency noise is discussed in detail and useful practical advice is given. The various theoretical and compact low-frequency (1/f) noise models in MOS transistors are treated extensively providing an in-depth understanding of the low-frequency noise mechanisms and the potential sources of the noise in MOS transistors. Advanced CMOS technology including nanometer scaled devices, strained Si, SiGe, SOI, high-k gate dielectrics, multiple gates and metal gates are discussed from a low-frequency noise point of view. Some of the most recent publications and conference presentations are included in order to give the very latest view on the topics. The book ends with an introduction to noise in analog/RF circuits and describes how the low-frequency noise can affect these circuits.

A Wireless Power Interface for Rechargeable Battery Operated Medical Implants

Abstract: This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm2 and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.

A Low-Dropout Regulator for SoC With $Q$ -Reduction

Abstract: A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.