Showing papers on "CMOS published in 2008"

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks

Abstract: An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

Abstract: This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply.

Analog design essentials

Abstract: Comparison of MOST and Bipolar transistor models.- Amplifiers, Source followers & Cascodes.- Differential Voltage and Current amplifiers.- Noise performance of elementary transistor stages.- Stability of Operational amplifiers.- Systematic Design of Operational Amplifiers.- Important opamp configurations.- Fully-differential amplifiers.- Design of Multistage Operational amplifiers.- Current-input Operational Amplifiers.- Rail-to-rail input and output amplifiers.- Class AB and driver amplifiers.- Feedback Voltage and Transconductance Amplifiers.- Feedback Transimpedance and Current Amplifiers.- Offset and CMRR: Random and systematic.- Bandgap and current reference circuits.- Switched-capacitor filters.- Distortion in elementary transistor circuits.- Continuous-time filters.- CMOS ADC and DAC principles.- Low-power Sigma-Delta AD converters.- Design of crystal oscillators.- Low-noise amplifiers.- Coupling effects in Mixed analog-digital ICs.

CMOS compatible nanoscale nonvolatile resistance switching memory.

Abstract: We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (103), long endurance (106), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

Abstract: Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power.

A low-noise self-calibrating dynamic comparator for high-speed ADCs

Abstract: This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Abstract: Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Abstract: An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

Abstract: An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

Characterization of a Novel Nine-Transistor SRAM Cell

Abstract: Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. A new nine-transistor (9T) SRAM cell is proposed in this paper for simultaneously reducing leakage power and enhancing data stability. The proposed 9T SRAM cell completely isolates the data from the bit lines during a read operation. The read static-noise-margin of the proposed circuit is thereby enhanced by 2 X as compared to a conventional six-transistor (6T) SRAM cell. The idle 9T SRAM cells are placed into a super cutoff sleep mode, thereby reducing the leakage power consumption by 22.9% as compared to the standard 6T SRAM cells in a 65-nm CMOS technology. The leakage power reduction and read stability enhancement provided with the new circuit technique are also verified under process parameter variations.

Tradeoffs and Optimization in Analog CMOS Design

Abstract: The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.

45nm High-k + metal gate strain-enhanced transistors

Abstract: Two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper. The first feature is the integration of stress-enhancement techniques with the dual metal-gate + high-k transistors. The second feature is the extension of 193 nm dry lithography to the 45 nm technology node pitches. Use of these features has enabled industry-leading transistor performance and the first high volume 45 nm high-k + metal gate technology.

A 200 $\mu$ W Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems

Abstract: The growing interest toward the improvement of patients' quality of life and the use of medical signals in nonmedical applications such as entertainment, sports, and brain-computerinterfaces, requires the implementation of miniaturized and wireless biopotential acquisition systems with ultralow power dissipation. Therefore, this paper presents the implementation of a complete EEG acquisition ASIC tailored towards the needs of such applications, i.e., high-signal quality, low-power dissipation and ease of use. The presented ASIC includes eight readout front-end channels and an 11-bit analog-to-digital converter (ADC). The key to its high performance and low-power dissipation is the new AC coupled chopper stabilized instrumentation amplifier (ACCIA) implementation that uses a coarse-fine servoloop and reaches more than 120 dB CMRR, consumes only 2.3 muA , and achieves a noise-efficiency factor (NEF) of 4.3. Furthermore, the ease of use of the ASIC is realized by incorporating Calibration and Electrode Impedance Measurement Modes to the ASIC. Therefore, the former can be used to check the functionality of the ASIC, as well as, to calibrate the gain matching of the channels, where as the latter can be used to track the quality of the biopotential electrode. The ASIC is implemented in 0.5 mum CMOS process and the total current consumption is 66 muA from 3 V.

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

Abstract: This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 103 muA/mum), high Ion/Ioff ratio (~107), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.

A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna

Abstract: The uses of terahertz systems (300 GHz to 3 THz) in radars, remote sensing, advanced imaging, and bio-agent and chemical detection have been extensively studied. A compact and low-cost signal source is a key circuit block of terahertz systems. Traditionally, the circuits have been built using highly optimized III-V technologies. With the advances of CMOS, it has become realistic to consider terahertz circuits in CMOS. This paper reports a signal source operating near 410 GHz that is fabricated using low-leakage transistors in a 6 M 45 nm digital CMOS technology.

An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS

Abstract: Current trends in analog/mixed-signal design for battery-powered devices demand the adoption of cheap and power-efficient ADCs. SAR architectures have been recently demonstrated as able to achieve high power efficiency in the moderate-resolution/medium- bandwidth range in Craninckx, J. and Van der Plas, G., (2007). However, when the comparator determines in first instance the overall performance, as in most SAR ADCs, comparator thermal noise can limit the maximum achievable resolution. More than 1 and 2 ENOB reductions are observed in Craninckx, J. and Van der Plas, G., (2007) and Kuttner, F., (2002), respectively, because of thermal noise, and degradations could be even worse with scaled supply voltages and the extensive use of dynamic regenerative latches without pre-amplification. Unlike mismatch, random noise cannot be compensated by calibration and would finally demand a quadratic increase in power consumption unless alternative circuit techniques are devised.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

Abstract: The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

Abstract: An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.

Spin Wave Magnetic NanoFabric: A New Approach to Spin-Based Logic Circuitry

Abstract: We describe a magnetic nanofabric, which may provide a route to building reconfigurable spin-based logic circuits compatible with conventional electron-based devices. A distinctive feature of magnetic nanofabric is that a bit of information is encoded into the phase of the spin wave signal. This makes it possible to transmit information without the use of electric current and to utilize wave interference for useful logic functionality. The basic elements include voltage-to-spin-wave and wave-to-voltage converters, spin waveguides, a spin wave modulator, and a magnetoelectric cell. We illustrate the performance of the basic elements by experimental data and the results of numerical modeling. The combination of the basic elements leads us to construct magnetic circuits for NOT and majority logic gates. Logic gates such as AND, OR, NAND, and NOR are shown as the combination of NOT and reconfigurable majority gates. Examples of computational architectures such as a multibit processor and a cellular nonlinear network are described. The main advantage of the proposed magnetic nanofabric is its ability to realize logic gates with fewer devices than in CMOS-based circuits. Potentially, the area of the elementary reconfigurable majority gate can be scaled down to 0.1 mum2. We also discuss the disadvantages and limitations of the magnetic nanofabric.

Why is CMOS scaling coming to an END

Abstract: The continued physical feature size scaling of complementary metal oxide semiconductor (CMOS) transistors is experiencing asperities due to several factors, and it is expected to reach its boundary at size of 22 nm technology by 2018 This paper discusses and analyzes the main challenges and limitations of CMOS scaling, not only from physical and technological point of view, but also from material (eg, high-k vs low-k) and economical point of view as well The paper also addresses alternative non-CMOS devices (ie, nanodevices) that are potentially able to solve the CMOS problems and limitations

Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS

Abstract: The emerging concept of multistandard radios calls for low-noise amplifier (LNA) solutions able to comply with their needs. Meanwhile, the increasing cost of scaled CMOS pushes towards low-area solutions in standard, digital CMOS. Feedback LNAs are able to meet both demands. This paper is devoted to the design of low-area active-feedback LNAs. We discuss the design of wideband, narrowband and multiband implementations. We demonstrate that competitive RF performance is achievable thanks to CMOS downscaling, pleasing many applications because of their low cost (digital CMOS) and low area (bondpad size).

Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18- $\mu$ m Technology

Abstract: Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 018-mum CMOS technology The APDs are theoretically analyzed, measured, and the results are interpreted Excellent breakdown performance is measured for the 10 and 20 m APDs at 102 V The APD system is compared to the previous implementations in standard CMOS Our APD has a 55% peak probability of detection of a photon at an excess bias of 2 V, and a 30 ns dead time, which is better than the previously reported results

A 0.9-V 60- $\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range

Abstract: A 0.9-V 60-muW delta-sigma modulator is designed using standard CMOS 0.13-mum technology. The modulator achieves 83-dB dynamic range in a signal bandwidth of 20 kHz with a sampling frequency of 2 MHz. The input-feedforward architecture is used to reduce the voltage swing of the integrators, which enables low-power amplifiers. By considering the characteristics of the modulator architecture, low-quiescent operational transconductance amplifiers are designed, which use positive feedback to increase dc gain. The designed modulator shows very high figure of merit among the state-of-the-art sub-l-V modulators.

A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

Abstract: A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transistors. In this work, an inductor connected at the gate of the cascode transistor and capacitive cross-coupling are strategically combined to reduce the noise and the nonlinearity influences of the cascode transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 mum CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and -2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

Abstract: We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

Abstract: A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Abstract: Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.

Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS

Abstract: With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65 nm and 45 nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65 nm to 45 nm. This decrease is expected to continue with further technology scaling as well. The results show that at nominal voltage, the Qcrit for a latch is just ~20% more than that of the bit cell in sub-65nm technology nodes. Further, as the voltage is scaled from 1 V to 0.4 V, Qcrit decreases by ~5X which substantially increases the probability of an upset if a particle strike happens. This work shows that in sub-65 nm technology nodes with aggressive voltage scaling, it is equally critical to solve the soft error problems in logic (latches, flip-flops) as it is in SRAMs.

The Blixer , a Wideband Balun-LNA-I/Q-Mixer Topology

Abstract: This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where capacitive loading is no problem. Thus a high RF bandwidth is achieved without using inductors for bandwidth extension. By using an I/Q mixer with 25% duty-cycle LO waveform the output IF currents have also 25% duty-cycle, causing 2 times smaller DC-voltage drop after IF filtering. This allows for a 2 times increase in the impedance level of the IF filter, rendering more voltage gain for the same supply headroom. The implemented balun-LNA-I/Q-mixer topology achieves > 18 dB conversion gain, a flat noise figure < 5.5 dB from 500 MHz to 7 GHz, IIP2 = +20 dBm and IIP3 = -3 dBm. The core circuit consumes only 16 mW from a 1.2 V supply voltage and occupies less than 0.01 mm2 in 65 nm CMOS.

A 90nm CMOS 60GHz Radio

Abstract: CMOS-based circuits operating at mm-wave frequencies have emerged in the past few years. This paper discusses the integration of a 60GHz CMOS single-chip transmitter and a single- chip receiver using a standard 90nm CMOS technology demonstrating a reliable solution for 60GHz single-chip radio. Proper transistor layout, complete and accurate modeling and optimized parasitic extraction method enabled the robust design of the wideband super-heterodyne architecture to support the entire 57- to-66GHz band. The analog radio front-end is controlled by a serial digital interface and has been co-designed and integrated together with a high-speed digital signal processor including analog-to-digital conversion, high speed PHY signal processing such as frequency-offset compensation, phase tracking, FIR and DFE, to support both advanced OFDM and SCBT modulation scheme. The resulting single-chip solution enables data throughputs exceeding 7Gb/s (QPSK) and 15Gb/s (16QAM) for a total DC power budget of below 200mW in TDD operation. In combination with a low-cost FR4-based packaging technology, it provides a high-performance cost-effective solution for a wide range of high volume consumer electronic applications.