Showing papers on "CMOS published in 2010"

Nanowire transistors without junctions

Abstract: All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

Abstract: A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting

Abstract: This paper presents a low power boost converter for thermoelectric energy harvesting that demonstrates an efficiency that is 15% higher than the state-of-the-art for voltage conversion ratios above 20. This is achieved by utilizing a technique allowing synchronous rectification in the discontinuous conduction mode. A low-power method for input voltage monitoring is presented. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. The converter, fabricated in a 0.13 ?m CMOS process, operates from input voltages ranging from 20 mV to 250 mV while supplying a regulated 1 V output. The converter consumes 1.6 (1.1) ?W of quiescent power, delivers up to 25 (175) ?W of output power, and is 46 (75)% efficient for a 20 mV and 100 mV input, respectively.

High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible Silicon-On-Insulator platform

Abstract: A new generation of Silicon-on-Insulator fiber-to-chip grating couplers which use a silicon overlay to enhance the directionality and thereby the coupling efficiency is presented. Devices are realized on a 200mm wafer in a CMOS pilot line. The fabricated fiber couplers show a coupling efficiency of −1.6dB and a 3dB bandwidth of 80nm.

A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology

Abstract: A fully-integrated FMCW radar system for automotive applications operating at 77 GHz has been proposed. Utilizing a fractional- synthesizer as the FMCW generator, the transmitter linearly modulates the carrier frequency across a range of 700 MHz. The receiver together with an external baseband processor detects the distance and relative speed by conducting an FFT-based algorithm. Millimeter-wave PA and LNA are incorporated on chip, providing sufficient gain, bandwidth, and sensitivity. Fabricated in 65-nm CMOS technology, this prototype provides a maximum detectable distance of 106 meters for a mid-size car while consuming 243 mW from a 1.2-V supply.

Ultralow-Power Design in Near-Threshold Region

Abstract: Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

Towards fabless silicon photonics

Abstract: Silicon photonic devices can be built using commercial CMOS chip fabrication facilities, or 'fabs'. However, nearly all research groups continue to design, build and test chips internally, rather than leveraging shared CMOS foundry infrastructure.

RF energy harvesting system and circuits for charging of mobile devices

Abstract: RF energy harvesting holds a promise able future for generating a small amount of electrical power to drive partial circuits in wirelessly communicating electronics devices. This paper presents the overview and progress achieved in RF energy harvesting field. A modified form of existing CMOS based voltage doubler circuit is presented to achieve 160% increase in output power over traditional circuits at 0 dBm input power. A schottky diode based RF energy harvesting circuit performance is also studied with practical and simulations results.

Device and Architecture Outlook for Beyond CMOS Switches

Abstract: Sooner or later, fundamental limitations destine complementary metal-oxide-semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale structures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these novel switches can complement the execution of specific algorithms or workloads by enabling quite unique architectures. Ultimately, exploiting these unusual responses will extend throughput in high-performance computing. Alternative tokens also require new transport mechanisms to replace the conventional chip wire interconnect schemes of charge-based computing. New intrinsic limits to scaling in post-CMOS technologies are likely to be bounded ultimately by thermodynamic entropy and Shannon noise.

High-mobility ambipolar transistors and high-gain inverters from a donor-acceptor copolymer semiconductor.

Abstract: Ambipolar organic field-effect transistors (OFETs), which are capable of both p- and n-channel operations, are gaining attention as an alternative approach to mimicking complementary metal-oxide semiconductor (CMOS) digital integrated circuits for achieving high-performance and cost-effective circuits in organic electronics. [1‐13] Low power dissipation and high performance are some of the major advantages of CMOS technology over non-complementary ones. [14] Power consumption is minimized in CMOS circuits because the component transistors are selectively turned on only when the circuit is switching, otherwise they are off at the steady state. The better performance of a CMOS circuit in terms of sharp switching and high noise immunity arises because every elemental transistor actively contributes to the function of the circuit. [14] Most efforts towards CMOS-like circuits in organic electronics have focused on utilizing distinct p- and n-type semiconductors. [1,15] However, the necessity of lateral patterning of semiconductors in CMOS circuits makes device fabrication on a common substrate a very complex process. Ambipolar OFETs represent an approach to high-performance CMOS-like circuits that minimize patterning and complex fabrication processes. [1] Ambipolar transistors are also of interest in fundamental studies of charge transport in organic semiconductors [1,6,16] as well as the development of efficient light-emitting transistors. [8,17‐21]

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Abstract: This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-μm 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 × 265 μm 2 .

An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection

Abstract: An output-capacitorless low-dropout regulator (LDO) with a direct voltage-spike detection circuit is presented in this paper. The proposed voltage-spike detection is based on capacitive coupling. The detection circuit makes use of the rapid transient voltage at the LDO output to increase the bias current momentarily. Hence, the transient response of the LDO is significantly enhanced due to the improvement of the slew rate at the gate of the power transistor. The proposed voltage-spike detection circuit is applied to an output-capacitorless LDO implemented in a standard 0.35-?m CMOS technology (where VTHN ? 0.5 V and VTHP ? -0.65 V). Experimental results show that the LDO consumes 19 ?A only. It regulates the output at 0.8 V from a 1-V supply, with dropout voltage of 200 mV at the maximum output current of 66.7 mA. The voltage spike and the recovery time of the LDO with the proposed voltage-spike detection circuit are reduced to about 70 mV and 3 ?s, respectively, whereas they are more than 420 mV and 30 ?s for the LDO without the proposed detection circuit.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply

Abstract: A 60-GHz band, three-stage pseudo-differential power amplifier (PA) is implemented with input and output baluns on-chip. Each stage consists of a neutralized common-source amplifier pair. Neutralization mitigates the intrinsic gate-drain feedback of each transistor for increased power gain and reverse isolation. Shielded transformers couple the gain stages and allow low supply voltage operation. Fabricated in a 65-nm bulk CMOS process, the measured small-signal gain of the 0.13 × 0.41 mm2 PA is 16 dB at 60 GHz with 3-dB bandwidth more than 8.5 GHz, while consuming 50 mW from a 1-V supply. Reverse isolation is better than 42 dB from 55 to 65 GHz. Maximum saturated output power is 11.5 dBm with a peak PAE of 15.2% measured at 62 GHz; from 58 to 65 GHz, the measured PAE is above 10%.

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

Abstract: A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-?m 2.5-V standard I/O FETs in a 0.13-?m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

Abstract: As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations, traditional MOSFET scaling theory prescribes reducing supply and threshold voltages in proportion to device dimensions, a practice that induces an exponential increase in subthreshold leakage. As a result, leakage power has become comparable to dynamic power in current-generation processes, and will soon exceed it in magnitude if voltages are scaled down any further. Beyond this inflection point, multicore processors will not be able to afford keeping more than a small fraction of all cores active at any given moment. Multicore scaling will soon hit a power wall. This paper presents resistive computation, a new technique that aims at avoiding the power wall by migrating most of the functionality of a modern microprocessor from CMOS to spin-torque transfer magnetoresistive RAM (STT-MRAM)---a CMOS-compatible, leakage-resistant, non-volatile resistive memory technology. By implementing much of the on-chip storage and combinational logic using leakage-resistant, scalable RAM blocks and lookup tables, and by carefully re-architecting the pipeline, an STT-MRAM based implementation of an eight-core Sun Niagara-like CMT processor reduces chip-wide power dissipation by 1.7× and leakage power by 2.1× at the 32nm technology node, while maintaining 93% of the system throughput of a CMOS-based design.

Electric current sensors: a review

Abstract: The review makes a brief overview of traditional methods of measurement of electric current and shows in more detail relatively new types of current sensors. These include Hall sensors with field concentrators, AMR current sensors, magneto-optical and superconducting current sensors. The influence of the magnetic core properties on the error of the current transformer shows why nanocrystalline materials are so advantageous for this application. Built-in CMOS current sensors are important tools for monitoring the health of integrated circuits. Of special industrial value are current clamps which can be installed without breaking the measured conductor. Parameters of current sensors are also discussed, including geometrical selectivity. This parameter specific for current sensors means the ability to suppress the influence of currents external to the sensor (including the position of the return conductor) and also suppress the influence on the position of the measured conductor with respect to the current.

Second-Harmonic Generation in Silicon Nitride Ring Resonators

Abstract: The emerging field of silicon photonics seeks to unify the high bandwidth of optical communications with CMOS microelectronic circuits. Many components have been demonstrated for on-chip optical communications, including those that utilize the nonlinear optical properties of silicon[1, 2], silicon dioxide[3, 4] and silicon nitride[5, 6]. Processes such as second harmonic generation, which are enabled by the second-order susceptibility, have not been developed since the bulk $\chi^{(2)}$ vanishes in these centrosymmetric CMOS materials. Generating the lowest-order nonlinearity would open the window to a new array of CMOS-compatible optical devices capable of nonlinear functionalities not achievable with the?$\chi^{(3)}$ response such as electro-optic modulation, sum frequency up-conversion, and difference frequency generation. Here we demonstrate second harmonic (SH) generation in CMOS compatible integrated silicon nitride (Si3N4) waveguides. The $\chi^{(2)}$ response is induced in the centrosymmetric material by using the nanoscale structure to break the bulk symmetry. We use a high quality factor Q ring resonator cavity to enhance the efficiency of the nonlinear optical process and detect SH output with milliwatt input powers.

CMOS wireless transceiver design

Abstract: Symbols, Conventions, Notations and Abbreviations. Preface. 1. Wireless Communications. 2. Transmitters and Receivers. 3. Transceivers in the Frequency Domain. 4. Performance of Transceivers. 5. High-Level Synthesis. 6. Building Blocks for CMOS Transceivers. 7. Realizing A CMOS Transceiver. 8. General Conclusions. Appendices. A-Process Information. Bibliography. Index.

Cognitive Radio Design Challenges and Techniques

Abstract: Cognitive radios are expected to communicate across two or three frequency decades by continually sensing the spectrum and identifying available channels. This paper describes the issues related to the design of wideband signal paths and the decades-wide synthesis of carrier frequencies. A new CMOS low-noise amplifier topology for the range of 50 MHz to 10 GHz is introduced that achieves a noise figure of 2.9 to 5.7 dB with a power dissipation of 22 mW. Several multi-decade carrier generation techniques are proposed and a CMOS prototype is presented that exhibits a phase noise of -94 to -120 dBc/Hz at 1-MHz offset while consuming 31 mW.

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS

Abstract: Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm2, and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 μA and 8 mA. Measurement results confirm the theoretical basis of the proposed design.

Spin-Transistor Electronics: An Overview and Outlook

Abstract: Spin transistors are a new concept device that unites an ordinary transistor with the useful functions of a spin (magnetoresistive) device. They are expected to be a building block for novel integrated circuits employing spin degrees of freedom. The interesting features of spin transistors are nonvolatile information storage and reconfigurable output characteristics: these are very useful and suitable functionalities for various new integrated circuit architectures that are inaccessible to ordinary transistor circuits. This article reviews the current status and outlook of spin transistors from the viewpoint of integrated circuit applications. The device structure, operating principle, performance, and features of various spin transistors are discussed. The fundamental and key phenomena/technologies for spin injection, transport, and manipulation in semiconductors and the integrated circuit applications of spin transistors to nonvolatile logic and reconfigurable logic are also described.

Electronic devices and systems, and methods for making and using the same

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

A Sub- $\mu$ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application

Abstract: An ultra-low power embedded CMOS temperature sensor based on serially connected subthreshold MOS operation is implemented in a 0.18 μm CMOS process for passive RFID food monitoring applications. Employing serially connected subthreshold MOS as sensing element enables reduced minimum supply voltage for further power reduction, which is of utmost importance in passive RFID applications. Both proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) signals can be obtained through proper transistor sizing. With the sensor core working under 0.5 V and digital interfacing under 1 V, the sensor dissipates a measured total power of 119 nW at 333 samples/s and achieves an inaccuracy of + 1/-0.8°C from - 10°C to 30°C after calibration. The sensor is embedded inside the fabricated passive UHF RFID tag. Measurement of the sensor performance at the system level is also carried out, illustrating proper sensing operation for passive RFID applications.

0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS

Abstract: Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

Abstract: This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The prototype IC is implemented in 65 nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07.

CMOS-integrated high-speed MSM germanium waveguide photodetector

Abstract: A compact waveguide-integrated Germanium-on-insulator (GOI) photodetector with 10 ± 2fF capacitance and operating at 40Gbps is demonstrated Monolithic integration of thin single-crystalline Ge into front-end CMOS stack was achieved by rapid melt growth during source-drain implant activation anneal

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic

Abstract: In this paper, the effect of process variations on delay is analyzed in depth for both static and dynamic CMOS logic styles. Analysis allows for gaining an insight into the delay dependence on fan-in, fan-out, and sizing in sub-100-nm technologies. Simple but reasonably accurate models are derived to capture the basic dependences. The effect of process variations in transistor stacks is analytically modeled and analyzed in detail. The impact of both interdie and intradie variations is evaluated and discussed. Interestingly, the input capacitance of static and dynamic logic is shown to be rather insensitive to variations. The delay variability was also shown to be a weak function of the input rise/fall time and load. Analysis shows that domino logic circuits suffer from a doubled variability as compared to the static CMOS logic style. The positive feedback associated with the keeper transistor is shown to be responsible for the variability increase, which, in turn, limits the speed performance. This adds to the well-known speed degradation due to the current contention associated with the keeper transistor. Monte Carlo simulations on a 90-nm technology, including layout parasitics, are performed to validate the results.