Showing papers on "CMOS published in 2018"

Integrated lithium niobate electro-optic modulators operating at CMOS-compatible voltages

Abstract: Electro-optic modulators translate high-speed electronic signals into the optical domain and are critical components in modern telecommunication networks1,2 and microwave-photonic systems3,4. They are also expected to be building blocks for emerging applications such as quantum photonics5,6 and non-reciprocal optics7,8. All of these applications require chip-scale electro-optic modulators that operate at voltages compatible with complementary metal–oxide–semiconductor (CMOS) technology, have ultra-high electro-optic bandwidths and feature very low optical losses. Integrated modulator platforms based on materials such as silicon, indium phosphide or polymers have not yet been able to meet these requirements simultaneously because of the intrinsic limitations of the materials used. On the other hand, lithium niobate electro-optic modulators, the workhorse of the optoelectronic industry for decades9, have been challenging to integrate on-chip because of difficulties in microstructuring lithium niobate. The current generation of lithium niobate modulators are bulky, expensive, limited in bandwidth and require high drive voltages, and thus are unable to reach the full potential of the material. Here we overcome these limitations and demonstrate monolithically integrated lithium niobate electro-optic modulators that feature a CMOS-compatible drive voltage, support data rates up to 210 gigabits per second and show an on-chip optical loss of less than 0.5 decibels. We achieve this by engineering the microwave and photonic circuits to achieve high electro-optical efficiencies, ultra-low optical losses and group-velocity matching simultaneously. Our scalable modulator devices could provide cost-effective, low-power and ultra-high-speed solutions for next-generation optical communication networks and microwave photonic systems. Furthermore, our approach could lead to large-scale ultra-low-loss photonic circuits that are reconfigurable on a picosecond timescale, enabling a wide range of quantum and classical applications5,10,11 including feed-forward photonic quantum computation. Chip-scale lithium niobate electro-optic modulators that rapidly convert electrical to optical signals and use CMOS-compatible voltages could prove useful in optical communication networks, microwave photonic systems and photonic computation.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Abstract: Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

The development of flexible integrated circuits based on thin-film transistors

Abstract: The use of thin-film transistors in liquid-crystal display applications was commercialized about 30 years ago. The key advantages of thin-film transistor technologies compared with traditional silicon complementary metal–oxide–semiconductor(CMOS) transistors are their ability to be manufactured on large substrates at low-cost per unit area and at low processing temperatures, which allows them to be directly integrated onto a variety of flexible substrates. Here, I discuss the potential of thin-film transistor technologies in the development of low-cost, flexible integrated circuits for applications beyond flat-panel displays, including the Internet of Things and lightweight wearable electronics. Focusing on the relatively mature thin-film transistor technologies that are available in semiconductor fabrication plants today, the different technologies are evaluated in terms of their potential circuit applications and the implications they will have in the design of integrated circuits, from basic logic gates to more complex digital and analogue systems. I also discuss microprocessors and non-silicon, near-field communication tags that can communicate with smartphones, and I propose the concept of a Moore’s law for flexible electronics. This Perspective discusses the potential of thin-film transistor technologies in the development of low-cost, flexible integrated circuits, evaluating the more mature technologies available today in terms of their potential circuit applications and the implications they will have in the design of integrated circuits.

A 28-GHz CMOS Direct Conversion Transceiver With Packaged $2 \times 4$ Antenna Array for 5G Cellular System

Abstract: This paper describes a 28-GHz CMOS direct conversion transceiver with packaged $2 \times 4$ patch antenna array for 5G communication. Beamforming antenna and reconfigurable transceiver architecture are used for high effective isotropic radiated power (EIRP). For low error vector magnitude (EVM), switchless matching transmitter (Tx)/receiver (Rx) to antenna and 28-GHz injection-locked local oscillator (LO) generator are employed. Test chip was fabricated in 28-nm RF CMOS process. Measurement results show Tx EIRPsat of 31.5 dBm ( $P_{\mathrm {sat}}$ of 10.5 dBm in one power amplifier (PA)), EIRPmax 24 dBm ( $P_{\mathrm {max}}$ of 2 dBm with backoff of 7.5 dB in one PA), Rx noise figure of 6.7 dB, and integrated LO phase noise of −38.7 dBc (0.67°). After IQ mismatch calibration, Tx LO leakage and image power are less than −35 dBc. Rx and Tx EVM show 2.2% (−33 dB) at medium RF power (Rx $P_{\mathrm {in}}$ of −60 dBm and Tx EIRP of 0 dBm) with well-fit beam control capability.

100 GHz Plasmonic Photodetector

Abstract: Photodetectors compatible with CMOS technology have shown great potential in implementing active silicon photonics circuits, yet current technologies are facing fundamental bandwidth limitations. Here, we propose and experimentally demonstrate for the first time a plasmonic photodetector achieving simultaneously record-high bandwidth beyond 100 GHz, an internal quantum efficiency of 36% and low footprint. High-speed data reception at 72 Gbit/s is demonstrated. Such superior performance is attributed to the subwavelength confinement of the optical energy in a photoconductive based plasmonic-germanium waveguide detector that enables shortest drift paths for photogenerated carriers and a very small resistance-capacitance product. In addition, the combination of plasmonic structures with absorbing semiconductors enables efficient and highest-speed photodetection. The proposed scheme may pave the way for a cost-efficient CMOS compatible and low temperature fabricated photodetector solution for photodetection b...

Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

Abstract: Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16- $\mu \text{m}$ and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact model based on MOS11 and PSP was developed. In addition to reproducing the device dc characteristics, the accuracy and validity of the compact models are demonstrated by comparing time- and frequency-domain simulations of complex circuits, such as a ring oscillator and a low-noise amplifier, with the measurements at 4 K.

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Abstract: Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, to a large extent, result from the well-known von-Neumann bottleneck . The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications such as artificial intelligence, machine learning, and cryptography. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable in-memory Boolean computations. In this paper, we present an augmented version of the conventional SRAM bit-cells, called the X-SRAM , with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations, including NAND, NOR, IMP (implication), XOR logic gates, with respect to different bit-cell topologies − the 8T cell and the 8+T Differential cell. In addition, we also present a novel ‘read-compute-store’ scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the proposed techniques.

Cryogenic MOS Transistor Model

Abstract: This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation.

Flexible CMOS integrated circuits based on carbon nanotubes with sub-10 ns stage delays

Abstract: High-performance logic circuits that are constructed on flexible or unconventional substrates are required for emerging applications such as real-time analytics. Carbon nanotube thin-film transistors (TFTs) are attractive for these applications because of their high mobility and low cost. However, flexible nanotube TFTs usually suffer from much lower performance than those built on rigid substrates, and the resulting flexible integrated circuits typically exhibit low-speed operation with logic gate delays of over 1 μs, which severely limits their practical application. Here we show that high-performance carbon nanotube TFTs and complementary circuits can be fabricated on flexible polyimide substrates using a high-yield, scalable process. Our flexible TFTs exhibit state-of-the-art performance with very high current densities (>17 μA μm−1), large current on/off ratios (>106), small subthreshold slopes (<200 mV dec−1), high field-effect mobilities (~50 cm2 V−1 s−1) and excellent flexibility. We also develop a reliable n-type doping process, which allows us to fabricate complementary logic gates and integrated circuits on flexible substrates. With our approach, we build flexible ring oscillators that have a stage delay of only 5.7 ns. High-performance carbon nanotube thin-film transistors and complementary circuits can be fabricated on flexible substrates, including ring oscillators that have a stage delay of only 5.7 ns.

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

Abstract: This letter presents a CMOS wideband variable gain LNA for 28-GHz 5G integrated phased-array transceivers preserving high third-order intercept point (OIP3) at all gain settings. The prototype LNA has three stages providing digitally controlled gain optimized for higher IIP3 at lower gain. The stages are coupled together using double-tuned transformers for maximum group delay flatness. Fabricated in a 40-nm CMOS process, it achieves 18–26 dB gain at 1-dB gain step with 12–14.5 dBm OIP3 and 3.3–4.3 dB noise figure, while consuming 21.5–31.4 mW across 26–33 GHz frequency range. The root-mean-square error of the gain steps is less than 0.38 dB.

High-Performance Back-Illuminated Three-Dimensional Stacked Single-Photon Avalanche Diode Implemented in 45-nm CMOS Technology

Abstract: We present a high-performance back-illuminated three-dimensional stacked single-photon avalanche diode (SPAD), which is implemented in 45-nm CMOS technology for the first time. The SPAD is based on a P+/Deep N-well junction with a circular shape, for which N-well is intentionally excluded to achieve a wide depletion region, thus enabling lower tunneling noise and better timing jitter as well as a higher photon detection efficiency and a wider spectrum. In order to prevent premature edge breakdown, a P-type guard ring is formed at the edge of the junction, and it is optimized to achieve a wider photon-sensitive area. In addition, metal-1 is used as a light reflector to improve the detection efficiency further in backside illumination. With the optimized 3-D stacked 45-nm CMOS technology for back-illuminated image sensors, the proposed SPAD achieves a dark count rate of 55.4 cps/μm2 and a photon detection probability of 31.8% at 600 nm and over 5% in the 420–920 nm wavelength range. The jitter is 107.7 ps full width at half-maximum with negligible exponential diffusion tail at 2.5 V excess bias voltage at room temperature. To the best of our knowledge, these are the best results ever reported for any back-illuminated 3-D stacked SPAD technologies.

The ambipolar transport behavior of WSe 2 transistors and its analogue circuits

Abstract: Tungsten diselenide (WSe2) has many excellent properties and provides superb potential in applications of valley-based electronics, spin-electronics, and optoelectronics. To facilitate the digital and analog application of WSe2 in CMOS, it is essential to understand the underlying ambipolar hole and electron transport behavior. Herein, the electric field screening of WSe2 with a thickness range of 1–40 layers is systemically studied by electrostatic force microscopy in combination with non-linear Thomas–Fermi theory to interpret the experimental results. The ambipolar transport behavior of 1–40 layers of WSe2 transistors is systematically investigated with varied temperature from 300 to 5 K. The thickness-dependent transport properties (carrier mobility and Schottky barrier) are discussed. Furthermore, the surface potential of WSe2 as a function of gate voltage is performed under Kelvin probe force microscopy to directly investigate its ambipolar behavior. The results show that the Fermi level will upshift by 100 meV when WSe2 transmits from an insulator to an n-type semiconductor and downshift by 340 meV when WSe2 transmits from an insulator to a p-type semiconductor. Finally, the ambipolar WSe2 transistor-based analog circuit exhibits phase-control by gate voltage in an analog inverter, which demonstrates practical application in 2D communication electronics. Transistors made from two-dimensional tungsten selenide (WSe2) crystals may simplify fabrication of electronic communication devices. Modern transistors amplify and manipulate current by applying electric fields to semiconductor films known as channels that are designed to transport either positive or negative charges. Mingdong Dong from Aarhus University in Denmark and colleagues have developed a new transistor that can move both types of charge. The team found that when individual flakes of WSe2 were stacked into a multi-layered channel structure, the dominant type of charge transported could be switched using an external electrode. A prototype amplifier constructed from two WSe2-based transistors showed this approach enabled fundamental control over analog signals, and could potentially be used in complex circuits that require fewer materials and smaller chip footprints than usual. Compared with unipolar transistors, ambipolar transistors, which can easily switch between n-type and p-type behavior by applying an electric field, are most promising candidates since they can effectively simplify circuit design and save the layout area in CMOS. In this study, we take a deep insight into the thickness dependent physical properties of WSe2, where the optical properties, electric field screening effect, and the ambipolar transport behavior are systematically studied. Furthermore, the investigation of ambipolar WSe2 transistors in analogue circuits exhibiting gate-controlled phase change directly explores its practical application in 2D communication electronics.

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

Abstract: A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is simple to implement and ensures that the pre-amplifier output nodes are only partially discharged to reduce the energy consumption. The comparator is analyzed and compared to its prior art in terms of energy consumption and input referred noise voltage. First-order equations are presented that show how to optimize the pre-amplifier for low noise and high gain. Both the dynamic bias comparator and the prior art are implemented on the same die and measurements show that the dynamic bias can reduce the average energy consumption by about a factor 2.5 for the same input-equivalent noise at an input common-mode level of half the supply voltage.

A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path

Abstract: This paper presents a millimeter-wave (mmW) frequency generation stage aimed at minimizing phase noise (PN) via waveform shaping and harmonic extraction while suppressing flicker noise upconversion via proper harmonic terminations. A 2nd-harmonic resonance is assisted by a proposed embedded decoupling capacitor inside a transformer for explicit common-mode current return path. Class-F operation with 3rd-harmonic boosting and extraction techniques allow maintaining high quality factor of a 10-GHz tank at the 30-GHz frequency generation. We further propose a comprehensive quantitative analysis method of flicker noise upconversion mechanism exploiting latest insights into the flicker noise mechanisms in nanoscale short-channel transistors, and it is numerically verified against foundry models. The proposed 27.3- to 31.2-GHz oscillator is implemented in TSMC 28-nm CMOS. It achieves PN of −106 dBc/Hz at 1-MHz offset and figure-of-merit (FoM) of −184 dBc/Hz at 27.3 GHz. Its flicker phase-noise ( $1/f^{3}$ ) corner of 120 kHz is an order-of-magnitude better than currently achievable at mmW.

Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

Abstract: This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteristics of this technology down to 4.2 K and to demonstrate the impact of cryogenic temperatures on the essential analog figures-of-merit. A new body-partitioning methodology is then introduced to obtain a set of analytical expressions for the electrostatic profile and the freeze-out layer thickness in field-effect transistors operating from deep-depletion to inversion. The proposed physics-based model relies on the drift-diffusion transport mechanism to obtain the drain current and subthreshold swing, and is validated with the experimental results. This model explains the degradation in subthreshold swing at deep-cryogenic temperatures by the temperature-dependent occupation of interface charge traps. This leads to a degradation of the theoretical limit of the subthreshold swing at deep-cryogenic temperatures.

High-Performance Carbon Nanotube Complementary Electronics and Integrated Sensor Systems on Ultrathin Plastic Foil.

Abstract: The longtime vacancy of high-performance complementary metal-oxide-semiconductor (CMOS) technology on plastics is a non-negligible obstacle to the applications of flexible electronics with advanced functions, such as continuous health monitoring with in situ signal processing and wireless communication capabilities, in which high speed, low power consumption, and complex functionality are desired for integrated circuits (ICs). Here, we report the implementation of carbon nanotube (CNT)-based high-performance CMOS technology and its application for signal processing in an integrated sensor system for human body monitoring on ultrathin plastic foil with a thickness of 2.5 μm. The performances of both the p- and n-type CNT field-effect transistors (FETs) are excellent and symmetric on plastic foil with a low operation voltage of 2 V: width-normalized transconductances (gm/W) as high as 4.69 μS/μm and 5.45 μS/μm, width-normalized on-state currents reaching 5.85 μA/μm and 6.05 μA/μm, and mobilities up to 80.26...

A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

Abstract: This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient ( $k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ( $P_{\mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ( $P_{\mathrm {1\,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz).

Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition

Abstract: Hierarchical temporal memory (HTM) is a machine learning algorithm inspired by the information processing mechanisms of the human neocortex and consists of a spatial pooler (SP) and temporal memory (TM). In this paper, we develop circuits and systems to achieve the optimized design of an HTM SP, an HTM TM, and a memristive analog pattern matcher for pattern recognition applications. The HTM SP realizes an optimized hardware design through the introduction of mean overlap calculations and by replacing the threshold determination in the inhibition stage with a weighted summation operator over the neighborhood of the pixel under consideration. HTM TM is based on discrete analog memristive memory arrays and a weight update procedure. The operation of the proposed system is demonstrated for a face recognition problem, using the standard AR, ORL, and Yale databases, and for speech recognition, using the TIMIT database, with achieved accuracies of 87.21% and approximately 90%, respectively, given an SNR of 10 dB. Visual data processing using binary HTM SP features requires less storage and processing memory than required by the traditional processing methods, with the area and power requirements for its implementation being 0.096 mm2 and 1756 mW, respectively. The design of the TM circuit for a single pixel requires 23.85 ${\mu}\text{m}^{2}$ of area and 442.26 ${\mu}\text{W}$ of power.

Microhotplates for metal oxide semiconductor gas sensor applications—towards the CMOS-MEMS monolithic approach

Abstract: The recent development of the Internet of Things (IoT) in healthcare and indoor air quality monitoring expands the market for miniaturized gas sensors. Metal oxide gas sensors based on microhotplates fabricated with micro-electro-mechanical system (MEMS) technology dominate the market due to their balance in performance and cost. Integrating sensors with signal conditioning circuits on a single chip can significantly reduce the noise and package size. However, the fabrication process of MEMS sensors must be compatible with the complementary metal oxide semiconductor (CMOS) circuits, which imposes restrictions on the materials and design. In this paper, the sensing mechanism, design and operation of these sensors are reviewed, with focuses on the approaches towards performance improvement and CMOS compatibility.

28 GHz Doherty Power Amplifier in CMOS SOI With 28% Back-Off PAE

Abstract: A single-stage, symmetric Doherty power amplifier (PA) in 45 nm CMOS silicon on insulator at 28 GHz is presented. The PA achieves a saturated output power of 22.4 dBm, a peak power added efficiency (PAE) of 40%, and a 6 dB back-off PAE of 28%. High efficiency is attained due to low combiner losses of 0.5 dB, obtained using a recently developed combiner synthesis technique. A compact modeling approach for parasitic-extracted PA transistors is presented, which considerably reduced simulation time. The PA is based on two-stack power devices and occupies overall chip area of only 0.63 mm2, including pads.

Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration

Abstract: Silicon co-integration offers compelling scale-up opportunities for quantum computing. In this framework, cryogenic temperature is required for the coherence of solid-state quantum devices. This paper reports the characterization of an nMOS quantum-dot dedicated structure below 100 mK. The device under test is built in thin silicon film fabricated with 28 nm high- $k$ metal gate ultra-thin body and ultra-thin buried oxide advanced CMOS technology. The MOS structure is functional with improved performances at cryogenic temperature. The results open new research avenues in CMOS co-integration for quantum computing applications within the FD-SOI platform.

Time-Resolved Measurement of Negative Capacitance

Abstract: To reduce the power consumption in scaled CMOS integrated circuits, transistors operating at low supply voltage with steep subthreshold swing (SS) are highly desirable. The negative capacitance (NC) effect in ferroelectric materials has emerged as a possible solution for achieving steep SS in transistors. In order to effectively leverage this effect in device applications, a proper understanding of its time-dependent nature is crucial. Here, we demonstrate that the NC effect occurs within a time window which is bounded by the switching time of ferroelectric domains at the faster time limit and screening charge compensation time of polarization at the slower time limit. We study this temporal dynamics of NC effect both by performing the transient measurements of metal–ferroelectric hafnium zirconium oxide–insulator–semiconductor capacitor connected in series with a load resistor and by characterizing NC field-effect transistors (NCFETs) at different time scales. Our experimental results provide deeper insight into the understanding of NC effect, reveal the time dependent switching nature of NCFETs, and pave way for the advancement of steep-slope transistors technology.

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

Abstract: This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an efficient on-chip foreground calibration algorithm to fix bit weight errors. Several other enabling techniques are also used, including signal independent reference using reservoir capacitors to improve speed and reduce area, plus LSB repeats and statistical residue measurement to improve efficiency. The prototype achieves 97.5-dB spurious-free dynamic range at 100-kHz input while operating at 16 MS/s and consumes 16.3 mW. It was fabricated in a 55-nm CMOS process and occupies 0.55 mm2.

A PUF scheme using competing oxide rupture with bit error rate approaching zero

Abstract: Security is critical to today's interconnected world, and hardware protection is equally important as security at the network and system levels. Silicon physically unclonable functions (PUFs) are increasingly used as a hardware root of trust and an entropy source for cryptography applications. In those applications, the reliability of PUF output is key to a successful implementation. Both weak and strong PUFs obtain output by amplifying analog signals from physical properties on IC blocks (e.g. propagation delay, ring oscillator, time-controlled oxide breakdown [1] or threshold voltage of SRAM transistors [2,3,4]). These physical measurements are by nature sensitive to environmental conditions, such as temperature, operating voltage, thermal/interface noise of transistors, process corners and aging. As a result, it is difficult to obtain a stable PUF output without taking additional stabilization and error-correction techniques, e.g. temporal majority voting (TMV), pre-burning on PUF bits for end-of-life (EOL) prediction and reliability screening, masking algorithms, as well as leveraging parity bits for an Error-Correcting-Code (ECC) [3,4]. This paper presents a PUF architecture fabricated in 55nm ultra-low-power (ULP) CMOS and 55nm embedded Flash. The scheme is able to produce reliable and uniformly random PUF output without the need for complex error correction or error bit testing.

A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS

Abstract: A fully integrated digitally controlled two-phase buck voltage regulator (VR) with on-die solenoid inductors with a planar magnetic core is demonstrated in 14-nm tri-gate CMOS for fine-grained power delivery/management domains of high power density in system-on-chips while enabling ultra-thin (z-height) packages. The VR achieves 1-A/mm2 power density for 400-mA load current with a measured peak efficiency of 84% at 100-MHz switching frequency including a digital PWM with >9 bits (8 ps) of resolution.

A 14.8 dBm 20.3 dB Power Amplifier for D-band Applications in 40 nm CMOS

Abstract: This paper presents a high output power, high gain, class-AB power amplifier (PA) in 40 nm CMOS technology for D-band applications. Two-way transformer-based power-combining is implemented in order to increase output power. The supply voltage of the designed PA is 1 V. The PA achieves a P SAT of 14.8 dBm, small-signal gain of 20.3 dB and maximum PAE of 8.9 % at 140 GHz.

Floating incremental/decremental flux-controlled memristor emulator circuit based on single VDTA

Abstract: In this paper, new analog emulator circuits of flux-controlled memristor based on current voltage differencing transconductance amplifier (VDTA) and passive elements are proposed. They emulate both types of memductance, incremental and decremental, solely by interchanging the VDTA output terminals controlled by a simple switch. It uses only one VDTA, two resistors, one capacitor and one multiplier emulating floating memductance. Compared to other designed emulator circuits, they consist of fewer CMOS transistors and have wider output ranges. Theoretical derivations and related results are validated using SPICE simulations. The effectiveness of the proposed memristor circuits is verified by experimental results using commercially available integrated circuits, showing close agreement with theoretical and simulation results and easily reproducible at a low cost. The simulation test results and use of 0.18 μm CMOS technology have shown that the maximum frequency is 2 MHz. The circuit has also been tested for non-volatility features.The application of the proposed floating memristor emulator in designing an FM-to-AM converter confirms the functionality of the proposed circuit.

A 200-ps-Response-Time Output-Capacitorless Low-Dropout Regulator With Unity-Gain Bandwidth >100 MHz in 130-nm CMOS

Abstract: An output-capacitorless low-dropout regulator (OCL-LDO) using enhanced multipath nested Miller compensation with embedded feedforward path for system-on-chip (SoC) applications is presented in this paper While state-of-the-art LDOs are restricted to low-frequency operation with a maximum unity-gain bandwidth (UGB) typically ranging from several hundred kilohertz to no higher than 10 MHz even in advanced technologies (65 nm or beyond), the prototype fabricated in a standard 130-nm CMOS process features over 100-MHz UGB for all loading conditions up to 25-mA output current while consuming a quiescent current of 112 μ A With this ultra-wide bandwidth, the proposed LDO achieves 200-ps response time for load transient with 300-ps edge time The extension of UGB also magnificently contributes to improvement of power-supply rejection (PSR), making it comparable to OCL-LDOs that use ripple-feedforward techniques to specifically boost PSR or LDOs with large off-chip decoupling capacitors, while enjoying much faster speed The chip area is 0008 mm2

A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS

Abstract: This brief presents a design procedure of a compact 33-GHz low-noise amplifier (LNA) for fifth generation (5G) applications realized in 28-nm LP CMOS. Based on the unique set of challenges presented by advanced nanoscale CMOS, the emphasis is put here on the optimization of design and layout techniques for active and passive components in the presence of rigorous metal density rules and other back-end-of-the-line challenges. All passive components are designed and optimized with full-wave electromagnetic simulations for a high quality factor. In addition, layout techniques help to miniaturize the total area as the suggested 5G frequency band of 33 GHz is not high enough to provide a sufficiently compact chip size. The resulting increase in the concentration of required metal fills furthermore makes this optimization more challenging. The fabricated LNA consists of two cascode stages with a total core area of $0.68{\times }0.34$ mm2. It exhibits 4.9-dB noise figure and 18.6-dB gain at 33 GHz while consuming only 9.7 mW from a 1.2-V power supply.