Showing papers on "CMOS published in 2019"

Scalable energy-efficient magnetoelectric spin-orbit logic.

Abstract: Since the early 1980s, most electronics have relied on the use of complementary metal–oxide–semiconductor (CMOS) transistors. However, the principles of CMOS operation, involving a switchable semiconductor conductance controlled by an insulating gate, have remained largely unchanged, even as transistors are miniaturized to sizes of 10 nanometres. We investigated what dimensionally scalable logic technology beyond CMOS could provide improvements in efficiency and performance for von Neumann architectures and enable growth in emerging computing such as artifical intelligence. Such a computing technology needs to allow progressive miniaturization, reduce switching energy, improve device interconnection and provide a complete logic and memory family. Here we propose a scalable spintronic logic device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear momentum) combined with magnetoelectric switching. The device uses advanced quantum materials, especially correlated oxides and topological states of matter, for collective switching and detection. We describe progress in magnetoelectric switching and spin–orbit detection of state, and show that in comparison with CMOS technology our device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced logic density (by a factor of 5). In addition, its non-volatility enables ultralow standby power, which is critical to modern computing. The properties of our device indicate that the proposed technology could enable the development of multi-generational computing. A scalable spintronic device operating via spin–orbit transduction and magnetoelectric switching and using advanced quantum materials shows non-volatility and improved performance and energy efficiency compared with CMOS devices.

CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

Abstract: Non-volatile computing-in-memory (nvCIM) could improve the energy efficiency of edge devices for artificial intelligence applications. The basic functionality of nvCIM has recently been demonstrated using small-capacity memristor crossbar arrays combined with peripheral readout circuits made from discrete components. However, the advantages of the approach in terms of energy efficiency and operating speeds, as well as its robustness against device variability and sneak currents, have yet to be demonstrated experimentally. Here, we report a fully integrated memristive nvCIM structure that offers high energy efficiency and low latency for Boolean logic and multiply-and-accumulation (MAC) operations. We fabricate a 1 Mb resistive random-access memory (ReRAM) nvCIM macro that integrates a one-transistor–one-resistor ReRAM array with control and readout circuits on the same chip using an established 65 nm foundry complementary metal–oxide–semiconductor (CMOS) process. The approach offers an access time of 4.9 ns for three-input Boolean logic operations, a MAC computing time of 14.8 ns and an energy efficiency of 16.95 tera operations per second per watt. Applied to a deep neural network using a split binary-input ternary-weighted model, the system can achieve an inference accuracy of 98.8% on the MNIST dataset. A 1 Mb non-volatile computing-in-memory system, which integrates a resistive memory array with control and readout circuits using an established 65 nm foundry CMOS process, can offer high energy efficiency and low latency for Boolean logic and multiply-and-accumulation operations.

Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K

Abstract: Implementation of an error-corrected quantum computer is believed to require a quantum processor with a million or more physical qubits, and, in order to run such a processor, a quantum control system of similar scale will be required. Such a controller will need to be integrated within the cryogenic system and in close proximity with the quantum processor in order to make such a system practical. Here, we present a prototype cryogenic CMOS quantum controller designed in a 28-nm bulk CMOS process and optimized to implement a 16-word (4-bit) XY gate instruction set for controlling transmon qubits. After introducing the transmon qubit, including a discussion of how it is controlled, design considerations are discussed, with an emphasis on error rates and scalability. The circuit design is then discussed. Cryogenic performance of the underlying technology is presented, and the results of several quantum control experiments carried out using the integrated controller are described. This article ends with a comparison to the state of the art and a discussion of further research to be carried out. It has been shown that the quantum control IC achieves promising performance while dissipating less than 2 mW of total ac and dc power and requiring a digital data stream of less than 500 Mb/s.

p-bits for probabilistic spin logic

Abstract: We introduce the concept of a probabilistic or p-bit, intermediate between the standard bits of digital electronics and the emerging q-bits of quantum computing. We show that low barrier magnets or LBMs provide a natural physical representation for p-bits and can be built either from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using LBMs as free layers can be combined with standard NMOS transistors to provide three-terminal building blocks for large scale probabilistic circuits that can be designed to perform useful functions. Interestingly, this three-terminal unit looks just like the 1T/MTJ device used in embedded magnetic random access memory technology, with only one difference: the use of an LBM for the MTJ free layer. We hope that the concept of p-bits and p-circuits will help open up new application spaces for this emerging technology. However, a p-bit need not involve an MTJ; any fluctuating resistor could be combined with a transistor to implement it, while completely digital implementations using conventional CMOS technology are also possible. The p-bit also provides a conceptual bridge between two active but disjoint fields of research, namely, stochastic machine learning and quantum computing. First, there are the applications that are based on the similarity of a p-bit to the binary stochastic neuron (BSN), a well-known concept in machine learning. Three-terminal p-bits could provide an efficient hardware accelerator for the BSN. Second, there are the applications that are based on the p-bit being like a poor man's q-bit. Initial demonstrations based on full SPICE simulations show that several optimization problems, including quantum annealing are amenable to p-bit implementations which can be scaled up at room temperature using existing technology.

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Abstract: Large-scale digital computing almost exclusively relies on the von Neumann architecture, which comprises separate units for storage and computations. The energy-expensive transfer of data from the memory units to the computing cores results in the well-known von Neumann bottleneck. Various approaches aimed toward bypassing the von Neumann bottleneck are being extensively explored in the literature. These include in-memory computing based on CMOS and beyond CMOS technologies, wherein by making modifications to the memory array, vector computations can be carried out as close to the memory units as possible. Interestingly, in-memory techniques based on CMOS technology are of special importance due to the ubiquitous presence of field-effect transistors and the resultant ease of large-scale manufacturing and commercialization. On the other hand, perhaps the most important computation required for applications such as machine learning, etc., comprises the dot-product operation. Emerging nonvolatile memristive technologies have been shown to be very efficient in computing analog dot products in an in situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bitwise Boolean computations. However, challenges with respect to large-scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive-based computing solutions. In this paper, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analoglike in-memory multibit dot-product engine (DPE). By applying appropriate analog voltages to the read ports of the 8T SRAM array and sensing the output current, an approximate analog–digital DPE can be implemented. We present two different configurations for enabling multibit dot-product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. We also demonstrate the robustness of the present proposal in presence of nonidealities such as the effect of line resistances and transistor threshold voltage variations. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read–write instructions and also as an on-demand analoglike dot-product accelerator.

Carbon nanotube digital electronics

Abstract: It is anticipated that the scaling of silicon complementary metal–oxide–semiconductor (CMOS) devices will end around 2020, but alternative technologies capable of maintaining advances in computing power and energy efficiency have not yet been established. Among various options, carbon-nanotube-based electronics has been shown to be one of the most promising candidates. A range of methods have been developed to prepare high-purity semiconducting carbon nanotubes suitable for use in integrated circuits, and 5 nm nanotube transistors with superior performance to that of silicon CMOS have been demonstrated. Here, we explore the potential of carbon nanotube digital electronics. We examine the development of nanotube-based CMOS field-effect transistors and the different nanotube material systems available to build integrated circuits. We also highlight the medium-scale integrated circuits created to date and consider the challenges that exist in delivering large-scale systems. This Perspective explores the potential of carbon nanotube electronics, examining the development of nanotube-based field-effect transistors and integrated circuits, and the challenges that exist in delivering large-scale systems.

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

Abstract: In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm 2 SRAM cells for Mobile SoC and High Performance Computing Applications

Abstract: A leading edge 5nm CMOS platform technology has been defined and optimized for mobile and HPC applications. This industry-leading 5nm technology features, for the first time, full-fledged EUV, and high mobility channel (HMC) finFETs with densest 0.021µm2 HD SRAM. This true 5nm CMOS platform technology is a full node scaling from our successful 7nm node [4] in offering ~1.84x logic density, 15% speed gain or 30% power reduction. The 5nm platform technology successfully passed qualification [3] with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks. Currently in risk production, this true 5nm platform technology is on schedule for high volume production in 1H 2020.

A CMOS-integrated quantum sensor based on nitrogen–vacancy centres

Abstract: The nitrogen–vacancy (NV) centre in diamond can be used as a solid-state quantum sensor with applications in magnetometry, electrometry, thermometry and chemical sensing. However, to deliver practical applications, existing NV-based sensing techniques, which are based on bulky and discrete instruments for spin control and detection, must be replaced by more compact designs. Here we show that NV-based quantum sensing can be integrated with complementary metal–oxide–semiconductor (CMOS) technology to create a compact and scalable platform. Using standard CMOS technology, we integrate the essential components for NV control and measurement—microwave generator, optical filter and photodetector—in a 200 μm × 200 μm footprint. With this platform we demonstrate quantum magnetometry with a sensitivity of 32.1 μT Hz−1/2 and simultaneous thermometry. A compact platform for quantum magnetometry and thermometry can be created by integrating nitrogen–vacancy-based quantum sensing with complementary metal–oxide–semiconductor (CMOS) technology.

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

Abstract: This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy and low power consumption is integrated with the transceiver. With the help of the proposed calibration, this paper is capable of boosting the data rate with higher order modulation scheme and wider channel-bonding bandwidth, which are demanded by IEEE 802.11ay. At the same time, it maintains the compatibility with the existing IEEE 802.11ad standard. This paper reports a two-channel-bonding data rate of 24.64 Gb/s in 128 quadrature amplitude modulation (QAM). The corresponding TX-to-RX error vector magnitude (EVM) is −26.1 dB. Furthermore, a four-channel-bonding data rate of 42.24 Gb/s in 64 QAM is realized with a single-element transceiver. The measured maximum data rate is 50.1 Gb/s in 64 QAM, which is the highest data rate achieved in the 60-GHz band. The power consumption is only 169 mW in the transmitting mode and 139 mW in the receiving mode.

Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits

Abstract: Among the beyond-complementary metal–oxide–semiconductor (CMOS) devices being explored, ferroelectric field-effect transistors (FeFETs) are considered as one of the most promising. FeFETs are being studied by all major semiconductor manufacturers, and experimentally, FeFETs are making rapid progress. FeFETs also stand out with the unique hysteretic $I_{\text {ds}}$ - $V_{\text {gs}}$ characteristic that allows a device to function as both a switch and a nonvolatile (NV) storage element. We exploit this FeFET property to build two categories of fine-grained logic-in-memory (LiM) circuits: 1) ternary content addressable memory (TCAM) which integrates efficient and compact logic/processing elements into various levels of memory hierarchy; 2) basic logic function units for constructing larger and more complex LiM circuits. Two writing schemes (with and without negative supply voltages respectively) for FeFETs are introduced in our LiM designs. The resulting designs are compared with existing LiM approaches based on CMOS, magnetic tunnel junctions (MTJs), resistive random access memories (ReRAMs), ferrorelectric tunnel junctions (FTJs), etc., that afford the same circuit-level functionality. Simulation results show that FeFET-based NV TCAMs offer lower area overhead than MTJ (79%) and CMOS (42% less) equivalents, as well as better search energy-delay products (EDPs) than TCAM designs based on MTJ ( $149\times $ ), ReRAM ( $1.7\times $ ), and CMOS ( $1.3\times $ ) in array evaluations. NV FeFET-based LiM basic circuit blocks are also more efficient than functional equivalents based on MTJs in terms of propagation delay ( $4.2\times $ ) and dynamic power ( $2.5\times $ ). A case study for an FeFET-based LiM accumulator further demonstrates that by employing FeFET as both a switch and an NV storage element, the FeFET-based accumulator can save area (36%) and power consumption (40%) when compared with a conventional CMOS accumulator with the same structure.

Cryogenic Characterization of 22-nm FDSOI CMOS Technology for Quantum Computing ICs

Abstract: An approach is proposed to realize large-scale, “high-temperature” and high-fidelity quantum computing integrated circuits based on single- and multiple-coupled quantum-dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in a commercial CMOS technology. Measurements of minimum-size 6 nm $\times20$ nm $\times80$ nm Si-channel n-MOSFETs (electron-spin qubit), SiGe-channel p-MOSFETs (hole-spin qubit), and double quantum-dot complementary qubits reveal strong quantum effects in the subthreshold region at 2 K, characteristic of resonant tunneling in a quantum dot. S-parameter measurements of a transimpedance amplifier (TIA) for spin readout show an improved performance from 300 K to 2 K. Finally, the qubit-with-TIA circuit has 50- $\Omega $ output impedance and 78-dB $\Omega $ transimpedance gain with a unity-gain bandwidth of 70 GHz and consumes 3.1 mW.

Silicon integrated circuit thermoelectric generators with a high specific power generation capacity

Abstract: Microelectronic thermoelectric generators (TEGs), which can recycle waste heat into electrical power, have applications ranging from the on-chip thermal management of integrated circuits to environmental energy sources for Internet-of-things sensors. However, the incompatibility of TEGs with silicon integrated circuit technology has prevented their broad adoption in microelectronics. Here, we report TEGs created using nanostructured silicon thermopiles fabricated on an industrial silicon complementary metal–oxide–semiconductor (CMOS) process line. These TEGs exhibit a high specific power generation capacity (up to 29 μW cm−2 K−2) near room temperature, which is competitive with typical (Bi,Sb)2(Se,Te)3-based TEGs. The high power capacity results from the ability of CMOS processing to fabricate a very high areal density of thermocouples with low packing fraction and to carefully control electrical and thermal impedances. TEG power was also found to increase significantly when thermocouple width was decreased, providing a path to further improvements. Unlike (Bi,Sb)2(Se,Te)3 TEGs, our silicon integrated circuit TEGs could be seamlessly integrated into large-scale silicon CMOS microelectronic circuits at very low marginal cost. Thermoelectric generators based on nanostructured silicon thermopiles, which are fabricated on an industrial silicon CMOS process line and are thus compatible with integrated circuit technology, exhibit a high specific power generation capacity of up to 29 μW cm−2 K−2 near room temperature.

Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing

Abstract: Metal–oxide memristive integrated technologies for analogue neuromorphic computing have undergone notable developments in the past decade, but are still not mature enough for very large-scale integration with complementary metal–oxide–semiconductor (CMOS) processes. Although non-volatile floating-gate synapse transistors are a more advanced technology embedded within CMOS processes, their performance as analogue resistive memories remains limited. Here, we report a low-power, two-terminal floating-gate transistor fabricated using standard single-poly technology in a commercial 180 nm CMOS process. Our device, which is integrated with a readout transistor, can operate in an energy-efficient subthreshold memristive mode. At the same time, it is linearized for small-signal changes with a two-orders-of-magnitude resistance dynamic range. Our device can be precisely tuned using optimized switching voltages and times, and can achieve 65 distinct resistive levels and ten-year analogue data retention. We experimentally demonstrate the feasibility of a selector-free integrated memristive array in basic neuromorphic applications, including spike-time-dependent plasticity, vector-matrix multiplication, associative memory and classification training. A floating-gate memristive device fabricated in a commercial 180 nm CMOS process can be integrated into a selector-free memristive array and used to demonstrate basic neuromorphic applications.

Tunnelling-based ternary metal–oxide–semiconductor technology

Abstract: The power density limits of complementary metal–oxide–semiconductor (CMOS) technology could be overcome by moving from a binary to a ternary logic system. However, ternary devices are typically based on multi-threshold voltage schemes, which make the development of power-scalable and mass-producible ternary device platforms challenging. Here we report a wafer-scale and energy-efficient ternary CMOS technology. Our approach is based on a single threshold voltage and relies on a third voltage state created using an off-state constant current that originates from quantum-mechanical band-to-band tunnelling. This constant current can be scaled down to a sub-picoampere level under a low applied voltage of 0.5 V. Analysis of a ternary CMOS inverter illustrates the variation tolerance of the third intermediate output voltage state, and its symmetric in–out voltage-transfer characteristics allow integrated circuits with ternary logic and memory latch-cell functions to be demonstrated. Quantum-mechanical band-to-band tunnelling can be used to create an energy-efficient ternary logic technology that can be fabricated on the wafer scale using complementary metal–oxide–semiconductor (CMOS) processes.

Nano-opto-electro-mechanical switches operated at CMOS-level voltages.

Abstract: Combining reprogrammable optical networks with complementary metal-oxide semiconductor (CMOS) electronics is expected to provide a platform for technological developments in on-chip integrated optoelectronics. We demonstrate how opto-electro-mechanical effects in micrometer-scale hybrid photonic-plasmonic structures enable light switching under CMOS voltages and low optical losses (0.1 decibel). Rapid (for example, tens of nanoseconds) switching is achieved by an electrostatic, nanometer-scale perturbation of a thin, and thus low-mass, gold membrane that forms an air-gap hybrid photonic-plasmonic waveguide. Confinement of the plasmonic portion of the light to the variable-height air gap yields a strong opto-electro-mechanical effect, while photonic confinement of the rest of the light minimizes optical losses. The demonstrated hybrid architecture provides a route to develop applications for CMOS-integrated, reprogrammable optical systems such as optical neural networks for deep learning.

High-Throughput In-Memory Computing for Binary Deep Neural Networks with Monolithically Integrated RRAM and 90nm CMOS

Abstract: Deep learning hardware designs have been bottlenecked by conventional memories such as SRAM due to density, leakage and parallel computing challenges. Resistive devices can address the density and volatility issues, but have been limited by peripheral circuit integration. In this work, we demonstrate a scalable RRAM based in-memory computing design, termed XNOR-RRAM, which is fabricated in a 90nm CMOS technology with monolithic integration of RRAM devices between metal 1 and 2. We integrated a 128x64 RRAM array with CMOS peripheral circuits including row/column decoders and flash analog-to-digital converters (ADCs), which collectively become a core component for scalable RRAM-based in-memory computing towards large deep neural networks (DNNs). To maximize the parallelism of in-memory computing, we assert all 128 wordlines of the RRAM array simultaneously, perform analog computing along the bitlines, and digitize the bitline voltages using ADCs. The resistance distribution of low resistance states is tightened by write-verify scheme, and the ADC offset is calibrated. Prototype chip measurements show that the proposed design achieves high binary DNN accuracy of 98.5% for MNIST and 83.5% for CIFAR-10 datasets, respectively, with energy efficiency of 24 TOPS/W and 158 GOPS throughput. This represents 5.6X, 3.2X, 14.1X improvements in throughput, energy-delay product (EDP), and energy-delay-squared product (ED2P), respectively, compared to the state-of-the-art literature. The proposed XNOR-RRAM can enable intelligent functionalities for area-/energy-constrained edge computing devices.

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

Abstract: An early evaluation in terms of circuit design is essential in order to assess the feasibility and practicability aspects for emerging nanotechnologies. Reconfigurable nanotechnologies, such as silicon or germanium nanowire-based reconfigurable field-effect transistors, hold great promise as suitable primitives for enabling multiple functionalities per computational unit. However, contemporary CMOS circuit designs when applied directly with this emerging nanotechnology often result in suboptimal designs. For example, 31% and 71% larger area was obtained for our two exemplary designs. Hence, new approaches delivering tailored circuit designs are needed to truly tap the exciting feature set of these reconfigurable nanotechnologies. To this effect, we propose six functionally enhanced logic gates based on a reconfigurable nanowire technology and employ these logic gates in efficient circuit designs. We carry out a detailed comparative study for a reconfigurable multifunctional circuit, which shows better normalized circuit delay (20.14%), area (32.40%), and activity as the power metric (40%) while exhibiting similar functionality as compared with the CMOS reference design. We further propose a novel design for a 1-bit arithmetic logic unit-based on silicon nanowire reconfigurable FETs with the area, normalized circuit delay, and activity gains of 30%, 34%, and 36%, respectively, as compared with the contemporary CMOS version.

An Overview on the Second Generation Voltage Conveyor: Features, Design and Applications

Abstract: This brief presents a comprehensive study on a particular kind of conveyor called second-generation voltage conveyor (VCII) This building block is based on voltage conveying concept and is the dual of second generation current conveyor (CCII) It is shown that VCII is a very useful block in those configurations where CCII is limited, in terms of number of active blocks The results of this brief are helpful in choosing the best building block between CCII and VCII for each specific application Finally, for the first time, the CMOS implementation of VCII is also presented Simulation results with PSPICE using 035- ${\mu }\text{m}$ CMOS technology and supply voltage of ±165 V are given to approve the theory

Demonstration of BEOL-compatible ferroelectric Hf 0.5 Zr 0.5 O 2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications

Abstract: We demonstrate successful scalability of conventional 100μm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in the Back-End-Of-Line of 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40μC/cm2, endurance > 1011 cycles, switching speeds < 100ns, operating voltages < 4V, and data retention at 125°C. Presented results pave the way to < 10fJ/bit ultra-low power FeRAM for IoT applications.

An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers

Abstract: This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art.

Design of a loop-based random access memory based on the nanoscale quantum dot cellular automata

Abstract: The use of modern quantum dot cellular automata (QCA) on the nanoscale gives better results than complementary metal–oxide–semiconductor (CMOS) technology such as diminution power consumption, augmentation clock frequency and device density enhancement. Thereupon, it becomes a substantial technology for forming whole varieties of memory. Random access memory (RAM) is an essential element of any computer set where the operating system, application programs and data can be kept to rapidly admonition via the main processor. The RAM is extremely swifter to read from and write into other kinds of the computer storages. There are some QCA cells for memory structures, wherein their specifications are used to design more optimized structures than CMOS. The offered techniques in the previous studies lead to extend in the consumption area, and the circuit complexity. So, in this paper a new single-bit QCA-based RAM is proposed to overcome these weaknesses. Ultimately, 4 × 1 RAM is designed by applying the single-bit memory. The operational authenticity of the offered layouts is demonstrated utilizing QCADesigner. Also, the QCAPro tool is utilized for calculating the dissipated energy of the circuit. The obtained results have indicated that the offered design has a smaller number of cells, low complexity and low wire crossing. Also, the wasted area has optimized based on the one-level loop-based structure. The suggested D-latch has 24 QCA cells, and the wasted area is 0.02 μm2. Each memory structure in RAM layout has the wasted area of 0.06 μm2 and 55 QCA cells. Finally, the obtained results have confirmed that the proposed design improves cell numbers and wasted area.

Wafer-scalable, aligned carbon nanotube transistors operating at frequencies of over 100 GHz

Abstract: Wireless device technology operating in the millimetre-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Here we report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Our devices also offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power. Radio-frequency transistors made from aligned carbon nanotubes offer high linearity and an extrinsic cutoff frequency of over 100 GHz.

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Abstract: This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.

Opening Terahertz for Everyday Applications

Abstract: CMOS IC technology has become an affordable means for implementing capable systems operating at 300 GHz and above. CMOS circuits have been used to generate a signal up to 1.3 THz to detect both amplitude and phase of signals up to 1.2 THz, and to detect a signal amplitude up to ~10 THz. Additionally, a transmitter and a receiver operating up to ~300 GHz for electronic smelling using rotational spectroscopy, a 30-Gb/s 300-GHz QPSK transmitter for data communication with -6-dBm output power, and an 820 GHz imaging array fabricated in CMOS have been reported. These results, along with the CMOS circuit performance in the literature, and link analyses suggest that the electronics necessary for everyday life applications in the terahertz band can be affordably realized.

Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Abstract: Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration of monolithic integration. In this article, we propose circuit-/device-level optimizations to improve the energy and density of RRAM-based in-memory computing architectures. We report experimental results based on prototype chip design of 128 × 64 RRAM arrays and CMOS peripheral circuits, where RRAM devices are monolithically integrated in a commercial 90-nm CMOS technology. We demonstrate the CMOS peripheral circuit optimization using input-splitting scheme and investigate the implication of higher low resistance state on energy efficiency and robustness. Employing the proposed techniques, we demonstrate RRAM-based in-memory computing with up to 116.0 TOPS/W energy efficiency and 84.2% CIFAR-10 accuracy. Furthermore, we investigate four-level programming with single RRAM device, and report the system-level performance and DNN accuracy results using circuit-level benchmark simulator NeuroSim.

A High-Gain Inverter With Low-Temperature Poly-Si Oxide Thin-Film Transistors

Abstract: We report a complementary metal oxide semiconductor (CMOS) inverter made of p-type low-temperature poly-Si (LTPS) thin-film transistor (TFT) using blue laser annealing of amorphous Si and an n-type amorphous indium-gallium-zinc oxide (a-IGZO) TFT. The LTPS TFT exhibits a field-effect mobility, threshold voltage, and subthreshold swing of 81.76 cm2/Vs, −1.1 V, and 0.65 V/dec, respectively, and the a-IGZO TFT exhibits 13.52 cm2/Vs, 1.2 V and 0.25 V/dec, respectively. The CMOS inverter shows a full swing and a high gain of 114.28 V/V and a wide noise margin with rising and falling times of 1.44 and $3.52~\mu \text{s}$ , respectively.

A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer

Abstract: This paper proposes a fully integrated digital low-dropout (DLDO) regulator using a beat-frequency (BF) quantizer implemented in a 65-nm low power (LP) CMOS technology. A time-based approach, replacing the conventional voltage quantizer by a pair of voltage-controlled oscillator and a time quantizer, makes the design highly digital. A D-flip-flop is utilized as a BF generator, which is used as the sampling clock for the DLDO. The variable sampling frequency in the BF DLDO can achieve fast response, LP consumption, and excellent stability at the same time. In addition to that, the DLDO has a built-in active voltage positioning (AVP) for lower peak-to-peak voltage deviation during load step. The load capacitor is only 40 pF, and the total core area of the DLDO is 0.0374 mm2. A 50-mA step in load current produces a voltage droop of 108 mV, which is recovered in 1.24 $\mu \text{s}$ . It can operate for a wide input voltage from 0.6 to 1.2 V while generating a 0.4–1.1-V output for a maximum load current of 100 mA. The peak current efficiency is 99.5% and the figure of merit (FOM) is 1.38 ps.

22nm STT-MRAM for Reflow and Automotive Uses with High Yield, Reliability, and Magnetic Immunity and with Performance and Shielding Options

Abstract: We demonstrate high yield results from a solder-reflow-capable spin-transfer-torque MRAM embedded in 22nm ultra-low leakage (ULL) CMOS technology. The technology supports −40 to 150°C operation and data retention though six solder reflow cycles and far exceeding 10 years at 150°C. Ten year native magnetic field immunity is >1100 Oe at 25°C at the 1ppm bit upset level. A shield-in-package solution demonstrates <1ppm bit upset rates from a disc magnet providing 3.5 kOe disturb field exposure for ~80 hours at 25°C. Trading off reflow capability, using smaller CD magnetic tunnel junctions, higher performance is achieved, for example read signal development times of 6ns at 125°C and average write pulse times slightly over 30ns at −40°C in a 20Mb design.