Showing papers on "CMOS published in 2021"

Silicon electro-optic micro-modulator fabricated in standard CMOS technology as components for all silicon monolithic integrated optoelectronic systems *

Abstract: In this paper, optoelectronic characteristics and related switching behavior of one monolithically integrated silicon light-emitting device (LED) with an interesting wavelength range of 400–900 nm are studied. Through the comparison of two types of geometry, Si avalanche-based LED and Si field-effect LED (Si FE LED), in the same device, we establish the dimensional dependence of the switching speed of the LED. Almost-linear modulation curve implies lower distortion is shown for the Si FE LED with light emission enhancement, and technology computer aided design (TCAD) simulations are in line with the experimental results. Our findings indicate that ON–OFF keying up to GHz frequencies should be feasible with such diodes. Potential applications should include Si FE LED integrated into the micro-photonic systems.

The performance limits of hexagonal boron nitride as an insulator for scaled CMOS devices based on two-dimensional materials

Abstract: Complementary metal–oxide–semiconductor (CMOS) logic circuits at their ultimate scaling limits place extreme demands on the properties of all materials involved. The requirements for semiconductors are well explored and could possibly be satisfied by a number of layered two-dimensional (2D) materials, such as transition metal dichalcogenides or black phosphorus. The requirements for gate insulators are arguably even more challenging. At present, hexagonal boron nitride (hBN) is the most common 2D insulator and is widely considered to be the most promising gate insulator in 2D material-based transistors. Here we assess the material parameters and performance limits of hBN. We compare experimental and theoretical tunnel currents through ultrathin layers (equivalent oxide thickness of less than 1 nm) of hBN and other 2D gate insulators, including the ideal case of defect-free hBN. Though its properties make hBN a candidate for many applications in 2D nanoelectronics, excessive leakage currents lead us to conclude that hBN is unlikely to be suitable for use as a gate insulator in ultrascaled CMOS devices. This Perspective assesses the performance limits of hexagonal boron nitride when used as a gate insulator in complementary metal–oxide–semiconductor (CMOS) devices based on two-dimensional materials, concluding that due to excessive leakage currents, the material is unlikely to be suitable for use in ultrascaled CMOS devices.

All-in-one two-dimensional retinomorphic hardware device for motion detection and recognition.

Abstract: With the advent of the Internet of Things era, the detection and recognition of moving objects is becoming increasingly important1. The current motion detection and recognition (MDR) technology based on the complementary metal oxide semiconductor (CMOS) image sensors (CIS) platform contains redundant sensing, transmission conversion, processing and memory modules, rendering the existing systems bulky and inefficient in comparison to the human retina. Until now, non-memory capable vision sensors have only been used for static targets, rather than MDR. Here, we present a retina-inspired two-dimensional (2D) heterostructure based retinomorphic hardware device with all-in-one perception, memory and computing capabilities for the detection and recognition of moving trolleys. The proposed 2D retinomorphic device senses an optical stimulus to generate progressively tuneable positive/negative photoresponses and memorizes it, combined with interframe differencing computations, to achieve 100% separation detection of moving trichromatic trolleys without ghosting. The detected motion images are fed into a conductance mapped neural network to achieve fast trolley recognition in as few as four training epochs at 10% noise level, outperforming previous results from similar customized datasets. The prototype demonstration of a 2D retinomorphic device with integrated perceptual memory and computation provides the possibility of building compact, efficient MDR hardware. A retina-inspired two-dimensional material based retinomorphic device exhibits all-in-one perception, memory and computing capabilities for motion detection and recognition.

Gallium nitride-based complementary logic integrated circuits

Abstract: Owing to its energy efficiency, silicon complementary metal–oxide–semiconductor (CMOS) technology is the current driving force of the integrated circuit industry. Silicon’s narrow bandgap has led to the advancement of wide-bandgap semiconductor materials, such as gallium nitride (GaN), being favoured in power electronics, radiofrequency power amplifiers and harsh environment applications. However, the development of GaN CMOS logic circuits has proved challenging because of the lack of a suitable strategy for integrating n-channel and p-channel field-effect transistors on a single substrate. Here we report the monolithic integration of enhancement-mode n-channel and p-channel GaN field-effect transistors and the fabrication of GaN-based complementary logic integrated circuits. We construct a family of elementary logic gates—including NOT, NAND, NOR and transmission gates—and show that the inverters exhibit rail-to-rail operation, suppressed static power dissipation, high thermal stability and large noise margins. We also demonstrate latch cells and ring oscillators comprising cascading logic inverters. Through the monolithic integration of enhancement-mode n-type and p-type gallium nitride field-effect transistors, complementary integrated circuits including latch circuits and ring oscillators can be created for use in high-power and high-frequency applications.

CMOS-based cryogenic control of silicon quantum circuits.

Abstract: The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer. A cryogenic CMOS control chip operating at 3 K is used to demonstrate coherent control and simple algorithms on silicon qubits operating at 20 mK.

All-Silicon Microdisplay Using Efficient Hot-Carrier Electroluminescence in Standard 0.18 μ m CMOS Technology

Abstract: All-CMOS monolithic microdisplay technologies have been attracting attention due to their direct integration of light-emitting pixel arrays and driving circuits on a single silicon substrate. Improvements to optical power efficiency have been a hot spot for all-silicon microdisplay technologies. MOS-like gate-control structure avalanche-mode light-emitting diodes (AMLEDs) that employ hot-carrier electroluminescence to produce light emission are used to enhance the optical power efficiency of pixel units. A semi-active matrix mode is used to reduce the power consumption of driver circuits. A $100\times 100$ pixel array with an all-CMOS monolithic microdisplay system is demonstrated using standard $0.18\mu \text{m}$ CMOS technology. The optical emission power and the breakdown voltage of the proposed AMLEDs are increased by 139.2% and reduced by more than 67%, respectively. The optical-power efficiency is $5.98\times 10 ^{{-7}}$ which is comparable to the best reported so far in all-CMOS monolithic microdisplay chip. With its significant optical-power efficiency, the proposed microdisplay technology has broad application prospects in near-to-eye display and head mounted displays (HMDs).

A cryogenic CMOS chip for generating control signals for multiple qubits

Abstract: Scaled-up quantum computers will require control interfaces capable of the manipulation and readout of large numbers of qubits, which usually operate at millikelvin temperatures. Advanced complementary metal–oxide–semiconductor (CMOS) technology is an attractive platform for delivering such interfaces. However, this approach is generally discounted due to its high power dissipation, which can lead to the heating of fragile qubits. Here we report a CMOS-based platform that can provide multiple electrical signals for the control of qubits at 100 mK. We demonstrate a chip that is configured by digital input signals at room temperature and uses on-chip circuit cells that are based on switched capacitors to generate static and dynamic voltages for the parallel control of qubits. We use our CMOS chip to bias a quantum dot device and to switch the conductance of a quantum dot via voltage pulses generated on the chip. Based on measurements from six cells, we determine the average power dissipation for generating control pulses of 100 mV to be 18 nW per cell. We estimate that a scaled-up system containing a thousand cells could be cooled by a commercially available dilution refrigerator. A platform based on complementary metal–oxide–semiconductor (CMOS) technology operating with qubits close to 100 mK can generate static and dynamic signals for the control of many qubits.

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Abstract: The development of small, energy-efficient artificial intelligence edge devices is limited in conventional computing architectures by the need to transfer data between the processor and memory. Non-volatile compute-in-memory (nvCIM) architectures have the potential to overcome such issues, but the development of high-bit-precision configurations required for dot-product operations remains challenging. In particular, input–output parallelism and cell-area limitations, as well as signal margin degradation, computing latency in multibit analogue readout operations and manufacturing challenges, still need to be addressed. Here we report a 2 Mb nvCIM macro (which combines memory cells and related peripheral circuitry) that is based on single-level cell resistive random-access memory devices and is fabricated in a 22 nm complementary metal–oxide–semiconductor foundry process. Compared with previous nvCIM schemes, our macro can perform multibit dot-product operations with increased input–output parallelism, reduced cell-array area, improved accuracy, and reduced computing latency and energy consumption. The macro can, in particular, achieve latencies between 9.2 and 18.3 ns, and energy efficiencies between 146.21 and 36.61 tera-operations per second per watt, for binary and multibit input–weight–output configurations, respectively. Commercial complementary metal–oxide–semiconductor and resistive random-access memory technologies can be used to create multibit compute-in-memory circuits capable of fast and energy-efficient inference for use in small artificial intelligence edge devices.

Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor Memory

Abstract: Recent advances in oxide ferroelectric (FE) materials have rejuvenated the field of low-power, nonvolatile memories and made FE memories a commercial reality. Despite these advances, progress on commercial FE-RAM based on lead zirconium titanate has stalled due to process challenges. The recent discovery of ferroelectricity in scandium-doped aluminum nitride (AlScN) presents new opportunities for direct memory integration with logic transistors due to the low temperature of AlScN deposition (approximately 350 °C), making it compatible with back end of the line integration on silicon logic. Here, we present a FE-FET device composed of an FE-AlScN dielectric layer integrated with a two-dimensional MoS2 channel. Our devices show an ON/OFF ratio of ∼106, concurrent with a normalized memory window of 0.3 V/nm. The devices also demonstrate stable memory states up to 104 cycles and state retention up to 105 s. Our results suggest that the FE-AlScN/2D combination is ideal for embedded memory and memory-based computing architectures.

A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control

Abstract: Microring modulators (MRMs) with CMOS electronics enable compact low power transmitter solutions for 400G Ethernet and co-packaged optical transceivers. In this article, we present a 3-D-integrated 112-Gb/s pulse amplitude modulation (PAM)-4 optical transmitter (OTX) using silicon photonic MRM, on-chip laser, and co-packaged 28-nm CMOS driver. The 3- $V_{\mathrm {pp}}$ driver includes a lookup table (LUT)-based PAM-4 nonlinear equalizer to address static and dynamic MRM nonlinearities. An integrated thermal control method that is insensitive to input power fluctuations is proposed to compensate for the temperature sensitivity of MRMs. PAM-4 measurement results of our OTX at 112 Gb/s show that transmitter dispersion eye closure quaternary (TDECQ) < 1.5 dB is achieved from 28 °C to 55 °C with 7.4-pJ/bit energy efficiency including on-chip laser.

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

Abstract: A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-based Gm/inverse-Gm-load cells. A distributed inductor peaking network and multi-phase clock calibration is implemented in the quarter-rate transmitter. The transceiver achieves <1E-8 pseudorandom binary sequence (PRBS)-31 PAM-4 bit error rate (BER) over a channel with 37.5-dB loss at 28 GHz while dissipating 602 mW per channel, excluding DSP.

High-Density Memristor-CMOS Ternary Logic Family

Abstract: This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems

Abstract: This article introduces a power-efficient and low-cost CMOS 28-GHz phased-array beamformer supporting fifth-generation (5G) dual-polarized multiple-in-multiple-out (MIMO) (DP-MIMO) operation. To improve the cross-polarization (cross-pol.) isolation degraded by the antennas and propagation, a power-efficient analog-assisted cross-pol. leakage cancellation technique is implemented. After the high-accuracy cancellation, more than 41.3-dB cross-pol. isolation is maintained along with the transmitter array to the receiver array. The element-beamformer in this work adopts the compact neutralized bi-directional architecture featuring a minimized manufacturing cost. The proposed beamformer achieves 22% per path TX-mode efficiency and a 4.9-dB RX-mode noise figure. The required on-chip area for the beamformer is only 0.48 mm2. In over-the-air measurement, a 64-element dual-polarized phased-array module achieves 52.2-dBm saturated effective isotropic radiated power (EIRP). The 5G standard-compliant OFDMA-mode modulated signals of up to 256-QAM could be supported by the 64-element modules. With the help of the cross-pol. leakage cancellation technique, the proposed array module realizes improved DP-MIMO EVMs even under severe polarization coupling and rotation conditions. The measured DP-MIMO EVMs are 3.4% in both 64-QAM and 256-QAM. The consumed power per beamformer path is 186 mW in the TX mode and 88 mW in the RX mode.

A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization

Abstract: This article presents frequency-modulated-continuous-wave (FMCW) radars developed for the detection of vital signs and gestures using two generations of 145-GHz transceivers (TRXs) integrated in 28-nm bulk CMOS. The performance and limitations of high-frequency radars are quantified with a system-level study, and the design and performance of individual circuit blocks are presented in detail. A 145-GHz center frequency and radar operation over an RF bandwidth of 10 GHz yield a displacement responsivity of 2 $\pi $ rad/mm and a windowed range resolution of 30 mm, respectively. Radar operation over a 0.1–7 m range is enabled by an effective-isotropic radiated power of 11.5 dBm and a noise figure of 8 dB. The ICs feature frequency multiplication by 9 in the transmit and receive paths, sub-arrayed dipole antennas, and neutralization of TX–RX leakage via delay control. A single TRX dissipates 500 mW from a 0.9-/1.8-V drive. The use of fast chirps (5–30- $\mu \text{s}$ ) mitigates the effect of 1/ $f$ -noise at the intermediate frequency (IF). Extensive characterization results showcase state-of-the-art performance of the TRXs, while the code-domain multiple-input and multiple-output (MIMO) radars ( $1 \times 4$ and $4 \times 4$ ) built with them demonstrate vital-sign and gesture detections.

μBrain: An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks.

Abstract: The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-located memory and processing capability that exploits event-based processing to reduce an always-on system's overall energy consumption (μW dynamic operation). The chip area in a 40 nm Complementary Metal Oxide Semiconductor (CMOS) digital technology is 2.82 mm2 including pads (without pads 1.42 mm2). This small area footprint enables μBrain integration in re-trainable sensor ICs to perform various signal processing tasks, such as data preprocessing, dimensionality reduction, feature selection, and application-specific inference. We present an instantiation of the μBrain architecture in a 40 nm CMOS digital chip and demonstrate its efficiency in a radar-based gesture classification with a power consumption of 70 μW and energy consumption of 340 nJ per classification. As a digital architecture, μBrain is fully synthesizable and lends to a fast development-to-deployment cycle in Application-Specific Integrated Circuits (ASIC). To the best of our knowledge, μBrain is the first tiny-scale digital, spike-based, fully parallel, non-Von-Neumann architecture (without schedules, clocks, nor state machines). For these reasons, μBrain is ultra-low-power and offers software-to-hardware fidelity. μBrain enables always-on neuromorphic computing in IoT sensor nodes that require running on battery power for years.

Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs

Abstract: Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply

Abstract: This brief proposes a sub-1V, voltage mode CMOS bandgap reference circuit. Conventionally, sub-1V references are obtained by converting PTAT and CTAT voltages to currents and summing them in the current domain. Such techniques have multiple operating points and cannot natively support applications that require PTAT currents in addition to a bandgap voltage. This brief presents a voltage mode reference circuit, which adds a PTAT voltage with a scaled version of a CTAT voltage all within the sub-1V domain. Compared to current mode bandgaps, summing in voltage domain enables reduction of one CTAT current mirror stage and a significant reduction in PTAT current mirror ratio resulting in a reduced number of error sources. In addition, this circuit also natively supports applications that require PTAT current. A novel, high-accuracy self-biasing technique has been adopted to minimize the systematic offset induced temperature coefficient. A prototype designed in 45nm TSMC CMOS technology for a nominal voltage of 500mV demonstrates 24.4ppm/°C temperature coefficient from −40°C to 125°C, 0.15% line regulation, and draws $7.2\mu \text{A}$ from a 1.05V supply.

A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications

Abstract: A cryogenic broadband low noise amplifier (LNA) for quantum applications based on a standard 40-nm CMOS technology is reported The LNA specifications are derived from the readout of semiconductor quantum bits at 42 K, whose quantum information signals are characterized as phase-modulated signals To achieve broadband input matching impedance and low noise figure, the gate-to-drain capacitance of the input transistor is exploited The goal is to involve a resistive and capacitive load into the input impedance match of a common-source stage with source inductive degeneration The capacitive load is created by an LC parallel tank whose resonant frequency is lower than the operating frequency The achieved non-constant in-band equivalent capacitance is proven to be beneficial to input impedance matching The resistive part of the load is provided by the transconductance of the cascode stage implicitly An inductor is added to the gate of the cascode transistor to suppress its noise, and a transformer-based resonator with two resonant frequencies serves as the load of the first stage, thus extending the operating bandwidth Design considerations for the cryogenic temperature operation of the LNA are proposed and analyzed The LNA achieves a measured gain ( $S_{21}$ ) of 35 ± 05 dB, return loss > 12 dB, and NF of 075–13 dB across the band (41–79 GHz), with 511-mW power consumption at room temperature, while it shows a measured gain of 42 ± 33 dB, and NF of 023–065 dB with 39-mW power consumption at 42 K between 46 and 8 GHz To the best of our knowledge, this is the first report of a cryogenic LNA based on a bulk CMOS process working above 4 GHz showing sub-1-dB NF both at room and cryogenic temperatures

A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

Abstract: Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal–oxide–semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power logic systems

VDCC-Based Memcapacitor/Meminductor Emulator and Its Application in Adaptive Learning Circuit

Abstract: In this paper, floating memcapacitor and meminductor emulators have been proposed using voltage differencing current conveyors, memristor and grounded capacitor. Meminductor emulator has been easily obtained from memcapacitor emulator and vice versa by interchanging the positions of memristor and capacitor. The proposed designs of memcapacitor and meminductor emulators are very simple as compared to most of the designs available in the literature. Proposed emulators perform satisfactorily for a wide range of frequency and also satisfy the non-volatility test. The performance of proposed memcapacitor and meminductor emulators has been verified by embedding the memristor emulator circuit and the SPICE model of memristor. The performance of proposed emulators is found to be satisfactory in both the cases. The proposed designs have been simulated by LTspice tool using 0.18 µm CMOS technology parameters. Adaptive learning circuits have also been designed using proposed memcapacitor and meminductor emulators that fully verify the workability of the design.

A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement

Abstract: This article introduces an SRAM-based physically unclonable function (PUF) that employs hybrid-mode operations in the enhancement–enhancement (EE) SRAM mode and CMOS SRAM mode to achieve both high native stability and low power. A data latching scheme based on the hybrid structure enables operations under low supply voltage ( ${V}_{\text {DD}}$ ). Furthermore, the proposed hybrid SRAM PUF is compatible with hot carrier injection (HCI) burn-in stabilization, which can reinforce PUF stability to ~100% without the requirements of bitcell redundancy, visible oxide damages, additional fabrication processes, helper data storage, or error-correcting code (ECC) circuits. The proposed PUF is fabricated in 130-nm standard CMOS, and the experimental results show that it achieves 0.29% native bit error rate (BER) at the nominal condition of 0.6 V/25 °C. The operating ${V}_{\text {DD}}$ scales down to 0.5 V, with a core energy efficiency of 2.07 fJ/b. After HCI burn-in, no bit errors are found across all ${V}_{\text {DD}}$ /temperature (VT) corners from 0.5 to 0.7 V and from −40 °C to 120 °C (5120 bits $\times $ 500 evaluations tested at each condition). Long-term reliability is verified by using an accelerated aging test equivalent to approximately 21 years of operation, where the reinforced PUF shows no bit errors even at the worst VT corner of 0.5 V/120 °C during the test. The introduced hybrid SRAM PUF also passes all applicable NIST SP 800–22 randomness tests. It has a compact bitcell with an area of 497 F2.

Cointegration of single-transistor neurons and synapses by nanoscale CMOS fabrication for highly scalable neuromorphic hardware

Abstract: Cointegration of multistate single-transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide semiconductor (CMOS) fabrication. The neurons and synapses were integrated on the same plane with the same process because they have the same structure of a metal-oxide semiconductor field-effect transistor with different functions such as homotype. By virtue of 100% CMOS compatibility, it was also realized to cointegrate the neurons and synapses with additional CMOS circuits. Such cointegration can enhance packing density, reduce chip cost, and simplify fabrication procedures. The multistate single-transistor neuron that can control neuronal inhibition and the firing threshold voltage was achieved for an energy-efficient and reliable neural network. Spatiotemporal neuronal functionalities are demonstrated with fabricated single-transistor neurons and synapses. Image processing for letter pattern recognition and face image recognition is performed using experimental-based neuromorphic simulation.

Aluminum scandium nitride-based metal-ferroelectric-metal diode memory devices with high on/off ratios

Abstract: In this Letter, we report a back-end-of-line (BEOL), complementary metal–oxide–semiconductor (CMOS)-compatible Al0.64Sc0.36N-based ferroelectric diode that shows polarization-dependent hysteresis in its leakage currents. Our device comprises a metal/insulator/ferroelectric/metal structure (Pt/native oxide/Al0.64Sc0.36N/Pt) that is compatible with BEOL temperatures (≤ 350 °C) grown on top of a 4-in. silicon wafer. The device shows self-selective behavior as a diode with > 105 rectification ratio (for 5 V). It can suppress sneak currents without the need for additional access transistors or selectors. Furthermore, given the polarization-dependent leakage, the diode current–voltage sweeps are analogous to that of a memristor with an on/off ratio of ∼ 50 000 between low and high resistance states. Our devices also exhibit stable programed resistance states during DC cycling and a retention time longer than 1000 s at 300 K. These results demonstrate that this system has significant potential as a future high-performance post-CMOS compatible nonvolatile memory technology.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

Abstract: This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

Reconfigurable photo-induced doping of two-dimensional van der Waals semiconductors using different photon energies

Abstract: Two-dimensional semiconductors have a range of electronic and optical properties that can be used in the development of advanced electronic devices. However, unlike conventional silicon semiconductors, simple doping methods to monolithically assemble n- and p-type channels on a single two-dimensional semiconductor are lacking, which makes the fabrication of integrated circuitry challenging. Here we report the reversible photo-induced doping of few-layer molybdenum ditelluride and tungsten diselenide, where the channel polarity can be reconfigured from n-type to p-type, and vice versa, with laser light at different frequencies. This reconfigurable doping is attributed to selective light–lattice interactions, such as the formation of tellurium self-interstitial defects under ultraviolet illumination and the incorporation of substitutional oxygen in tellurium and molybdenum vacancies under visible illumination. Using this approach, we create a complementary metal–oxide–semiconductor (CMOS) device on a single channel, where the circuit functions can be dynamically reset from a CMOS inverter to a CMOS switch using pulses of different light frequencies. Few-layer molybdenum ditelluride and tungsten diselenide field-effect transistors can be reversibly doped with different carrier types and concentrations using pulses of ultraviolet and visible light, allowing reconfigurable complementary metal–oxide–semiconductor circuits to be created.

Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting

Abstract: In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems.

2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter

Abstract: High selectivity becomes increasingly important with an increasing number of devices that compete in the congested 2.4-GHz industrial, scientific, and medical (ISM)-band. In addition, low power consumption is very important for Internet-of-Things (IoT) receivers. We propose a 2.4-GHz zero-intermediate frequency (IF) receiver front-end architecture that reduces power consumption by 2 $\times $ compared with state-of-the-art and improves selectivity by >20-dB without compromising on other receiver metrics. To achieve this, the entire receive chain is optimized. The low-noise transconductance amplifier (LNTA) is optimized to combine low noise with low power consumption. State-of-the-art sub-30-nm complementary metal–oxide–semiconductor (CMOS) processes have almost equal strength complementary field-effect transistors (FETs) that result in altered design tradeoffs. A Windmill 25%-duty cycle frequency divider architecture is proposed, which uses only a single NOR-gate buffer per phase to minimize power consumption and phase noise. The proposed divider requires half the power consumption and has 2 dB or more reduced phase noise when benchmarked against state-of-the-art designs. An analog finite impulse response (FIR) filter is implemented to provide very high receiver selectivity with ultralow power consumption. The receiver front end is fabricated in a 22-nm fully depleted silicon-on-insulator (FDSOI) technology and has an active area of 0.5 mm2. It consumes 370 $\mu \text{W}$ from a 700-mV supply voltage. This low power consumption is combined with a 5.5-dB noise figure. The receiver front end has −7.5-dBm input-referred third-order-intercept point (IIP3) and 1-dB gain compression for a −22-dBm blocker, both at maximum gain of 61 dB. From three channels offset onward, the adjacent channel rejection (ACR) is ≥63 dB for Bluetooth Low-Energy (BLE), BT5.0, and IEEE802.15.4.

A New Extremely Low Power Temperature Insensitive Electronically Tunable VCII-Based Grounded Capacitance Multiplier

Abstract: In this brief, a new circuit topology to realize an electronically tunable grounded capacitor multiplier with extremely low power consumption and low supply voltage requirement is investigated. The proposed circuit uses an electronically tunable second generation voltage conveyor (VCII) and a single floating capacitor. Owing to the translinear principle, current gain of VCII is varied through a control current and, as a result, the value of simulated capacitor is also varied. Favorably the obtained gain is temperature insensitive. Both of the required supply voltage and control currents are very low because all transistors are biased in subthreshold region: therefore, electronic tunability is achieved while the power consumption is kept at very low value. In addition, the circuit realization is very simple since only twelve transistors are required. Simulation results, performed at schematic level in 0.18 $\mu \text{m}$ CMOS technology and supply voltage of ±0.3V, are presented. It is shown that a multiplication factor from 1 to 100 is possible while the power consumption varies from 10 nW to 67 nW.

Analysis and Design of a CMOS Bidirectional Passive Vector-Modulated Phase Shifter

Abstract: This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the proposed passive VMPS can provide consistent phase-shift performance for bidirectional operation. The proof-of-concept VMPS is implemented in 40-nm CMOS technology and occupies a core chip area of 0.15 mm2. Measured results prove that it can provide consistent bidirectional 6-bit phase-shift operation, with accurate phase tuning (i.e., RMS phase error <24°) and low gain error (i.e., ±0.6 dB) over the whole 70–90 GHz band.