Topic
CMOS
About: CMOS is a research topic. Over the lifetime, 81371 publications have been published within this topic receiving 1189078 citations. The topic is also known as: complementary metal–oxide–semiconductor & complementary-symmetry metal–oxide–semiconductor.
Papers published on a yearly basis
Papers
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TL;DR: This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB, which adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths.
Abstract: This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB. This design adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer. These new techniques suppress signal dependent energy inside the delta-sigma loop, reduce internal channel coupling and power consumption. Manufactured in 0.35 mum double poly, three metal CMOS process, the single-die chip includes two analog modulators, on-chip bandgap reference circuit, decimation filter and serial interface circuits. The core die area is around 14.8 mm2. The ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Total power consumption is less than 330 mW.
29 citations
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TL;DR: In this paper, the impact of circuit placement on single-event transients (SETs) on heavy ion experiments on 65 nm bulk CMOS inverter chains has been investigated.
Abstract: Heavy ion experiments on 65 nm bulk CMOS inverter chains demonstrate the impact of circuit placement on single-event transients (SETs). Experimental data and simulations show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design due to the existence of pulse quenching.
29 citations
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TL;DR: In this paper, the authors investigated the fabrication of a micromachined microwave switch using the commercial 0.35 µm double polysilicon four metal complementary metal oxide semiconductor (CMOS) process and the post-process of only one maskless wet etching.
Abstract: In this study, we investigate the fabrication of a micromachined microwave switch using the commercial 0.35 µm double polysilicon four metal (DPFM) complementary metal oxide semiconductor (CMOS) process and the post-process of only one maskless wet etching. The post-process has merits of easy execution and low cost. The post-process uses an etchant (silox vapox III) to etch the silicon dioxide layer to release the suspended structures of the microwave switch. The microwave switch is a capacitive type that is actuated by an electrostatic force. The components of the microwave switch are coplanar waveguide (CPW) transmission lines, a suspended membrane and supported springs. Experimental results show that the driving voltage of the switch is about 17 V. The switch has an insertion loss of -2.5 dB at 50 GHz and an isolation of -15 dB at 50 GHz.
29 citations
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IBM1
TL;DR: A four-channel WDM silicon photonic transmitter with integrated lasers and modulators driven by low-power 32nm CMOS drivers, is demonstrated to operate at a data rate of 4×28Gb/s with BER<;10-12 and power consumption of 10.0pJ/bit.
Abstract: A four-channel WDM silicon photonic transmitter with integrated lasers and modulators driven by low-power 32nm CMOS drivers, is demonstrated to operate at a data rate of 4×28Gb/s with BER<10−12 and power consumption of 10.0pJ/bit.
29 citations
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TL;DR: In this article, analytical modeling equations describing the current transport in carbon nanotube field effect transistors (CNT-FETs) have been developed from physical electronics, which have strong dependence on the chiral vector and device geometries.
Abstract: In the present work, analytical modeling equations describing the current transport in carbon nanotube field effect transistors (CNT-FETs) have been developed from physical electronics, which have strong dependence on the chiral vector and device geometries. These model equations for the CNT-FETs have been compared with the available experimental data and then used to generate voltage transfer characteristics of basic logic devices based on complementary CNT-FETs. The voltage transfer characteristics exhibit characteristics similar to the voltage transfer characteristics of standard CMOS logic devices, with a sharp transition near the logic threshold voltage depending on the input conditions. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
29 citations