Common gate

About: Common gate is a research topic. Over the lifetime, 1095 publications have been published within this topic receiving 10397 citations.

A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation

Abstract: A broadband inductorless low-noise amplifier (LNA) design that utilizes simultaneous noise and distortion cancellation is presented. Concurrent cancellation of the intrinsic third-order distortion from individual stages is exhibited with the common-gate and common-source cascade. The LNA is then limited by the second-order interaction between the common source and common gate stages, which is common in all cascade amplifiers. Further removal of this third-order distortion is achieved by incorporating a second-order-distortion-free circuit technique in the common gate stage. Implemented in 0.13 m CMOS technology, this LNA achieved 16 dBm in both the 900 MHz and 2 GHz bands. Measurements demonstrate that the LNA has a minimum internal gain of 14.5 dB, noise figure of 2.6 dB from 800 MHz to 2.1GHz while drawing 11.6 mA from 1.5 V supply voltage.

A capacitor cross-coupled common-gate low-noise amplifier

Abstract: The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

Abstract: The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.

A Low-Power, Linearized, Ultra-Wideband LNA Design Technique

Abstract: This work proposes a practical linearization technique for high-frequency wideband applications using an active nonlinear resistor, and analyzes its performance with Volterra series. The linearization technique is applied to an ultra-wideband (UWB) cascode common gate Low Noise Amplifier (CG-LNA), and two additional reference designs are implemented to evaluate the linearization technique - a standard (without linearization) cascode CG-LNA and a single-transistor CG-LNA. The single-transistor CG-LNA achieves +6.5 to +9.5 dBm IIP3, 10 dB (max.) gain, and 2.9 dB (min.) NF over a 3-11 GHz bandwidth (BW); the LNA consumes 2.4 mW from a 1.3 V supply. The cascode linearized LNA achieves +11.7 to +14.1 dBm IIP3, 11.6 dB (max.) gain, and 3.6 dB (min.) NF over 1.5 to 8.1 GHz; the cascode LNA consumes 2.62 mW from a 1.3 V supply. Experimental results show that the linearization technique improves the cascode LNA's IIP3 by a factor of 3.5 to 9 dB over a 2.5-10 GHz frequency range.

A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-/spl mu/m CMOS

Abstract: A power amplifier for wireless applications has been implemented in a standard 0.25-/spl mu/m CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-/spl Omega/ load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices.