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Communication channel

About: Communication channel is a research topic. Over the lifetime, 137411 publications have been published within this topic receiving 1715077 citations. The topic is also known as: communication channel & communications channel.


Papers
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Journal ArticleDOI
TL;DR: This work considers a deep learning-based prediction and partially overlapping channel assignment to propose a novel intelligent channel assignment algorithm, which can intelligently avoid potential congestion and quickly assign suitable channels in SDN-IoT.
Abstract: Due to the fast increase of sensing data and quick response requirement in the Internet of Things (IoT) delivery network, the high speed transmission has emerged as an important issue. Assigning suitable channels in the wireless IoT delivery network is a basic guarantee of high speed transmission. However, the high dynamics of traffic load (TL) make the conventional fixed channel assignment algorithm ineffective. Recently, the software defined networking-based IoT (SDN-IoT) is proposed to improve the transmission quality. Besides this, the intelligent technique of deep learning is widely researched in high computational SDN. Hence, we first propose a novel deep learning-based TL prediction algorithm to forecast future TL and congestion in network. Then, a deep learning-based partially channel assignment algorithm is proposed to intelligently allocate channels to each link in the SDN-IoT network. Finally, we consider a deep learning-based prediction and partially overlapping channel assignment to propose a novel intelligent channel assignment algorithm, which can intelligently avoid potential congestion and quickly assign suitable channels in SDN-IoT. The simulation result demonstrates that our proposal significantly outperforms conventional channel assignment algorithms.

212 citations

Proceedings ArticleDOI
18 Apr 1991
TL;DR: In this paper, the feasibility of bounding the delay jitter for real-time channels in a packet-switched store-and-forward wide-area network with general topology was made.
Abstract: A study is made of the feasibility of bounding the delay jitter for real-time channels in a packet-switched store-and-forward wide-area network with general topology, extending the scheme proposed in previous papers. The authors prove the correctness of the solution, and study its effectiveness by means of simulations. The results show that the scheme is capable of providing a significant reduction in delay jitter, that there is no accumulation of jitter along the path of a channel, and that jitter control reduces the buffer space required in the network significantly. >

212 citations

Journal ArticleDOI
TL;DR: Mathematical methods of Markov chain theory are used to prove the inherent lnstablhty of the system and prove that the optimal pohcy which maximizes the maximum achievable throughput wtth a stable channel is found.
Abstract: The purpose of this paper is to analyze and optimize the behavior of the broadcast channel for a packet transmission operating in the slotted mode Mathematical methods of Markov chain theory are used to prove the inherent lnstablhty of the system If no control is apphed, the effective throughput of the system will tend to zero tf the population of user terminals ~s sufficiently large Two classes of control pohcles are examined, the first acts on admissions to the channel from active terminals, and the second modifies the retransmlss~on rate of packets In each case sufflc~ent conditions for channel stability are given. In the case of retransm~sslon controls it is shown that only pohcles which assure a rate of retransmlsslon from each blocked terminal of the form off = 1/n, where n is the total number of blocked terminals, will yield a stable channel It ts also proved that the optimal pohcy which maximizes the maximum achievable throughput wtth a stable channel IS of the formf = (1 - k)/n Simulations illustrating channel lnstabdlty and the effect of the opnmal control are prowded

211 citations

Book
12 May 1999
TL;DR: Fundamentals of Inductive Magnetic Head and Medium and Fundamental Limitations of Magnetic Recording are explained.
Abstract: Preface. Introduction. Fundamentals of Inductive Magnetic Head and Medium. Read Process in Magnetic Recording. Write Process in Magnetic Recording. Inductive Magnetic Process. Magnetoresistive Heads. Magnetic Recording Media. Channel Coding and Error Correction. Noises. Nonlinear Distortions. Peak Detection Channel. PRML Channel. Decision Feedback Channel. Off-Track Performance. Head-Disk Assembly Servo. Fundamental Limitations of Magnetic Recording. Alternative Information Storage Technologies.

211 citations

Journal ArticleDOI
01 Sep 2000
TL;DR: A novel adaptive Bayesian receiver for signal detection and decoding in fading channels with known channel statistics is developed, based on the sequential Monte Carlo methodology, and is ideally suited for high-speed parallel implementation using the very large scale integration (VLSI) systolic array technology.
Abstract: A novel adaptive Bayesian receiver for signal detection and decoding in fading channels with known channel statistics is developed; it is based on the sequential Monte Carlo methodology that has emerged in the field of statistics. The basic idea is to treat the transmitted signals as "missing data" and to sequentially impute multiple samples of them based on the observed signals. The imputed signal sequences, together with their importance weights, provide a way to approximate the Bayesian estimate of the transmitted signals and the channel states. Adaptive receiver algorithms for both uncoded and convolutionally coded systems are developed. The proposed techniques can easily handle the non-Gaussian ambient channel noise. It is shown through simulations that the proposed sequential Monte Carlo receivers achieve near-bound performance in fading channels for both uncoded and coded systems, without the use of any training/pilot symbols or decision feedback. Moreover, the proposed receiver structure exhibits massive parallelism and is ideally suited for high-speed parallel implementation using the very large scale integration (VLSI) systolic array technology.

211 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202270
20214,425
20206,535
20197,160
20187,052
20176,315