Comparator

About: Comparator is a research topic. Over the lifetime, 28095 publications have been published within this topic receiving 174862 citations.

Time interleaved converter arrays

Abstract: High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.

Digital waveform generation for electrosurgical generators

Abstract: An electrosurgical generator (10) has an improved design for generating output waveforms using a microprocessor (15). The waveforms are generated in the form of a serial digital output from the microprocessor (15). The serial digital output is transformed into an electrosurgical RF output in an amplifier stage. The improved design also includes a monitoring circuit to continuously monitor the serial digital output by time-averaging the output, and then comparing that value with a threshold. The electrosurgical generator (10) comprises a microprocessor (15), an algorithm in the microprocessor (15) capable of toggling an output port of the microprocessor (15), an output amplifier (16), an adjustable high voltage DC power supply (17), a patient circuit including an active electrode (12) and a return electrode (13). The electrosurgical generator (10) may further comprise a mode selector (20) for selecting one of a plurality of pulse patterns in the serial digital output, and a plurality of command sequences in the algorithm, where each command sequence is designed to produce one of the plurality of patterns. There may also be a tank damp circuit (22) for reducing the amplitude of voltage spikes in the electrosurgical output, and a pulse suppression circuit. The monitoring circuit comprises a low pass filter (19) and a comparator to verify operation of the waveform generator.

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

Abstract: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

Abstract: ―This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB. Differential input range is ± 1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR.

Design techniques for high-speed, high-resolution comparators

Abstract: Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >