Comparator

About: Comparator is a research topic. Over the lifetime, 28095 publications have been published within this topic receiving 174862 citations.

Automatic voice transcription device

Abstract: PROBLEM TO BE SOLVED: To perform power savings by comparing the integrated output of an analog voice signal with a prescribed reference value, discriminating a musical note and a rest based on the compared result and stopping an analog-digital conversion and a frequency analysis in the period of the rest SOLUTION: The output signal of a low-pass filter (an LPF) 107 is also inputted to an integration circuit 17 and is compared with a reference voltage VREF in a comparator 18 after the integration Then, in a CPU 113, the segmentation is performed in such a manner that when the output of the comparator 18 is a logical '1' (the integrated output in the circuit 17 is larger than the voltage VREF), the integrated output is made a musical note and when the output of the comparator 18 is a logical '0' (the integrated output in the circuit 17 is smaller than the voltage VREF), the integrated output is made to be a rest Moreover, power savings is performed by operating an A/D converter 106 and a DSP 105 when the output of the comparator 18 is the logical '1' and by stopping both circuits when the output of the comparator 18 is the logical '0' because the digital conversion and the frequency analysis are not needed to be performed at this period

An efficient power reduction technique for CMOS flash analog-to-digital converters

Abstract: An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm2 without I/O pads.

Continuous approximation type analog-digital converter and method thereof

Abstract: The invention provides a continuous approximation type analog-digital converter and a method thereof. Particularly, in each bit decision period of last several bit decision periods, a comparator is used for continuously conducting multiple comparison on a first potential and a second potential on an analog-digital converting circuit to obtain a plurality of comparison results, and then a continuous approximation type control circuit is used for generating corresponding carry-out bits according to the comparison results.

Analog circuit techniques utilizing BiCMOS technology

Abstract: The author focuses on analog design utilizing BiCMOS technology, illustrating the techniques used by circuit examples. An overview of the process and some device characteristics are given, and simple current cell, a latched comparator, and a sample/hold amplifier are described. These devices illustrate several useful analog functions. Several BiCMOS systems are also described, demonstrating the power and flexibility of BiCMOS technology. >

Direct current imbalance suppression circuit for wireless receiver

Abstract: The present invention discloses a direct current imbalance suppression circuit for a wireless receiver. The direct current imbalance suppression circuit for the wireless receiver comprises a variable gain module, a peak detection circuit, a digital control module and an offset voltage generation module. The peak detection circuit is configured to detect the output of the variable gain module in the wireless receiver, the output of the variable gain module is taken as the input signals of a comparator, and the output comparator is taken as the input signals of the digital control module; and the digital control module is configured to control the offset voltage generation module to generate an offset voltage and is connected with the input end of the variable gain module; and the offset voltage generation module consists of current source array, switch pair array with mutually inverted control signals and a resister RC and generates the adaptive offset voltage adaptive through controlling the value of current flowing the RC. The direct current imbalance suppression circuit for a wireless receiver is able to rapidly perform direct current imbalance calibration, effectively inhibit the direct current imbalance of the wireless receiver, overcome the problem that the calibration of direct current imbalance is only performed at the condition of the direct current signal work in the prior art, and realize the direct current imbalance inhibition in the condition of the alternate current signal work.