Comparator

About: Comparator is a research topic. Over the lifetime, 28095 publications have been published within this topic receiving 174862 citations.

A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration

Abstract: This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.

An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants

Abstract: This paper presents an efficiency-enhanced integrated full-wave CMOS rectifier for the transcutaneous power transmission in high-current biomedical implants. The comparator-controlled switches are developed to minimize the voltage drop along the conducting path while achieving the unidirectional current flow. The proposed unbalanced-biasing scheme also minimizes the reverse leakage current of the rectifier under different input amplitudes, thereby optimizing the rectifier power efficiency. Moreover, the proposed rectifier is able to self start and operates at low input amplitudes. Implemented in a standard 0.35 mum CMOS process with maximum threshold voltages of |Vthp| = 0.82 V and Vthn = 0.69 V, the rectifier can source a maximum output current of 20 mA and operate properly with inputs of different amplitudes and frequencies. With a 1.5 MHz input of 1.2 V amplitude, the proposed rectifier can achieve the peak voltage conversion ratio of 95% and the power efficiency of at least 82%.

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Abstract: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

An 8-bit 150-MHz CMOS A/D converter

Abstract: This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-/spl mu/m CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2/spl times/1.5 mm/sup 2/.

A Wireless Power Interface for Rechargeable Battery Operated Medical Implants

Abstract: This brief presents a highly integrated wirelessly powered battery charging circuit for miniature lithium (Li)-ion rechargeable batteries used in medical implant applications. An inductive link and integrated Schottky barrier rectifying diodes are used to extract the DC signal from a power carrier while providing low forward voltage drop for improved efficiency. The battery charger employs a new control loop that relaxes comparator resolution requirements, provides simultaneous operation of constant-current and constant-voltage loops, and eliminates the external current sense resistor from the charging path. The accuracy of the end-of-charge (EOC) detection is primarily determined by the voltage drop across matched resistors and current-sources and the offset voltage of the sense comparator. Experimental results in 0.6-mum 3M-2P CMOS technology indicate that plusmn1.3% (or plusmn20 muA) EOC accuracy can be obtained under worst case conditions for a comparator offset voltage of plusmn5 mV. The circuit measures roughly 1.74 mm2 and dissipates 8.4 mW in the charging phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW) for an efficiency of 73%.