About: Comparator applications is a(n) research topic. Over the lifetime, 2518 publication(s) have been published within this topic receiving 26639 citation(s).
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••12 Dec 2008
TL;DR: In this paper, a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique is presented, which does not require any amplifiers for the offset voltage cancellation and quiescent current.
Abstract: This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.
TL;DR: In this article, a comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented, which reduces the power consumption as well as the die area and increases the comparison speed.
Abstract: A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5- mu m n-well process with a die area of only 140*100 mu m/sup 2/. This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore +or-0.5 LSB resolution is equal to +or-4.9 mV). >
TL;DR: An analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived so that designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design.
Abstract: The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.
••01 Feb 2008
TL;DR: This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR because it uses a comparator, named time-domainComparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
Abstract: The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.
TL;DR: A comparator-based switched-capacitor (CBSC) design method for sampled-data systems utilizes topologies similar to traditional opamp-based methods but relies on the detection of the virtual ground using a comparator instead of forcing it with feedback.
Abstract: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW
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