Showing papers on "Comparator applications published in 1983"

CMOS current comparator circuit

Abstract: A CMOS current comparator circuit design is presented and its simulated performance described. A comparator circuit designed to detect the presence of, for example, 5 ?A realised in a standard polysilicon-gate CMOS process technology exhibits a simulated propagation delay of about 10 ns.

Sampling wave-form digitizer for dynamic testing of high speed data conversion components

Abstract: A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line. A modified T-filter system operatively coupled between the output of the latching comparator and the input of the operational amplifier allows control of the integrator slope and filters out signal spikes to allow the required accuracy for high speed measurements while a similar modified T-filter is provided in the feedback loop for preventing disturbances at the integrator output which could be caused by the sampling of the latching comparators and for simultaneously preventing ringing and for rounding off signal spikes in the feedback loop. Various adaptions of the broad sampling digitizer system are provided for measuring the settling time of a 12-bit digital-to-analog converter whose common mode output reading is one-half LSB accuracy in under 40 nanoseconds and a dynamic tester for very fast-acting sample and hold amplifier circuits which measure, by independently controlling the polarity of the square wave or test stimulus signal and the polarity of the hold select command, such circuit parameters as acquisition time, sample-to-hold settling time, sample-to-hold offset, glitch amplitude, amplitude delay, hold mode feedthrough rejection, risetime, slew rate, and the like.

Differential receiver with self-adaptive hysteresis

Abstract: A conventional regenerative comparator is modified by including a transistor switch in the feedback network to open circuit the feedback path according to the output state of the comparator, and by biasing the noninverting input of the comparator with a voltage directly proportional to the amplitude of the input signal, thereby providing variable threshold comparator with a hysteresis transfer characteristic with two distinct state change threshold levels that are a fixed ratio of the amplitude of the input signal.

Limiter with dynamic hysteresis

Abstract: Limiter circuit (13) with dynamic hysteresis for providing improved distortion immunity at the circuit output is response to an input signal. The limiter circuit (13) includes a positive (15) and negative peak detector (17). Two weighted averages are taken of the positive and negative peaks, preferably by means of a voltage divider network (18). The first input to a comparator circuit receives the input signal to the limiter circuit (13). Different voltages from the voltage divider network (18) are applied to the second input of the comparator circuit (21) so as to create a dynamic hysteresis effect in the comparator circuit (21). The different voltages are chosen in response to the output voltage from the comparator circuit (21) by means of an analog switch (19). The comparator circuit (21) includes a fixed hysteresis voltage for stabilizing the limiter circuit (13) at low level voltage input signals.

High speed comparator circuit with input-offset compensation function

Abstract: A comparator circuit which can operate at a high-speed and with a high comparison accuracy. The comparator circuit comprises a differential amplifier provided with an input offset voltage compensating circuit which stores the offset voltage and derives an offset-free output signal from the amplifier in response to first and second states of a first control signal and a latch circuit for storing the offset-free output signal in response to a second control signal having a higher frequency than the first control signal.

Focus servo system having object lens protection circuit for an optical disc player

Abstract: A focus servo system for an optical video disc player. A pair of signals generated by two pairs of photo-cells are supplied to an adder and a differential amplifier, an output signal of the adder is supplied to a first comparator and an output signal of the differential amplifier is supplied to a second comparator. When an output signal of the adder reaches a reference voltage of the first comparator, a focus servo pull-in range is detected. Thereafter, when an output signal of the differential amplifier reaches a reference voltage of the second comparator, a stable operation condition of the focus servo system is detected and a servo system loop is closed so that a malfunction is prevented.

Wide common mode range analog CMOS voltage comparator

Abstract: An improved analog CMOS comparator circuit is described. The improved circuit incorporates an additional CMOS device in the output stage of a conventional differential comparator. The additional device compensates for current imbalances which occur at relatively high common mode voltages thus allowing the improved comparator to operate over a wider range of common mode input voltages.

Transition detector circuit

Abstract: A noise-tolerant transition detector circuit (10) for detecting when an input signal rises above a first value (V2) and falls below a second value (V1) comprising: comparator means (12, 14) which produces a first output signal when the input signal rises above the first value and a second output signal when the input signal falls below the second value; and bistable means (20) which is set to its first stable state in response to the comparator means first output signal and which is set to its second stable state in response to the comparator means second output signal Noise may be further reduced by using further bistable means (26) and pulse-forming means (28, 32, 34, 36) may also be employed

Stabilized power source parallel operation system

Abstract: A stabilized power source parallel operation system in which the composite output current is maintained at a predetermined level even if a plurality of the parallel power sources are deenergized. Each power source has a voltage comparator, a current converter and a current comparator. The outputs of each of the voltage comparators are interconnected by an inter-power source voltage bus so that each of the current comparators compare the same current.

Latched comparator circuit

Abstract: A latched comparator circuit is disclosed in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof and which are supplied with a differential input. Also, there is disclosed a latched comparator circuit in which a voltage comparator circuit of a differential construction composing a part of the latched comparator circuit is substituted for by a plurality of differential amplifying circuits connected in parallel to the prior stage thereof that are supplied with a differential input for voltage comparison and in which a switching circuit is provided between the differential amplifying circuits and a latch circuit for electrically separating both of them upon latch operation.

Digital waveform shaping circuit

Abstract: The present invention provides a digital signal waveform shaping circuit for reproducing a digital signal recorded on a recording medium. The waveform shaping circuit includes at least one comparator for receiving an input signal and a delay circuit connected to the output of the comparator for delaying the comparator output by one-bit-cell. The input signal is compared with a threshold level associated with the output of the delay circuit.

Circuit for self-monitoring of a measurement converter for magnetic/inductive flow test sets

Abstract: For self-monitoring of a measurement converter (2) for magnetic/inductive flow test sets, two mutually independent comparator stages (6, 10) are provided in order to increase the accuracy. The one comparator stage (6) monitors two input amplifiers (4, 5) which are connected on the input side to a test-signal source (3). Two compensation amplifiers (8, 9) are connected in parallel to only one of the two input amplifiers (4) and are monitored by the other comparator stage (10).

Periodic signal detecting circuit including comparator circuit with variable threshold and varying time constant

Abstract: A periodic signal detecting circuit including a comparator compares a threshold voltage varying with a time constant and an engine speed signal from an electromagnetic pickup coil so as to generate an output. The time constant is varied in accordance with the switching operation of a diode switch which is turned on and off in accordance with the comparator output. When the switch is in off condition, the threshold voltage is varied with the time constant which is changed successively.

Signal delay generating circuit

Abstract: A signal generating circuit for generating a delayed signal in response to a pulsed timing signal with a delay time which is not substantially affected by variations in supply voltage or temperature. A voltage comparator receives a first input from a voltage division point of a voltage dividing circuit coupled across a voltage source. The other input terminal of the comparator is coupled to a RC circuit and to one terminal of a switch, the other terminal of which is connected to the voltage source. The position of the switch is determined by the output of the timing signal source. If desired, a flip-flop having its set input terminal coupled to a periodic pulse source and its reset input terminal coupled to the output of the comparator may have its complementary output used as the timing signal source to the switch, with the normal output of the flip-flop providing the delayed signal. Alternatively, a pair of comparators may be provided, each comparator comparing the RC circuit voltage to a different voltage from different points on the voltage dividing circuit, with the comparator outputs and the switching signal being combined in a logic circuit to obtain the delayed signal.

Bandwidth control circuit for a phase locked loop

Abstract: OF THE DISCLOSURE Control signals for switching the bandwidth of a filter in a phase locked loop are provided by comparator circuits having time delays at their inputs that vary as a function of the magnitude of changes in the outputs from a phase comparator. These variable time delays permit the comparator circuits to produce an output having a duration of the proper length in order to permit the filter to have a large bandwidth for a long enough time to permit the phase locked loop to become locked.

Comparator circuit having hysteresis voltage substantially independent of variation in power supply voltage

Abstract: A comparator circuit provided with a hysteresis characteristic comprises an amplifier comparing an input voltage with a reference voltage, a voltage-clamping circuit clamping the output voltage of the amplifier at a first stabilized voltage or at a second stabilized voltage in response to the comparison output of the amplifier, and a feedback circuit generating a first feedback voltage or a second feedback voltage as the reference voltage in response to the output voltage level of the amplifier, whereby the hysteresis voltage of the comparator circuit is substantially independent of the variation in a power supply voltage for actuating the comparator circuit.

Parallel analog-to-digital converter circuit

Abstract: A parallel analog-to-digital converter circuit comprises a plurality of level comparator circuits (10) and a plurality of detector means (52). The level comparator circuits (10) compare the level of one analog input signal with a plurality of reference levels. Any two or more level comparator circuits (10) which receive consecutive reference levels from one set. Each of the detector means (52) determines whether or not the output signals from the level comparator circuits (10) of one set are in a specified state. According to the number of sets of level comparator circuits (10) whose output signals are detected to be in the specified state, it is determined whether or not the analog-to-digital converter circuit functions correctly. The upper limit of the speed of analog-to-digital conversion can be determined according to this number of sets.

Actuator operating center detecting circuit and optical disk apparatus with the detecting circuit

Abstract: A detecting circuit for detecting an operating center of an actuator of an optical head includes a first comparator for comparing a tracking signal based on a reproduced signal coming from the optical head with a reference voltage approximate to zero voltage level, and a second comparator for comparing the tracking signal of which the DC component is removed with a second reference voltage approximate to zero voltage level. A level inversion of a binary output signal of the first comparator is detected at a level inverting point of a binary output signal of the second comparator. The operating center of the actuator is checked with the detection of the level inversion.

Vertical focus servo system for an optical disc player

Abstract: A pair of signals generated by two pairs of photo-cells (9a, 9c; 9b, 9d) is supplied to an adder (16) and a differential amplifier (14), an output signal of the adder is supplied to a first comparator (19) and an output signal of the differential amplifier is supplied to a second comparator (30). When an output signal of the adder reaches a reference voltage of the first comparator, a focus servo pull-in range is detected. Thereafter, when an output signal of the differential amplifier reaches a reference voltage of the second comparator, a stable operation condition of the focus servo system is detected and a servo system loop is closed so that a malfunction is prevented.

Multi-input zero offset comparator

Abstract: A multiple input window comparator for use in apparatus requiring sensing of a voltage window, such as power supplies and system monitors, including a first comparator having multiple input transistors, each of which receives a signal to be compared. The comparator characteristics for each input signal are balanced through the use of a current mirror circuit connected to each input transistor. A complementary second comparator circuit is provided which, in combination with the first comparator circuit, produces a signal indicating when one or more of the input signals exceeds the voltage boundaries (voltage window) defined by reference signals of the first and second comparator. The circuit topology of each of the first and second comparators produces a zero input voltage offset with respect to the respective reference voltage, such that the comparator output signal occurs substantially instantaneously and uniformly with the transition of the threshold voltage by one or more of the input signals. The comparator may be implemented with separate, discrete components or entirely on a single integrated circuit.

Switched capacitor oscillator formed by a damped resonator with saturable feedback

Abstract: A switched capacitor oscillator is constructed by providing a damped resonator network with a comparator as a nonlinear feedback element by connecting the input of the comparator to the output of a first operational amplifier of the resonator network and connecting the output of the comparator to the input of the resonator network. The comparator thus becomes a saturable positive feedback element for the resonator network. Also disclosed is a startup network for the oscillator and an input network which derives an input from a reference voltage in order to eliminate supply voltage noise and provide precision control of amplitude.

Pulse width modulation circuit and integration circuit of analog product using said modulation circuit

Abstract: A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above. The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

Device for recovery of clock frequency in digital transmission

Abstract: The device for recovery of the clock frequency of a digital signal comprises a rectifier, a filter having a very narrow bandwidth coupled to the first input of a phase comparator of analog type, a controlled oscillator, the output of which delivers the recovered clock signal and is coupled to the second input of the phase comparator via a low-pass filter. The output of the phase comparator is connected to the input of a loop filter, the output of which is connected to the control input of the oscillator.

Electronic voltage control device

Abstract: The invention relates generally to an electronic device for controlling the voltage supplied to a load, and in particular to a device having a transfer function of the first order. The technical problem to be solved concerned the provision of a device which, while retaining a characteristic of the first order, would enable control of the controlled signal frequency. The solution to the problem resides in providing a closed loop frequency control stage (9-11) operating in constant average current conditions and comprising a phase comparator (9), means operative to evaluate the sign of a hysteresis comparator (4') output voltage, and an adder (11).

Method for operating a fault detection circuit

Abstract: A fault protection circuit having circuit halves (H1, H2) which are operated in parallel and are duplicated for fault detection, and having a downstream-connected comparator circuit (V) whose two signal inputs are connected to the signal outputs of the two circuit halves (H1, H2). The signal output of the first circuit half (H1) is connected directly to an output connection (A), for the direct emission of its output signals (a1), to the supply lead to a downstream-connected load (A). In order to monitor the first circuit half (H1), the second circuit half (H2) passes its output signals (a2) directly to the comparator circuit (V) and not to the load. The received signal (e) is passed to both circuit halves (H1, H2) for processing. After processing, the received output signals (a1, a2) of both circuit halves (H1, H2) are compared with one another in the comparator circuits (V). The comparator circuit (V) first checks the equality or inequality of the compared output signals (a1, a2). Its comparator output (Al) does not emit a test result until the output signal (a1) of the first circuit half (H1) has started to be passed via the supply lead to the load (A). In the event of an inequality of the compared output signals (a1 NOTEQUAL a2), an alarm (A1) is triggered by the comparator circuit (V). In this case, the comparator output (Al) continuously emits the "no alarm" test result except when the comparator circuit ... Original abstract incomplete.

Triangle waveform generator

Abstract: A triangle waveform generator having a comparator which drives an integrator via a limiter is disclosed. At the output of the integrator, the desired triangular waveform voltage is present. The output of the integrator is connected to a first input of the comparator. The output of the comparator is fed back to its first input via a resistor. The output of the integrator is coupled via an integral action controller to a second input of the comparator. The integral action controller has a substantially longer time constant than the integrator. With this circuit, a triangular voltage is obtained, the parameters of which, namely, the slope and the positive and negative peak values, depend only on resistors and reference voltages which can be set within narrow tolerances.

Phase locked loop for high speed data

Abstract: A phase locked loop circuitry for high frequency digital electronic signals is provided which includes a loop filter having a substantially infinite bandwidth and wherein the sum of the frquency comparator and phase comparator output signals is actively integrated by an operational amplifier and summed with a flat, passively attenuated signal from the phase comparator. The PLL circuit includes a phase comparator having a full adder employing current mode logic so as to reduce parasitic capacitances and stray voltages, a frequency comparator having an additional, final flip-flop means out of the final combinatorial logic so as to retain the polarity of the final waveform transition, and an inhibiting circuit to disable the output of the final flip-flop of the frequency comparator when phase lock is attained by adding a complementary signal thereto.

Latching comparator with hysteresis

Abstract: A self latching comparator circuit has upper and lower input offset voltages associated therewith to establish hysteresis in response to a differential input signal. The comparator circuit comprises a differential amplifier adapted to receive a differential input signal and first and second parallel current mirror circuits for producing upper and lower input offset voltages when each are respectively activated. Antisaturation means are provided for preventing the current mirror circuits from saturating. An output circuit is also provided which does not load the differential output and therefore provides for a well controlled hysteresis.

Delayed monostable multivibrator

Abstract: A buffer comparator receives input pulses and produces buffer output signals that drive first and second output comparators arranged to operate as an amplitude-sensitive logic circuit that produces a high level output signal when and only when the internal driving signals have an amplitude between first and second threshold levels. In one embodiment, the output of the buffer comparator is applied directly to the non-inverting input terminal of the first logic circuit comparator and through a low resistance resistor to an R-C network and the inverting terminal of the second logic circuit comparator. The remaining input terminals on the logic comparators are connected to a multiple voltage divider that provides lower and upper threshold voltages to the respective comparators. An input pulse applied to the buffer comparator initiates an internal driving signal that charges the capacitor in the R-C network exponentially. While the voltage on the capacitor rises between the lower and upper threshold levels the logic comparators produce a high level output signal. When the input signal terminates, the low resistance resistor reverses the ordinary switching sequence of the logic comparators and prevents the formation of an output pulse at this time. A second embodiment of the invention dispenses with the means to reverse the ordinary switching sequence during discharge of the capacitor in the R-C network and thus provides a second positive-going output pulse at this time.

Gain control of audio-amplifying systems

Abstract: The gain of a conventional power amplifier AP is reduced, by means of a feedback circuit RT, as soon as the amplified signal overcomes a prefixed threshold value, determined by a peak detector C, near the saturation level of the same amplifier AP. An audio amplifier projected for a given maximum power can thus be used as if it was able to supply a higher power. When, at a signal peak, the threshold value (preferably fixed from 3 to 6dB below the saturation level of the amplifier) is exceeded the output of the comparator C acts on attenuator AT with a time constant determined by T so as to reduce the gain of the amplifier AP. The time constant circuit T enables the output signal of the comparator to charge a capacitor (C1, Figure 2) very quickly (nano sec) and as the output of the comparator C falls to zero the capacitor (C1) discharges slowly (e.g. 200 m sec) through resistor (R1). The variable attenuator AT may be of CMOS type.