Showing papers on "Comparator applications published in 1987"

Switching power supply VCO

Abstract: An inventive oscillator, inter alia, is disclosed which can be used to generate a frequency modulated control signal or a pulsewidth modulated control signal for application to a switching means in a switching power supply. The output voltage of a power supply is used to control the magnitude of a high bias voltage and a low bias voltage applied to a plus terminal of a voltage comparator, wherein when the output of the voltage comparator is high, the high bias voltage is applied to the plus terminal, and when the output of the voltage comparator is low, the low bias voltage is applied to the plus terminal. A capacitor, coupled to the output of the voltage comparator via a resistor, is coupled between the minus terminal of the voltage comparator and a ground so that when the output of the voltage comparator is high the capacitor charges. When the voltage across the capacitor exceeds that of the high bias voltage, the output of the voltage comparator goes low, discharging the capacitor until the voltage across the capacitor reaches the low bias voltage now applied to the plus terminal of the voltage comparator. The output of the voltage comparator then goes high, and the cycle repeats, thus generating a squarewave output corresponding to the output voltage of the power supply.

Voltage comparator circuit

Abstract: In the comparator circuit, the amplifier circuit (6) is comprised of an inverting amplifier section (21) having a high gain and a noninverting amplifier section (22) having a low output impedance. Therefore, the comparator circuit has a high input sensitivity. The comparator circuit also can operate at a high speed.

Direct current adjusting device

Abstract: A control circuit for adjusting current to a direct current motor that has a free wheeling diode connected in parallel with the armature winding includes a controllable switching element connected in series with the armature winding, a comparator that has a control voltage corresponding to a desired rotational speed of the motor applied to one input of the comparator and an integrating circuit connected to the other input of the comparator. An electronic switch is connected across the integrating circuit, and the output of the comparator controls the controllable switching element and the electronic switch.

FM receiver with improved adjacent-channel rejection

Abstract: An FM receiver having a phase-locked loop demodulator and a control voltage correction circuit for the local tuning oscillator. The correction circuit includes a comparator for comparing the output frequency of the phase-locked loop demodulator with the output signal from a reference oscillator, the output of the comparator being connected through an integrator to provide a control signal for the local oscillator as part of an automatic frequency control loop. The comparator output is also fed through an integrator to an adder connected between the demodulator output and the demodulator oscillator controlled input, for setting the demodulator oscillator at the center intermediate frequency when no carrier signal is being received.

Comparator with input offset current elimination

Abstract: A comparator circuit for use with other comparator circuits on a common resistive divider chain includes PNP input transistors operating in conjunction with a current mirror circuit, and input circuitry coupled between the divider chain and the PNP transistors for rendering the input bias currents to the PNP transistors equal when the comparator is in an unbalanced state. This circuitry is coupled to different potentials on the divider chain, and a current is derived from each of these potentials. These currents are essentially equal because they are each derived from the sum of half of the emitter currents of each input PNP transistor in the comparator. So, although the PNP transistor will have unequal currents when the inputs are not balanced, the input circuitry will balance these currents at all times.

Piezoelectric phase locked loop circuit

Abstract: A structural member having a piezoelectric transmitter film and a piezoelectric receiver film adhered thereto. The transmitter film produces a vibration upon activation by a voltage controlled oscillator which forms part of a phase-lock loop circuit. The vibrations of the structural member generate electric signals on the receiver film, which feed into a phase comparator. The other input of the phase comparator is the output signal of the voltage controlled oscillator. The phase comparator will output a dc signal proportional to the difference in phase between the two signals. When the structural member becomes damped, the phase comparator will go into saturation, thereby producing a voltage which can activate an alarm signal or other device.

Signal diversity arrangement for mobile reception

Abstract: The invention relates to a signal diversity arrangement for a mobile reception, comprising a receiver and a diversity processor, which receives the input signals and applies a different input signal to the receiver when interference occurs. The diversity processor comprises an interference detector operating in the analog mode and a comparator, to whose first input is applied the output signal of the interference detector and to whose senond input is applied a suitably set voltage V1. The comparator shows on its output the occurence of interference by way of a binary signal when the threshold voltage V at the second input is exceeded. No less than one integrator is available having a discharging time constant, to whose input is applied a signal derived from the interference signal and whose time of integration is equal to the switching interval of one of the input signals and whose output signal is added to either the interference signal at the first comparator input such that when the interference is increased the total voltage at the first input of the comparator is increased also, or the output signal is applied to the second comparator input such that the threshold voltage is lowered when the interference rises. In the case of a series of integrators whose inputs each receive a signal derived from the interference signal of the associated input signal, the output signals of these integrators are each time applied to one of the comparator inputs and the threshold voltage V is changed each time in accordance with the interference signal during the switching interval.

Receiver for optical digital signals having different amplitudes

Abstract: A receiver for optical digital signals which have different amplitudes which comprises a transimpedance amplifier which has a photodiode connected to its input and which produces an output that is supplied to one of the inputs of a comparator. Oppositely poled diodes are connected between the inputs of the comparator and a reference voltage is supplied to the other input of the comparator and a capacitor is connected to the other input of the comparator which together with a resistor comprises a differentiator for the output signals of the transimpedance amplifier.

Frequency doubling circuit for out-of-phase, incremental pulses of an angular step generator

Abstract: The invention relates to a frequency doubling circuit for the sinusoidal and cosinusoidal signals emitted by an angular step generator. According to the invention, four comparators are provided, while the sinusoidal signal is located at the non-inverting inputs of the first and the second comparator, the inverted sinusoidal signal is located at the inverting input of the first comparator and at the non-inverting input of the fourth comparator, the cosinusoidal signal at the non-inverting input of the third comparator, and the inverted cosinusoidal signal at the inverting inputs of the second to fourth comparator. Further, two XOR gates are provided, while the outputs of the first and third comparator are located at the inputs of the first XOR gate and the outputs of the second and fourth comparator are located at the inputs of the second XOR gate.

Circuit arrangement for generating a clock signal which is synchronous in respect of frequency to a reference frequency

Abstract: In addition to a filter phase comparator, an integrator, a first filter and a voltage-controlled oscillator of relatively low stability and having a wide pull-in range, a circuit arrangement for generating a clock signal comprises a frequency generator of high stability having a narrow pull-in range, a second phase comparator and second and third filters. The first phase comparator is supplied with the reference frequency and the clock signal emitted by the voltage-controlled oscillator. The second phase comparator is supplied with the clock signal and a normal frequency generated by a normal frequency generator. In the event of the failure of the reference frequency or the overshooting of predetermined phase difference values, a regulating circuit formed by the second phase comparator, the second filter, the third filter and the voltage-controlled oscillator is closed.

NMOS analog voltage comparator

Abstract: An NMOS analog voltage comparator is disclosed having two matching cascaded inverter-pairs. The comparator has fast response time, is not sensitive to temperature variations while operating, and operates independent of integrated circuit parameter variations encountered during circuit manufacture.

Nonquadrature correction circuit

Abstract: A phase comparator has additional circuitry for correcting nonquadrature error during operation of the comparator. The phase comparator has a 90 degree power divider which receives a reference signal input and produces two reference outputs, one shifted 90 degrees out of phase with the other. The phase comparator also has a zero degree power divider which receives a return signal, such as a reflected signal of a radar transmitter unit. The outputs of the power dividers are applied to mixers and filters to result in an I video output whose frequency is the difference between the reference and signal input frequencies, and a Q video output which is identical in frequency but shifted 90 degrees. The correction circuit includes a frequency trap connected to the reference input and tunable about a center frequency of approximately the third harmonic of the fundamental reference frequency. While the phase comparator is operating, the trap is detuned from the center frequency while the phase error is monitored until the phase error nears zero. Band pass filter means which electrically isolate the power divider from external circuitry can improve operation.

Reset and synchronization interface circuit

Abstract: A reset and synchronization interface circuit (10) for use in a subscriber power controller (7) includes a reset circuit portion (12) and a synchronization circuit portion (14). The reset circuit portion is formed of a first comparator (16), a second comparator (18), and an output network (20) for generating a reset signal. The first comparator compares an input signal with the reference voltage to produce a first output signal and a second output signal. The second comparator compares the first output signal from the first comparator with the reference voltage to produce a third output signal. The output network inverts and shifts the level of the third output signal to produce the reset signal. The synchronization circuit portion is formed of a third comparator (22) and an AND logic gate (24) for generating a modified synchronizing signal. The third comparator inverts a synchronizing clock signal to generate a complementary synchronizing clock signal. The AND logic gate combines logically the second output signal from the first comparator with the complementary synchronizing clock signal to produce the modified synchronizing signal.

CMOS binary threshold comparator

Abstract: A binary threshold comparator is disclosed for first and second binary numbers, wherein the first is variable and the second is a threshold or reference, with the complement of the second number available. The comparator may be a high threshold (greater/equal) comparator or a low threshold (less/equal) comparator. It comprises 5 MOSFETs per bit stage, with two additional MOSFETs per comparator for high/low determination and carry in precharge. A particular multi-bit embodiment of the comparator has a modified most significant bit stage which provides a complement of the normal output when the most significant bits of the numbers to be compared are different to prevent an immediate reversal of comparator output when a counter containing the variable number rolls over from all ones to all zeros or vice versa.

Frequency-doubling circuit for phase-shifted incremental pulses of an angle encoder

Abstract: Die Erfindung betrifft eine Frequenzverdopplungsschaltung fur die von einem Winkelschrittgeber abgegebenen Sinus- und Kosinus-Signale. The invention relates to a frequency-doubling circuit for the output from an angle encoder sine and cosine signals. Erfinsungsgmeas sind vier Komparatoren vorgesehen, wobei das Sinus-Signal an den nichtinvertierenden Eingangen des ersten und des zweiten Komparators anliegt, das invertierte Sinus-Signal am invertierenden Eingang des ersten Komparators und am nichtinvertierenden Eingang des vierten Komparators anliegt, das Kosinus-Signal am nichtinvertierenden Eingang des dritten Komparators anliegt, und das invertierende Kosinus-Signal an den ivnertierenden Eingangen des zweiten bis vierten Komparators anliegt. Erfinsungsgmeas four comparators are provided, wherein the sine wave signal is applied to the non-inverting inputs of the first and of the second comparator is applied the inverted sine signal at the inverting input of the first comparator and at the noninverting input of the fourth comparator, the cosine signal at the noninverting input the third comparator is applied, and the inverting signal to the cosine ivnertierenden inputs of the second to fourth comparator is applied. Weiter sind zwei XOR-Gatter vorgesehen, wobei die Ausgange des ersten und dritten Komparators an den Eingangen des ersten XOR-Gatters und die Ausgange des zweiten und vierten Komparators an den Eingangen des zweiten XOR-Gatters anliegen. Furthermore, two XOR gates are provided, wherein the outputs of the first and third comparator at the inputs of the first XOR gate and the outputs of the second and fourth comparator at the inputs of the second XOR gate abut.

Low voltage phase comparator

Abstract: A phase comparator which comprises a differential amplifier; and a first and a second active load circuit each comprising a current mirror circuit and from which is derived an output signal which is reversed in phase with respect to the output of the differential amplifier. The outputs of the respective active load circuits are superimposed upon each other through other current mirror circuits, and an output resulting from the superimposition is alternately provided based on rectangular waveform signals which are reversed in phase with respect to each other. By smoothing the output, a DC output corresponding to the phase shift of input signal from the rectangular waveform signals is produced. The phase comparator comprises a combination of transistors and diodes which are cascode-connected to each other, and thus is operable with a predetermined voltage as low a 1 V or less.

Receiver for optical digital signals having various amplitudes

Abstract: Die Erfindung bezieht sich auf einen Empfanger fur optische Digitalsignale mit unterschiedlicher Amplitude, mit einem Transimpedanz-Verstarker (TIV 1), an dessen Eingang eine Fotodiode (FD) angeschaltet ist, und dessen Ausgang an einen Eingang eines Komparators (K) angeschaltet ist. The invention relates to a receiver for optical digital signals with different amplitude, with a transimpedance amplifier (TIV 1), at whose input a photodiode (FD) is turned on, and its output to an input of a comparator (K) is turned on. Erfindungsgemas sind zwischen die Eingange des Komparators antiparallele Dioden (D1, D2) geschaltet, liegt eine Referenzspannung (VR) am anderen Eingang des Komparators an, und ist eine Kapazitat (C1) ebenfalls am anderen Eingang des Komparators angeschaltet, die zusammen mit einem Widerstand (R2) fur die Ausgangssignale des Transimpedanz-Verstarkers ein Differenzierglied darstellt. According to the invention between the inputs of the comparator anti-parallel diodes (D1, D2) connected, is situated on a reference voltage (VR) at the other input of the comparator, and a capacitor (C1) is also connected at the other input of the comparator, which (together with a resistor R2) is a differentiating element for the output signals of the transimpedance amplifier.

Analysis of reference-tap-voltage fluctuation in flash A/D converter

Abstract: To improve the speed and accuracy of the CMOS flash A/D converter using a copper-type comparator, an analysis has been performed for the voltage variation at each reference terminal of the ladder resistor providing a reference voltage. A model has been developed in which the circuit made of the ladder resistor and the input capacitance of the comparator is treated as a distributed network. A theoretical formula is derived which analytically provides transient behavior of each reference terminal voltage due to change in the comparator. With this formula, it is found that the maximum error of the reference terminal voltage occurs when the input voltage is either 0 or V ref. The error decreases exponentially with reduction of ladder resistors and comparator input capacitances and with increase of time. It is found that the product of the ladder resistor and the comparator input capacitance between adjacent terminals must be less than 5 × 10−13 F.Ω in order to obtain an 8 bit A/D converter with 20 MS/s. Variation is decreased if the midpoint of the ladder resistor is fixed. For instance, when the midpoint is fixed, the product of the ladder resistor and the comparator input capacitance is allowed to increase up to 2 × 10−12 F.Ω.

Semiconductor type pressure detector

Abstract: PURPOSE: To make the apparatus small and applicable as pressure switch, by integrating a pressure sensor, an amplifier and a comparator on the same semiconductor chip. CONSTITUTION: An output voltage of a semiconductor pressure sensor 8 is amplified 9 to a practical level to be drawn at a terminal 10. An output voltage of the amplifier 9 is compared with an internal reference voltage by a comparator 11 to output an voltage 'L' or 'H' at terminal 12. Then, the reference voltage is changed by a value of a resistance externally attached to a terminal 13. The comparator 11 has a hysteresis characteristic, the range of which is changed by a value of a resistance externally attached to a terminal 14. The sensor 8, the amplifier 9 and the comparator 11 are all integrated on the same conductor chip to make characteristic of a small semiconductor pressure sensor work spatially to the fullest. In the application, this ensures immediate availability of a practical output voltage in use as pressure sensor and also enables the selection of operation level and the alteration of hysteresis range by an external resistance in use as pressure switch. COPYRIGHT: (C)1988,JPO&Japio

Analog-to-digital converter with a capacitiv network

Abstract: To improve the dynamic response of an analog-digital converter based on the principle of charge distribution with a weighted capacitive network (C to C/2 ) and a following connected comparator (K), a coupling capacitor (Ck) is connected between the capacitive network (C to C/ ) and the comparator (K). In this way, only the coupling capacitor (Ck) needs to be charged during the offset compensation of the comparator (K) in series with the capacitive network (C to C/2 ). A differential structure for the analog-digital converter can be simply implemented with a second coupling capacitor (Ck1) at the second input of the comparator (K). … …

A comparator for comparing differential input signals and method therefor

Abstract: A high speed two micron CMOS comparator uses an input differential stage (11) having feedback current mirror loads (18, 20) providing high speed current signals to an output cascode stage (28). Current mirror arrangement provide fast signal propagation through the comparator. Hysteresis is established by the output of the comparator positively fedback through a similar feedback differential stage (42) superimposing controlled current signals into the cascode stage. Hysteresis of the output signal respecting a differential input signal is controlled by the ratio of bias currents of internal current sources which ratio is relatively insensitive to temperature changes.

Daisy chain collision detection circuit

Abstract: A daisy chain collision detection circuit for use with a StarLAN coded data transceiver includes a voltage comparator having an inverting input, a non-inverting input and an output. The inverting input of the voltage comparator is responsive to differential output voltages from a differential line drive and transient spike voltages from the primary of an isolation transformer. A charging capacitor is connected to the non-inverting input of the voltage comparator. The capacitor is charged to a reference voltage which is directly proportional to the peak voltage of the differential output voltages. The output of the voltage comparator provides an internal collision detection signal which is switched from a high logic level to a low logic level upon the occurrence of a daisy chain collision.

Device for controlling a circuit through an impedance

Abstract: Device for quickly and accurately controlling a current through a load impedance, for example a coil of a micro-stepping stepping motor, in which a comparator compares a reference signal with a current measuring signal and, dependent on the sign of the difference, makes the load impedance connect either to the one or to the other of two voltage sources, which are differently polarized with respect to each other, by means of a switching device. In order to avoid too quick a switching the comparator is controlled by an impulse sender, the comparator being able to change its output signal only during and/or a short time after a pulse has been received from the impulse sender.

A cascade comparator ADC using a magnetic modulator

Abstract: The precise ampere-turn comparator can be used as a most-significant bit digital-to-analog converter (DAC) and as an input comparator in the cascade comparator analog-to-digital converter (ADC). A 20-bit cascade comparator ADC can be easily constructed using a precise ampere-turn comparator, a low-cost IC-type DAC and a low-cost IC-type ADC. This paper explains the basic system and results of various experiments on a 20-bit cascade comparator ADC by the use of a second-harmonic-type magnetic modulator.