Showing papers on "Comparator applications published in 1988"

A 100-MHz pipelined CMOS comparator

Abstract: The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2- mu m CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. >

A high-speed CMOS comparator for use in an ADC

Abstract: A dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time. >

Comparator with extended common-mode input voltage range

Abstract: A comparator comprising two differential input stages (Q1 to Q4 and Q5 to Q8) which are connected in parallel and fed by a common constant circuit source (QB) whose current is passed either to both or only to the one or only to the other differential input stage, depending on whether the common-mode input voltage of the comparator is within, above or below a voltage range that is between the voltage values of the two poles (VC, VE) of a supply voltage source (B) of the comparator, and comprising a common current mirror circuit (Q9, Q10) which is associated with the outputs of both differential input stages and from which the comparator output signal is derived. At least one (Q1 to Q4) of the two differential input stages operates in common-base connection, with this differential input stage (Q1 and Q4) receiving its supply current from the common-mode input voltage source.

Bar code detector

Abstract: PURPOSE: To allow an analog signal to be always between the high level and low level of a binarization signal and to execute exact binarization by obtaining a signal to load hysteresis to the peak holding circuit output of a floating binarization circuit from the power source voltage of a comparator. CONSTITUTION: An analog signal A executes the charge/discharge of a capacitor 4 and generates a comparing reference value B. The comparing reference value B is inputted to a non-inverting input D of a comparator 1. Since the comparing reference value B is passed through a diode 2, the change of a signal is delayed to the analog signal A only by the dead zone part of the diode. Thus, when the analog signal A is changed from a peak by the dead zone part, the analog signal A and the comparing reference value B are across and the output of the comparator 1 is switched. Since the output of the comparator 1 is pulled up by the power source of the comparator 1, a binarization signal C is switched at the power source voltage level of the comparator 1. When the binarization signal C is switched, the hysteresis is loaded through a resistor 5 for hysteresis to the non-inverting input D and the binarization signal C is prevented from being oscillated. COPYRIGHT: (C)1990,JPO&Japio

Comparator unit for a flash analog-to-digital converter

Abstract: A high speed comparator unit for a flash A/D converter in which a bank of comparator units compare simultaneously an analog input voltage with equally spaced reference voltages, and an encoder ROM produces digital signals based on the comparator unit's outputs. The comparator unit includes a two-stage cascode configuration and a level shifter configuration which effectively reduces the miller-effect of the comparator unit.

Phase and frequency comparator circuit for phase locked loop

Abstract: A phase and frequency detector circuit includes both a phase comparator such as an exclusive-OR gate possessing high phase sensitivity, and a frequency-phase comparator that is sensitive to differences in frequency. The outputs of these circuits are combined to provide a single output signal offering both frequency discrimination and sharp phase discrimination.

Microprocessor-controlled amplifier

Abstract: An amplifier circuit having an FET connected in series with a resistor coupled to a constant voltage source, coupled between a pair of amplifiers, such as audio amplifiers in a two-stage amplifying circuit. The FET specifically and directly determines the amount of gain of the two-stage amplifier, or the like. RDS of the FET is continually monitored by its connection to one input of an amplifier serving as a comparator, with the other input thereof serving as a reference voltage derived from a modulated signal emanating from a microprocessor. Each of the signals VDS, and the reference from the microprocessor is filtered through a low pass filter to remove the audio, or other cyclical signals, and, in the latter case, in order to provide a substantially constant reference voltage to the input of the comparator. The output of the comparator is coupled to an RC circuit, the capacitor thereof being continually charged and discharged in response to the state of the output of the comparator. The output from the RC circuit is coupled to the FET to define the gate voltage of VGS thereof, which in turn determines the value of RDS , to thereby continually alter RDS, to thereby provide the gain so desired and specifically required in the amplifying circuitry. Such value is inherently defined by the modulated reference signal emanating from the microprocessor.

Voltage comparator having hysteresis characteristics

Abstract: A voltage comparator circuit with hysteresis characteristics includes a voltage comparator circuit for comparing an input signal voltage with a comparison reference voltage and outputting a comparison result, a resistor element connected between the reference potential terminal and the comparison reference voltage input terminal of the voltage comparator circuit, a first constant current source for supplying current into the comparison reference voltage terminal and a second constant current source for deriving current out of the comparison reference voltage input terminal, and a control circuit for selectively activating one of the first and second current sources, in accordance with the logic level of an output of the voltage comparator circuit.

Signal averaging for optical time domain relectometers

Abstract: Means for digitizing and averaging the signals in an optical time domain reflectometer are disclosed in which a comparator is used to output a 1 or 0 into an arbitrarily large number of successive time-bins. In each comparator choice, the analog voltage signal from the OTDR receiver is compared to a selected analog voltage value. The selected value is chosen randomly from the range of available signals in the interval of interest; and each such valve is used to provide a comparator input into every time-bin during one waveform recovery. Each comparator output signal (1 or 0) is directed to a separate time-bin (counter), representing the desired time interval (resolution). Subsequent comparator output signals are added to each time bin. The waveform recovery runs are repeated until an acceptable signal-to-noise result is achieved. Each waveform run uses a different voltage for comparison to the receiver voltage. Such comparison voltages may be selected by a random generator; or an ordered series of comparison voltages may be used.

Performance of fast monolithic ECL voltage comparators in constant-fraction discriminators and other timing circuits

Abstract: Timing errors caused by voltage comparator operation are investigated in detail for constant-fraction discriminators and other timing circuits. These errors result from changing comparator response time for input signals with different slopes (voltage/time) and different levels. Comparator response time is analyzed for a modern high-speed ECL voltage comparator using the SPICE circuit analysis program, which models the complex nonlinearities present in comparator operation. The simulated response time for a -90-mV to 10-mV step input is slightly larger than the specified comparator performance, indicating a conservative analysis. Response time is presented for a variety of input signals and supports a comparator response-time model that consists of a charge-sensitivity (variable-time) delay component and a fixed-delay component SPICE circuit simulation is extended to simulate comparator operation in a constant-fraction discriminator circuit. >

CMOS differential comparator with offset voltage

Abstract: To generate an impressed offset voltage for a differential comparator, a circuit arrangement in complementary MOS technology is proposed in which the offset voltage is impressed by the design of the transistors. For this purpose, the geometries (W/L) of the input differential transistors (M1, M2; M11, M12) are designed symmetrically and geometries (W/L) of the associated load transistors (M3, M4; M13, M14) are designed asymmetrically, and the geometries (W/L) of the transistors of the output driver circuit (M6 to M9; M16, M17) are matched to the operating characteristic thus generated in the differential comparator.

Phase locked loop with optimally controlled bandwidth

Abstract: A phase locked loop has a digital phase comparator, a filter with multiple bandwidths, a voltage controlled oscillator and a frequency divider connected to the phase comparator to complete the loop. Control circuitry is coupled to both the phase comparator and filter for controlling switching between a wide bandwidth and a narrow bandwidth. The switching in bandwidth is in response to either detecting when the output signal is within a predetermined range of the reference frequency for a predetermined time period or detecting when the output signal exceeds and falls below the reference frequency a predetermined number of times. The control circuit is implemented with circuitry which accurately detects either condition and is capable of blocking any premature change of bandwidth.

High-speed accurate CMOS comparator

Abstract: A high-speed CMOS comparator for A/D convertors is discussed. The circuit has high resolution (better than 5 mV) in combination with high speed (clock frequencies up to 50 MHz). The advantage of the proposed structure is that no clock feedthrough is injected to the input, only one switch in a symmetrical structure is used and the effect of any current biasing on the comparator speed has been reduced.

Comparator circuit using resonant-tunneling transistor

Abstract: A comparator circuit comprises a differential amplifier supplied with a reference signal and an input signal. A resonant-tunneling transistor has a base supplied with an output signal of the differential amplifier. A collector is connected to a first power supply source via a resistor. An emitter is connected to a second power supply source. Therefore, it is possible to simplify a circuit configuration of the comparator circuit and to improve an operation speed of the comparator circuit by outputting an output signal from a connection portion between the resistor and the collector of the transistor.

Input apparatus of electronic system for extracting pitch data from input waveform signal

Abstract: An input waveform signal is converted into a digital peak value signal by an A/D converter, and the digital peak value signal is input to one input terminal A of a comparator. The other input terminal B of the comparator receives a preset digital peak value signal from a memory. These input signals are compared by the comparator. The content of the memory is reduced at a predetermined rate. If the comparator detects that the currently input waveform level is larger than the continuously reduced level of the memory, i.e., if A>B, a new waveform level is loaded in the memory. As a result, the output from the comparator is inverted. That is, condition A>B is changed into condition A

Cache tag comparator with read mode and compare mode

Abstract: A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.

Detection circuit for a video tape recorder signal

Abstract: A detection circuit for a video tape recorder signal on the input of a TV set connected to a line synchronization separating circuit (11) in turn connected to a PLL (12) comprises a first phase comparator (15), the PLL (12) exhibiting a first time constant (I1, C1) corresponding to an operation on a normal TV signal. This circuit further comprises a switch (20) for switching the PLL on a second time constant (3I1, C1) shorter than the first one, a second phase comparator (22) for comparing the input and output phases of the first phase comparator, the second phase comparator being associated with a third time constant (I2, C2) shorter than the first and second ones, a threshold comparator (24) supplying to the switch (20) a control signal when the comparator output (22) is outside determined limits.

Nonhysteretic periodic-threshold SQUID comparator and A/D converter

Abstract: A SQUID comparator having two junctions configured so that its operating characteristics are substantially the same as a single junction SQUID. In particular, the ratio of the critical current of these two junctions is selected to avoid introduction of hysteresis. An n-bit single pass comparator is present that can produce 4-bit A/D conversion up to 10 GHz. A method is implemented to remove effects of dynamic hysteresis by use complementary comparators.

Motor rotation speed controlling apparatus

Abstract: The present invention is directed to a motor rotation speed controlling apparatus including a comparator, a detecting circuit for detecting a feedback signal of a motor, a motor driving transistor, and a circuit for changing the level of a constant voltage fed to the comparator. The comparator compares a saw-tooth voltage with a constant voltage and outputs a signal which has a duty cycle corresponding to the result of the comparison. The motor driving transistor drives the motor in response to the output signal from the comparator. To change the duty cycle of the output signal from the comparator, a circuit is used that changes the level of the constant voltage in response to a feedback signal detected by the detecting circuit.

Complementary voltage comparator

Abstract: A complementary voltage comparator is described wherein a CMOS operational amplifier having an input stage comprising N-channel field effect transistors is coupled with a CMOS operational amplifier having an input stage comprising P-channel field effect transistors. The outputs of the operational amplifiers are converted to currents and combined to indicate the relative magnitudes of the voltages being compared. This configuration allows the range of input voltages to vary over the full range of supply voltages and negates the need for offset correction.

Automatically stabilized latched differential comparator with single clock

Abstract: A differential comparator, working with microwaves and using only one clock, is disclosed. This comparator has a differential amplifier and a divergence circuit in which are included two voltage level translators. The coupling between the amplifier and the divergence circuit is made at the gates of the load transistors of the divergence circuit. Two insulation transistors, working in either saturated mode or resistive mode, are used to provide the amplifier with an automatic control loop which stabilizes all the rest voltages. The clock signal, applied to two transistors which short circuit the two feedback transistors of the divergence circuit, controls the passage from the measuring phase to the divergence phase.

Circuit for sensing voltages beyond the supply voltage of the sensing circuit

Abstract: A voltage sensing circuit wherein voltages that appear at first and second sensing nodes are converted into first and second currents which are proportional to their respective voltages. A comparing circuit compares the first current to the second current and generates a difference current proportional to the difference between the magnitudes of the two currents. A rectifier circuit rectifies the difference current, and the difference current is added to a reference current. The combined current is applied to the first input terminal of a comparator. The second input terminal of the comparator is coupled to a reference voltage, and the comparator indicates when the voltage created from the combined currents exceeds the reference voltage.

Threshold detecting battery protection circuitry

Abstract: A power shutdown circuit includes an electronic latch circuit connected in series with a monitored power supply and comparator input and power terminals. The output terminal of the comparator is coupled to the control terminal of the latch. When a monitored signal magnitude crosses a threshold, the comparator provides a control signal which renders the latch nonconductive. A main switch device also connected to an output of the latch responds to the nonconductive state thereof to remove power from an electrical load.

Radiation detector circuit having a 1-bit quantized output

Abstract: Radiation detectors are mounted in an optic focal plane of an infrared radiation sensor system. The radiation detectors produce output signals indicating detected radiation. The output signals are sampled by a sample-and-hold circuit and passed to a 1-bit comparator. The comparator produces a 1-bit signal at a high voltage level for samples of the output signal that are greater than a reference voltage and at a low voltage level for samples of the output signal that are less than the reference voltage. In this manner, the comparator reduces the effects of any gamma spikes on the measurement of intensity of radiation. The 1-bit signal is less susceptible to effects of interference than analog signals in conventional systems and the 1-bit comparator produces this 1-bit signal without consuming a great deal of electrical power. A multiplexor carries such 1-bit signals from the focal plane to a processor over less wires than in conventional systems. The processor receives and integrates the 1-bit signals and produces an output that indicates intensity and angle of detected radiation.

A 10-bit 5 Msample/sec CMOS 2-step flash ADC

Abstract: A 10-bit, 5-Msample/s, two-step flash A/D (analog-to-digital) converter fabricated in a 1.6- mu m CMOS process is described. With minimal capacitor-matching requirements and comparator offset-voltage cancellation, the architecture is monotonic. To minimize charge-injection errors, the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000 and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54k square mils. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

Comparator circuit operable for a wide range of input signal

Abstract: An improved comparator circuit which can operate stably against noise or fluctuation in a power supply is disclosed. The comparator circuit includes a differential amplifier having first and second input terminal, a first diode for biasing the first input terminal at a constant voltage, a second diode coupled between the first and second input terminals, and means for gradually changing the potential at the first input terminal towards the above constant voltage.

Duty cycle controller for horizontal synchronization signals in a television receiver

Abstract: A pulse generator of controllable duty cycle for horizontal synchronization signals in a television receiver is provided. The pulse generator broadly comprises a duty cycle control loop with a comparator means having an output coupled to the output of the pulse generator, a duty cycle detector means coupled to the comparator means for detecting the duty cycle of the output of the comparator means, a duty cycle control means for setting the duty cycle of the output of the comparator means to a desired value, and an error feedback means coupled to the duty cycle control means, the duty cycle detector means, and the comparator means. Duty cycle control is achieved either by a control pulse or by means of a voltage divider which is coupled between a supply voltage and ground, with a voltage divider node connected to the base of the error feedback transistor. The comparator means, the duty cycle of which is the duty cycle of the pulse generator, is turned on by means of the voltage at its base dropping 0.7 V below the voltage at its emitter. The rate of change of the base voltage is in turn controlled by an RC time constant and the error feedback means. The comparator means is turned off by means of an edge trigger means which receives the horizontal synchronization signal as an input.

Zero-cross point detecting circuit

Abstract: For the purpose of detection of a zero-cross point of an input signal, the input is applied to one of two input terminals of a comparator which has an inverted input terminal and a non-inverted input terminal, the same bias voltage is applied to each of two input terminals of the comparator from a bias voltage supplying circuit, the value of the bias voltage applied to either the inverted input terminal or the non-inverted input terminal of the comparator is changed by a bias voltage changing circuit from that determined by the bias voltage supplying circuit depending on whether the output of the comparator is in its high or low level, the output of the comparator is a detection signal of the zero-cross point of the input signal.

CMOS comparator bias voltage generator

Abstract: An apparatus for generating a CMOS comparator bias voltage for a CMOS comparator includes a dummy comparator having a negative input and a positive input coupled together to receive a common mode reference voltage corresponding to the common mode input voltage of the CMOS comparator. The dummy comparator also includes a bias input and an output. The apparatus for generating a CMOS comparator bias voltage further includes a bias amplifier having a negative input coupled to the output of the dummy comparator, a positive input for receiving a threshold reference voltage corresponding to the input threshold of the next stage driven by the CMOS comparator, and an output coupled to the bias input of said dummy comparator to form a comparator bias voltage.

Differential comparator with reduced delay variation.

Abstract: A differential comparator (16) includes a matched pair of transistors (Q1, Q2) having emitters coupled to a current source (22) through a pair of emitter-degeneration resistors (R1, R2) and having collectors coupled to a voltage source through a pair of load resistors (R3, R4) such that a differential input voltage (Vbd) applied across the transistor bases produces an amplified differential output voltage (Vdo) across the transistor collectors. The emitter-degeneration resistors (R1, R2) are sized so that a differential input current (Ibd) produced in the bases of the amplifier transistors (Q1, Q2) is substantially constant over a range of differential input voltage (Vbd) including the range for which the amplifier transistors (Q1, Q2) remain active when the input voltage (Vin) varies with constant slew rate, thereby minimizing variation in input capacitance with respect to input voltage (Vin). This in turn minimizes variation in time delay between the comparator differential input and output voltages with respect to input voltage slew rate.