Showing papers on "Comparator applications published in 1994"

Apparatus and method for capture detection in a cardiac stimulator

Abstract: A capture detection circuit for an implantable cardiac stimulator. A signal detected by an electrode in the heart following delivery of a stimulating pulse is amplified, bandpass and highpass filtered, rectified, integrated over a selected window of time starting at a selected delay after delivery of the stimulating pulse, and applied to two comparators having different reference values. If the integrated signal exceeds the first reference value, the first comparator output goes high. If the integrated signal exceeds the second reference value, the second comparator goes high. If both comparators remain low, non-capture is indicated. If the first comparator goes high and the second comparator remains low, capture is indicated. If the second comparator goes high, an intrinsic contraction is indicated. The window of integration can be extended to distinguish capture from intrinsic contraction.

DC-to-DC converter operating in a discontinuous mode

Abstract: A converter employs a comparator sensing the current through an output diode, for generating a confirmation signal of an OFF state of the switch until the discharge current of the inductor toward the user circuit and the external filter capacitance has become null, thus ensuring the operation in a discontinuous mode under any condition. A turn-off signal of the switch is provided by another comparator which, instead of the voltage on a sensing resistance connected in series with the switch, may sense the voltage across the switch itself. This latter embodiment is particularly suited in case of an output MOS transistor and the circuit comprises means for masking for a preset period of time the turn-off signal produced by said comparator, in order to allow a predefined turn-on phase of the switch. Enabling of the turn-on of the switch is conventionally provided by a dedicated (third) comparator of the output voltage. The circuit does not require the use of an error amplifier, for the compensation of which special complex integratable circuits or alternatively access to the output node of the error amplifier through a dedicated pin may be needed. Neither a local oscillator for turning off the switch is needed. The circuit is simple and suited for integration in large complex system chips, where there is a limited availability of pins and silicon area. Different embodiments are described.

Soil moisture sensor

Abstract: Moisture sensor devices, systems and methods of making and using the same employ a pair of elongated, probe-like, conductive sensor elements, coupled as part of an LC oscillator circuit. The use of an LC oscillator circuit can minimize adverse effects of conductivity variances in the medium being monitored, because the resistance of the medium (and, thus, the medium's conductivity) has minimal or no effect on the resonant frequency of an LC oscillator circuit. An LC oscillator circuit of suitable stability for moisture sensing applications includes first and second comparators connected such that the output of the first comparator is coupled to the inverting input of the second comparator. An inductor is coupled between the output and inverting input of the first comparator and a capacitance C is provided between the output of the second comparator and the inverting input of the first comparator. The capacitance C is composed primarily of the capacitance value provided by the pair of probe-like sensor elements and the dielectric constant of the medium in which the probe-like sensor elements are disposed. The capacitance is averaged over the length of the probe-like sensor elements.

Differential comparator circuit

Abstract: A differential comparator circuit for an Analog-to-Digital Converter (ADC) or other application includes a plurality of differential comparators and a plurality of offset voltage generators. Each comparator includes first and second differentially connected transistor pairs having equal and opposite voltage offsets. First and second offset control transistors are connected in series with the transistor pairs respectively. The offset voltage generators generate offset voltages corresponding to reference voltages which are compared with a differential input voltage by the comparators. Each offset voltage is applied to the offset control transistors of at least one comparator to set the overall voltage offset of the comparator to a value corresponding to the respective reference voltage. The number of offset voltage generators required in an ADC application can be reduced by a factor of approximately two by applying the offset voltage from each offset voltage generator to two comparators with opposite logical sense such that positive and negative offset voltages are produced by each offset voltage generator.

Comparator circuit for decreasing shoot-through current on power switches

Abstract: A low power, break before make output circuit includes an output transistor pair 12 and 14, a first control circuit 20, a second control circuit 22, a first comparator 16, and a second comparator 18. First control circuit 20 has a first input coupled to a first digital control input and an output coupled to a control terminal of a first transistor 12 in the output transistor pair. Second control circuit 22 has a first input coupled to a second digital control input and an output coupled to a control terminal of a second transistor 14 in the output transistor pair. First comparator 16 has an input connected to the output of first control circuit 20 and an output connected to the second input of second control circuit 22. First comparator 16 compares a voltage at the control terminal of first transistor 12 to a first predetermined voltage and formulates a voltage at its output in response to the comparison. Second comparator 18 has an input connected to the output of second control circuit 22 and an output connected to the second input of first control circuit 20. Second comparator 18 compares a voltage at the control terminal of second transistor 14 to a second predetermined voltage and formulates a voltage at its output in response to the comparison. The voltages at the output of first comparator 16 and second comparator 18 influence the outputs of first control circuit 20 and second control circuit 22 thereby ensuring that first transistor 12 is not conducting when second transistor 14 is activated.

Digital interface circuit with dual switching points for increased speed

Abstract: A buffer, driver, or level-shifting circuit having an input connected to signal inputs of a pair of comparators and an output connected between a pair of pull-up and pull-down transistors controlled by the comparators. A first reference voltage applied to the reference input of the comparator controlling the pull-up transistor is selected to be less than the nominal transition point of the circuit, while a second reference voltage applied to the reference input of the comparator controlling the pull-down transistor is selected to be greater than the nominal transition point of the circuit, thereby allowing the circuit to recognize the beginning of signal transitions on the its input sooner. The comparators are differential amplifiers which are enableable and disableable in response to a feedback signal from the circuit's output in order to reduce current consumption during transitions. When the output is high, the comparator controlling pull-down is enabled, while the comparator controlling pull-up is disabled. When the output is low, the comparator controlling pull-up is enabled, while the comparator controlling pull-down is disabled. Undershoot and overshoot control circuitry may be provided by replacing the single pull-up transistor, pull-down transistor, or both with pairs of parallel transistors whose combined conductance is comparable to that of the replaced transistor. One of the parallel transistors is turned off after the nominal transition point has been reached on the circuit's output, thus slowing pull-down or pull-up during the latter part of the transition when speed no longer matters.

A clock generator and phase comparator for use in such a clock generator

Abstract: 1. A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.

Micro power R-C relaxation oscillator

Abstract: An R-C relaxation oscillator having two comparators and a silicon controlled rectifier dissipates very low average power without resulting in frequency instabilities due to circuit propagation delays. A timing capacitor CT is charged through a timing resistor RT. The first comparator compares the voltage across the timing capacitor with an upper threshold voltage VTH. When the voltage across the timing capacitor crosses the upper threshold voltage, the comparator turns on the silicon controlled rectifier, which causes the capacitor to discharge the voltage that it has stored. The second comparator turns off the silicon controlled rectifier when the voltage across the timing capacitor falls below a lower threshold voltage VTL. The silicon controlled rectifier also provides boosted comparator bias current during the discharge phase, enabling the second comparator to respond quickly to the lower threshold voltage crossing and allowing fast capacitor discharge (therefore narrow clock pulses) and increasing frequency stability.

True hysteresis window comparator for use in monitoring changes in switch resistance

Abstract: Electronic circuitry is disclosed for interfacing with a plurality of two-position switches to determine if each switch is opened, closed or faulty to some extent. Each switch is connectable in series with a pull-up resistor and between two different voltage values. The switch provides an output voltage at the connection of one terminal of the switch with the pull-up resistor. This switch voltage is presented to both an inverting input of a first comparator and a non-inverting input of a second comparator. The non-inverting input of the first comparator has a reference voltage of a certain value applied thereto, while the inverting input of the second comparator has a reference voltage of a certain value also applied thereto, the reference voltage values being different so as to define a "window" or "dead band" region of voltage. The switch output voltage is compared to the reference voltages on the two comparators. If the switch is closed, the comparator outputs will assume certain states. On the other hand, if the switch is opened, the comparator outputs will assume the opposite states. Finally, if the switch is faulty such that a finite impedance value is developed across the terminals of the switch, the voltage value will then be generated which causes both comparator outputs to assume the same state, thereby indicating a faulty switch to subsequent signal processing circuitry.

A high-accuracy high-speed CMOS current comparator

Abstract: A high-accuracy high-speed current comparator is presented which has well-controlled input resistance and bias currents. Moreover, compared to previous high-speed solutions, it has an accuracy five times better with a lower power consumption. >

Low-voltage CMOS comparator with offset cancellation

Abstract: A CMOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

Method and apparatus for sensing an input current with a bridge circuit

Abstract: A current sensor includes first and second branches interconnected by a center conductor magnetically coupled to an annular current comparator for producing an output signal related, in magnitude and phase, to an input current. The input current divides, according to a predetermined relationship, between the first and second branches such that the current in the center conductor interconnecting the first and second branches is also related to the input current. A current is induced in the annular current comparator in relation to the current in the center conductor and, thus, in relation to the input current. Secondary windings are wound about and magnetically coupled to the annular current comparator for producing an output signal responsive to the current induced within the annular current comparator.

Analog to digital converter providing varying digital resolution

Abstract: An analog to digital converter which includes a resistive network for generating a number of first reference voltages related to each other by a first linear relationship and a number of second reference voltages related to each other by a second linear relationship, where the first linear relationship is different from the second linear relationship. Also included are first comparators which compare an analog signal to each one of the first reference voltages to produce specified first comparator signals where a respective comparator of the first comparators is provided for each of the first reference voltages. Second comparators are provided to compare the analog signal to each of the second reference voltages to produce second comparator signals where a respective comparator of the second comparators is provided for each one of the second reference voltages. Also included is an encoder to directly convert the first comparator signals and the second comparator signals to a linear digital encoded signal having respecting different quantization resolutions in different parts of its range.

Digital-to-pulse width converter utilizing a distributed pulse width

Abstract: A digital-to-analog converter includes a digital-to-pulse width converter that converts a desired digital set-point value to a corresponding signal having a pulse width indicative of the desired set-point value. The desired set-point value is fed to a comparator which compares that value to the current count value from a counter that is counting up in ascending integer order. However, instead of presenting the counter output signal lines to the comparator in a normal conventional manner wherein the count value of the counter is presented to the comparator in the conventional ascending integer order, the current value of the counter is presented to the comparator in other than a conventional ascending order. The result is a comparator output signal that transitions more than one time between binary logic levels. This effectively increases the frequency of the comparator output signal. An optimum connection of the counter output signal lines to the comparator can be achieved such that the comparator output signal is divided up into a series of binary logic level pulses that are distributed across the entire cycle time period of the counter. This results in a subsequent output of an integrator that has reduced ripple voltage amplitude.

Hysteresis comparator circuit for operation with a low voltage power supply

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

Offset-compensated low power current comparator

Abstract: A new current comparator based on a folded-cascode amplifier is presented. It has an excellent sensitivity of 20 nA and provides offset compensation, avoiding clock-feedthrough errors. The circuit dissipates only 30 µW and achieves a switching time better than 30 ns with a 0.5 µA input step current. Moreover, the bias current and the input impedance are well-controlled parameters.

Protective circuit for protecting transistor from thermal destruction

Abstract: An overheat protective circuit includes a first voltage generator generating a first voltage stabilized against a change of an operating temperature, a second voltage generator generating a second voltage changeable in accordance with a change of the operating temperature, a comparator having first and second inputs coupled to receive the first and second voltages, respectively, and a switching circuit responding to a first logic level of the output signal from the comparator to render a transistor to be protected non-conductive. This protective circuit further includes a control circuit which monitors a power voltage and controls, when the power voltage is in a predetermined range, the level at one of the first and second inputs of the comparator such that the comparator outputs its output signal having the second logic level to deactivate the switching circuit.

Battery charger device

Abstract: A battery charging device capable of charging any variety of rechargeable batteries and capable of being powered by either a 110 volt or a 220 volt A.C. power source. The battery charging device comprises an integrator circuit having a D.C. power source; a voltage comparator; a solid state relay; a D.C. output circuit; a positive voltage feedback circuit; and a negative voltage feedback circuit. The integrator circuit receives A.C. power from an A.C. power source and provides an output to the voltage comparator. The voltage comparator, in turn, is connected so as to provide an output to the solid state relay. The solid state relay preferably includes a zero voltage closing circuit and provides an output to the D.C. output circuit. The D.C. output circuit is connected to a battery-to-be-charged and provides an output D.C. voltage thereto. The D.C. output circuit is also connected to and provides outputs to the negative and positive feedback circuits which, in turn, provide feedback to the voltage comparator. Preferably, optical coupling devices connect the output from the voltage comparator to the solid state relay, as well as the positive and negative feedback circuits to the voltage comparator.

Multiple level parallel magnitude comparator

Abstract: A magnitude comparator is modified to compare the magnitudes of two large binary values more quickly and with minimum gate delays. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing magnitude comparator delay. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal. This circuitry, along with logic circuitry which indicates whether corresponding bit values within associated groups exactly match, defines a magnitude comparator block. Multiple magnitude blocks are used to facilitate the comparison of larger binary values. Each magnitude comparator block generates a compare output signal which, in turn, is an input to a corresponding gating element. Each gating element possesses a logic input signal, derived in part from its magnitude comparator block's match logic circuitry. The gating element logic input signals ensure that only the compare output signal of the magnitude comparator block having the highest order bits with magnitude difference will be allowed to propagate through as the final compare output signal.

Comparator having latched output when disabled from the power supply

Abstract: A comparator (10) operates in comparator mode or in static leakage current test mode as determined by a control signal. In the comparator mode, the comparator receives a differential input signal for amplification through an analog differential front-end comparator input stage (31). The output of the comparator input stage is presented as a single-ended signal that is applied to an input of a buffer (32). The buffer amplifies the single-ended signal to digital logic levels. In test mode, the control signal enables a feedback circuit (36-42) from the output of the buffer back to its input and disables the differential front-end comparator input stage by removing the power supply. The last valid data state present at the output of the buffer is thus latched back to its input to allow static leakage current testing of down-stream circuitry without interference from the comparator drawing large static currents.

Temperature compensated opto-electronic circuit and mouse using same

Abstract: A temperature compensated opto-electronic circuit structure including a emitter connected to one input of a comparator to provide a reference signal. A detector signal is applied to another input terminal of a comparator, and the output of the comparator is determined by a difference between the reference signal and the detector signal. As the temperature of the opto-electronic circuit increases and decreases, the reference signal is automatically adjusted due to the temperature-related forward voltage changes of the emitter.

Method and circuit for clamping the recirculation current in stator windings

Abstract: A circuit for clamping the voltage spike of a stator coil winding of a brushless direct current motor is disclosed. The circuit uses a comparator to monitor the voltage on a stator winding. When a voltage spike is detected, the comparator turns on the stator winding driver transistor to clamp the voltage spike. The comparator can be designed to trigger at a desired threshold voltage so that the threshold can optimized. Additionally, the comparator can be selectively disabled to trigger when voltage spikes are anticipated.

An accurate offset-compensated current comparator

Abstract: An offset-compensated current comparator is presented which provides an accuracy better than 30 nA. Moreover, the proposed topology allows a well-controlled input resistance and bias currents to be achieved. Simulated results from 2-/spl mu/m CMOS process are included.

Electronic security switching network

Abstract: The invention relates to an electronic security switching network having a key-like encoder (1), a plug holder (21), a code comparator (2), code recognition logic (7) and an output stage (18) having switches (15; 16) for the opening or commissioning function. The encoder has a clock frequency. The data transmission is carried out via the operating voltage supply lines of the encoder. The code comparator comprises an address comparator (3) and a data comparator (4) as well as memories (5; 6) assigned thereto. The code recognition logic recognises not only the correct code but also incorrect codes in a digital and analog manner, the latter being more likely to be recognised. An enable switch (15) of the output stage is actuated in the case of a correct code and an inhibit switch (16) in the case of incorrect codes. The two switches act in the opposite direction in the circuits to be switched.

Amorphous, thin film transistor driver/receiver circuit with hysteresis

Abstract: A driver circuit has hysteresis. The driver circuit includes a comparator circuit having first and second inputs and an output. The driver circuit also includes a variable voltage divider circuit coupled between the second input and the output of said comparator. The voltage divider circuit provides a first voltage to the second input of the comparator when the output of the comparator is at a second voltage, and a third voltage to the second input of the comparator when the output of the comparator is at a fourth voltage. Therefore, the output voltage of the comparator switches from the second to the fourth voltage when the voltage of a signal at the first input of the comparator rises above the first voltage, and the output voltage of the comparator switches from the fourth to the second voltage when the voltage of the signal at the first input of the comparator falls below the third voltage.

Frequency synthesizing apparatus for a communication system.

Abstract: A phase-locked loop frequency synthesizing apparatus has a voltage controlled oscillator (4) which is supplied with a control voltage derived from the output of a phase comparator (2) one input of which receives a reference frequency. A direct digital synthesizer (5) frequency-divides the output frequency signal with a non-integral decimal dividing function to produce a phase-comparative frequency signal for application to the other input of the phase comparator. The apparatus can be used in microwave, mobile or similar communications apparatus.

Input circuit for level-shifting TTL or CMOS to ECL signals

Abstract: An input circuit which converts an input signal to an output signal. A first level comparator has a first input to which the input signal is applied and a second input to which a first reference voltage is applied for comparison with the input signal, and an output which the output signal is manifested. A second level comparator has a first input connected to the first input of the first level comparator for application one input signal, and a second input to which a second reference voltage is applied for comparison with the input signal, with the second level comparator limiting the voltage at the first input of the first level comparator to substantially the second reference voltage whenever the input signal exceeds the second reference voltage as determined by the second level comparator.

Digital regenerative comparator

Abstract: A regenerative comparator provides the capability of operating faster than a traditional regenerative comparator and the hysteresis points can be individually set and fine tuned. The regenerative comparator includes a current mirror having an input transistor connected to first and second output transistors, a first and second reference current sources which are set at a first and second predetermined level, respectively. An outputs of the first and second output transistors are provided to the latch through an inverter. The output of the latch transitions from a first logical output state to a second logical output state when an input current increases from a magnitude less than the first predetermined level to a magnitude greater than the first predetermined level.

Neural n-port voltage comparator network

Abstract: Use is made of a neural architecture to realise a low-offset VLSI implementation of an n-port voltage comparator that performs the winner-take-all function. The circuit has a wide resolution (~50 dB), high gain, and a Hopfield-like positive feedback interconnect matrix, making possible the detection of very small perturbations (< 10 mV). The circuit is suitable for applications in Hamming and neural networks, vector quantisers, and other analogue parallel signal processing systems. The performance of the network was measured on a 32 input 2.0 µm CMOS circuit.

Detector for detecting heart depolarizations

Abstract: A compact, power-sparing detector for detecting heart polarizations is described. The detector has a first operational amplifier which uses sensed heart signals from a heart as an input signal. By means of feedback coupling via a second operational amplifier, a resistor and a capacitor, the system strives to achieve a minimum voltage gradient across the input terminals of the first operational amplifier. When an electrical signal with a signal slope corresponding to a heart depolarization arrives at the input terminal of the first operational amplifier, the second operational amplifier is no longer able to damp the input signal, and a peak output signal is sent from the first operational amplifier to each of a first comparator and a second comparator, respectively. The comparators produce an output signal as long as the output signal from the first operational amplifier is maximal, and the output signal from the comparators is integrated in a time integrator in order to determine the duration of the output signals. If a sufficient duration elapses, a detection signal is generated at the output terminal.